Modified the STM32 demo to use the bit definitions in the ST header file.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1050 35acf78f-673a-0410-8e92-d51de3d6d3f4master
gdisirio
parent
c9c4259de8
commit
255aea8bd2
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@ -46,28 +46,29 @@ void hwinit0(void) {
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* Clocks and PLL initialization.
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*/
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// HSI setup.
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RCC->CR = HSITRIM_RESET_BITS | CR_HSION_MASK;
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while (!(RCC->CR & CR_HSIRDY_MASK))
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RCC->CR = RCC_CR_HSITRIM_RESET_BITS | RCC_CR_HSION;
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while (!(RCC->CR & RCC_CR_HSIRDY))
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; // Waits until HSI stable, it should already be.
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// HSE setup.
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RCC->CR |= CR_HSEON_MASK;
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while (!(RCC->CR & CR_HSERDY_MASK))
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR & RCC_CR_HSERDY))
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; // Waits until HSE stable.
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// PLL setup.
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RCC->CFGR = PLLSRC_HSE_BITS | PLLPREBITS | PLLMULBITS;
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RCC->CR |= CR_PLLON_MASK;
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while (!(RCC->CR & CR_PLLRDY_MASK))
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RCC->CFGR = RCC_CFGR_PLLSRC_HSE_BITS | PLLPREBITS | PLLMULBITS;
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY))
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; // Waits until PLL stable.
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// Clock sources.
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RCC->CFGR |= HPRE_DIV1_BITS | PPRE1_DIV2_BITS | PPRE2_DIV2_BITS |
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ADCPRE_DIV8_BITS | USBPREBITS | MCO_DISABLED_BITS;
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RCC->CFGR |= RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE1_DIV2 |
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RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_ADCPRE_DIV8 |
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RCC_CFGR_MCO_NOCLOCK | USBPREBITS;
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/*
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* Flash setup and final clock selection.
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*/
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FLASH->ACR = FLASHBITS; // Flash wait states depending on clock.
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RCC->CFGR |= SW_PLL_BITS; // Switches on the PLL clock.
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while ((RCC->CFGR & CFGR_SWS_MASK) != SWS_PLL_BITS)
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RCC->CFGR |= RCC_CFGR_SW_PLL; // Switches on the PLL clock.
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while ((RCC->CFGR & RCC_CFGR_SW) != RCC_CFGR_SW_PLL)
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;
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/*
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@ -28,7 +28,6 @@
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#undef FALSE
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#undef TRUE
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#include "stm32f10x_map.h"
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#include "stm32f10x_rcc.h"
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#define FALSE 0
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#define TRUE (!FALSE)
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#endif
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@ -62,62 +61,25 @@
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#define PLLPREBITS ((PLLPRE - 1) << 17)
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#define PLLMULBITS ((PLLMUL - 2) << 18)
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#ifdef SYSCLK_48
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#define USBPREBITS USBPRE_DIV1_BITS
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#define USBPREBITS RCC_CFGR_USBPRE_DIV1_BITS
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#define FLASHBITS 0x00000011
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#else
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#define USBPREBITS USBPRE_DIV1P5_BITS
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#define USBPREBITS RCC_CFGR_USBPRE_DIV1P5_BITS
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#define FLASHBITS 0x00000012
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#endif
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/*
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* Definitions for RCC_CR register.
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* Extra definitions for RCC_CR register (missing from the ST header file).
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*/
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#define CR_HSION_MASK (0x1 << 0)
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#define CR_HSIRDY_MASK (0x1 << 1)
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#define CR_HSITRIM_MASK (0x1F << 3)
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#define HSITRIM_RESET_BITS (0x10 << 3)
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#define CR_HSICAL_MASK (0xFF << 8)
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#define CR_HSEON_MASK (0x1 << 16)
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#define CR_HSERDY_MASK (0x1 << 17)
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#define CR_HSEBYP_MASK (0x1 << 18)
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#define CR_CSSON_MASK (0x1 << 19)
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#define CR_PLLON_MASK (0x1 << 24)
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#define CR_PLLRDY_MASK (0x1 << 25)
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#define RCC_CR_HSITRIM_RESET_BITS (0x10 << 3)
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/*
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* Definitions for RCC_CFGR register.
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* Extra definitions for RCC_CFGR register (missing from the ST header file).
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*/
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#define CFGR_SW_MASK (0x3 << 0)
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#define SW_HSI_BITS (0 << 0)
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#define SW_HSE_BITS (1 << 0)
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#define SW_PLL_BITS (2 << 0)
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#define CFGR_SWS_MASK (0x3 << 2)
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#define SWS_HSI_BITS (0 << 2)
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#define SWS_HSE_BITS (1 << 2)
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#define SWS_PLL_BITS (2 << 2)
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#define CFGR_HPRE_MASK (0xF << 4)
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#define HPRE_DIV1_BITS (0 << 4)
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#define CFGR_PPRE1_MASK (0x7 << 8)
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#define PPRE1_DIV1_BITS (0 << 8)
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#define PPRE1_DIV2_BITS (4 << 8)
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#define CFGR_PPRE2_MASK (0x7 << 11)
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#define PPRE2_DIV1_BITS (0 << 11)
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#define PPRE2_DIV2_BITS (4 << 11)
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#define CFGR_ADCPRE_MASK (0x3 << 14)
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#define ADCPRE_DIV2_BITS (0 << 14)
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#define ADCPRE_DIV4_BITS (1 << 14)
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#define ADCPRE_DIV6_BITS (2 << 14)
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#define ADCPRE_DIV8_BITS (3 << 14)
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#define CFGR_PLLSRC_MASK (0x1 << 16)
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#define PLLSRC_HSI_BITS (0 << 16)
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#define PLLSRC_HSE_BITS (1 << 16)
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#define CFGR_PLLXTPRE_MASK (0x1 << 17)
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#define CFGR_PLLMUL_MASK (0xF << 18)
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#define CFGR_USBPRE_MASK (0x1 << 22)
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#define USBPRE_DIV1P5_BITS (0 << 22)
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#define USBPRE_DIV1_BITS (1 << 22)
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#define CFGR_MCO_MASK (0x7 << 24)
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#define MCO_DISABLED_BITS (0 << 24)
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#define RCC_CFGR_PLLSRC_HSI_BITS (0 << 16)
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#define RCC_CFGR_PLLSRC_HSE_BITS (1 << 16)
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#define RCC_CFGR_USBPRE_DIV1P5_BITS (0 << 22)
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#define RCC_CFGR_USBPRE_DIV1_BITS (1 << 22)
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/*
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* IO pins assignments.
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@ -35,7 +35,6 @@
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#undef FALSE
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#undef TRUE
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#include "stm32f10x_map.h"
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#include "stm32f10x_rcc.h"
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#define FALSE 0
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#define TRUE (!FALSE)
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#endif
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@ -74,6 +74,8 @@ GNU-Linux-GCC - ChibiOS/RT simulator for x86 Linux systems, it is
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initialization code in board.c. All the demos now use PAL for I/O. AVR is
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not supported because its "sparse" registers layout, it would not be
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efficient enough for my taste.
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- Modified the STM32 demo to use the bit definitions in the ST header file,
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removed the bit definitions in board.h.
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- Documentation section reorganization and fixes.
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- Changed the STM32 demo stack sizes, it was incorrectly adjusted in version
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1.3.0 but it did not create problems (not a bug).
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