From 237a87e071aa0bb89ba3e90f453cdde712c4a53c Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sat, 24 Aug 2013 08:22:49 +0000 Subject: [PATCH] git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6215 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- .../NONSTANDARD_STM32F4_BARTHESS1/board.c | 1 - .../NONSTANDARD_STM32F4_BARTHESS1/board.mk | 4 +- os/hal/platforms/STM32/I2Cv1/i2c_lld.c | 309 +++++++---------- os/hal/platforms/STM32/I2Cv1/i2c_lld.h | 49 +-- os/hal/platforms/STM32/I2Cv2/i2c_lld.c | 48 +-- testhal/STM32F4xx/I2C/.project | 2 +- testhal/STM32F4xx/I2C/Makefile | 19 +- testhal/STM32F4xx/I2C/chconf.h | 312 +++++++++++------- testhal/STM32F4xx/I2C/halconf.h | 9 +- testhal/STM32F4xx/I2C/main.c | 6 +- testhal/STM32F4xx/I2C/mcuconf.h | 2 +- 11 files changed, 374 insertions(+), 387 deletions(-) diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.c b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.c index 193217320..cf4fd460e 100644 --- a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.c +++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.c @@ -14,7 +14,6 @@ limitations under the License. */ -#include "ch.h" #include "hal.h" /** diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk index 8f50edf14..fe33d03fd 100644 --- a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk +++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk @@ -1,5 +1,5 @@ # List of all the board related files. -BOARDSRC = $(CHIBIOS)/boards/NONSTANDARD_STM32F4_BARTHESS1/board.c +BOARDSRC = $(CHIBIOS)/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.c # Required include directories -BOARDINC = $(CHIBIOS)/boards/NONSTANDARD_STM32F4_BARTHESS1 +BOARDINC = $(CHIBIOS)/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1 diff --git a/os/hal/platforms/STM32/I2Cv1/i2c_lld.c b/os/hal/platforms/STM32/I2Cv1/i2c_lld.c index ba5d0a140..35c607330 100644 --- a/os/hal/platforms/STM32/I2Cv1/i2c_lld.c +++ b/os/hal/platforms/STM32/I2Cv1/i2c_lld.c @@ -26,7 +26,6 @@ * @{ */ -#include "ch.h" #include "hal.h" #if HAL_USE_I2C || defined(__DOXYGEN__) @@ -110,25 +109,6 @@ I2CDriver I2CD3; /* Driver local functions. */ /*===========================================================================*/ -/** - * @brief Wakes up the waiting thread. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] msg wakeup message - * - * @notapi - */ -#define wakeup_isr(i2cp, msg) { \ - chSysLockFromIsr(); \ - if ((i2cp)->thread != NULL) { \ - Thread *tp = (i2cp)->thread; \ - (i2cp)->thread = NULL; \ - tp->p_u.rdymsg = (msg); \ - chSchReadyI(tp); \ - } \ - chSysUnlockFromIsr(); \ -} - /** * @brief Aborts an I2C transaction. * @@ -150,27 +130,6 @@ static void i2c_lld_abort_operation(I2CDriver *i2cp) { dmaStreamDisable(i2cp->dmarx); } -/** - * @brief Handling of stalled I2C transactions. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static void i2c_lld_safety_timeout(void *p) { - I2CDriver *i2cp = (I2CDriver *)p; - - chSysLockFromIsr(); - if (i2cp->thread) { - Thread *tp = i2cp->thread; - i2c_lld_abort_operation(i2cp); - i2cp->thread = NULL; - tp->p_u.rdymsg = RDY_TIMEOUT; - chSchReadyI(tp); - } - chSysUnlockFromIsr(); -} - /** * @brief Set clock speed. * @@ -184,8 +143,9 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) { int32_t clock_speed = i2cp->config->clock_speed; i2cdutycycle_t duty = i2cp->config->duty_cycle; - chDbgCheck((i2cp != NULL) && (clock_speed > 0) && (clock_speed <= 4000000), - "i2c_lld_set_clock"); + osalDbgCheck((i2cp != NULL) && + (clock_speed > 0) && + (clock_speed <= 4000000)); /* CR2 Configuration.*/ dp->CR2 &= (uint16_t)~I2C_CR2_FREQ; @@ -197,19 +157,15 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) { if (clock_speed <= 100000) { /* Configure clock_div in standard mode.*/ - chDbgAssert(duty == STD_DUTY_CYCLE, - "i2c_lld_set_clock(), #1", - "Invalid standard mode duty cycle"); + osalDbgAssert(duty == STD_DUTY_CYCLE, "invalid standard mode duty cycle"); /* Standard mode clock_div calculate: Tlow/Thigh = 1/1.*/ - chDbgAssert((STM32_PCLK1 % (clock_speed * 2)) == 0, - "i2c_lld_set_clock(), #2", - "PCLK1 must be divided without remainder"); + osalDbgAssert((STM32_PCLK1 % (clock_speed * 2)) == 0, + "PCLK1 must be divisible without remainder"); clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 2)); - chDbgAssert(clock_div >= 0x04, - "i2c_lld_set_clock(), #3", - "Clock divider less then 0x04 not allowed"); + osalDbgAssert(clock_div >= 0x04, + "clock divider less then 0x04 not allowed"); regCCR |= (clock_div & I2C_CCR_CCR); /* Sets the Maximum Rise Time for standard mode.*/ @@ -217,37 +173,33 @@ static void i2c_lld_set_clock(I2CDriver *i2cp) { } else if (clock_speed <= 400000) { /* Configure clock_div in fast mode.*/ - chDbgAssert((duty == FAST_DUTY_CYCLE_2) || (duty == FAST_DUTY_CYCLE_16_9), - "i2c_lld_set_clock(), #4", - "Invalid fast mode duty cycle"); + osalDbgAssert((duty == FAST_DUTY_CYCLE_2) || + (duty == FAST_DUTY_CYCLE_16_9), + "invalid fast mode duty cycle"); if (duty == FAST_DUTY_CYCLE_2) { /* Fast mode clock_div calculate: Tlow/Thigh = 2/1.*/ - chDbgAssert((STM32_PCLK1 % (clock_speed * 3)) == 0, - "i2c_lld_set_clock(), #5", - "PCLK1 must be divided without remainder"); + osalDbgAssert((STM32_PCLK1 % (clock_speed * 3)) == 0, + "PCLK1 must be divided without remainder"); clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 3)); } else if (duty == FAST_DUTY_CYCLE_16_9) { /* Fast mode clock_div calculate: Tlow/Thigh = 16/9.*/ - chDbgAssert((STM32_PCLK1 % (clock_speed * 25)) == 0, - "i2c_lld_set_clock(), #6", - "PCLK1 must be divided without remainder"); + osalDbgAssert((STM32_PCLK1 % (clock_speed * 25)) == 0, + "PCLK1 must be divided without remainder"); clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 25)); regCCR |= I2C_CCR_DUTY; } - chDbgAssert(clock_div >= 0x01, - "i2c_lld_set_clock(), #7", - "Clock divider less then 0x04 not allowed"); + osalDbgAssert(clock_div >= 0x01, + "clock divider less then 0x04 not allowed"); regCCR |= (I2C_CCR_FS | (clock_div & I2C_CCR_CCR)); /* Sets the Maximum Rise Time for fast mode.*/ dp->TRISE = (I2C_CLK_FREQ * 300 / 1000) + 1; } - chDbgAssert((clock_div <= I2C_CCR_CCR), - "i2c_lld_set_clock(), #8", "the selected clock is too low"); + osalDbgAssert((clock_div <= I2C_CCR_CCR), "the selected clock is too low"); dp->CCR = regCCR; } @@ -320,7 +272,7 @@ static void i2c_lld_serve_event_interrupt(I2CDriver *i2cp) { } dp->CR2 &= ~I2C_CR2_ITEVTEN; dp->CR1 |= I2C_CR1_STOP; - wakeup_isr(i2cp, RDY_OK); + _i2c_wakeup_isr(i2cp); break; default: break; @@ -355,7 +307,7 @@ static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags) { dp->CR2 &= ~I2C_CR2_LAST; dp->CR1 &= ~I2C_CR1_ACK; dp->CR1 |= I2C_CR1_STOP; - wakeup_isr(i2cp, RDY_OK); + _i2c_wakeup_isr(i2cp); } /** @@ -398,35 +350,35 @@ static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint16_t sr) { dmaStreamDisable(i2cp->dmatx); dmaStreamDisable(i2cp->dmarx); - i2cp->errors = I2CD_NO_ERROR; + i2cp->errors = I2C_NO_ERROR; if (sr & I2C_SR1_BERR) /* Bus error. */ - i2cp->errors |= I2CD_BUS_ERROR; + i2cp->errors |= I2C_BUS_ERROR; if (sr & I2C_SR1_ARLO) /* Arbitration lost. */ - i2cp->errors |= I2CD_ARBITRATION_LOST; + i2cp->errors |= I2C_ARBITRATION_LOST; if (sr & I2C_SR1_AF) { /* Acknowledge fail. */ i2cp->i2c->CR2 &= ~I2C_CR2_ITEVTEN; i2cp->i2c->CR1 |= I2C_CR1_STOP; /* Setting stop bit. */ - i2cp->errors |= I2CD_ACK_FAILURE; + i2cp->errors |= I2C_ACK_FAILURE; } if (sr & I2C_SR1_OVR) /* Overrun. */ - i2cp->errors |= I2CD_OVERRUN; + i2cp->errors |= I2C_OVERRUN; if (sr & I2C_SR1_TIMEOUT) /* SMBus Timeout. */ - i2cp->errors |= I2CD_TIMEOUT; + i2cp->errors |= I2C_TIMEOUT; if (sr & I2C_SR1_PECERR) /* PEC error. */ - i2cp->errors |= I2CD_PEC_ERROR; + i2cp->errors |= I2C_PEC_ERROR; if (sr & I2C_SR1_SMBALERT) /* SMBus alert. */ - i2cp->errors |= I2CD_SMB_ALERT; + i2cp->errors |= I2C_SMB_ALERT; /* If some error has been identified then sends wakes the waiting thread.*/ - if (i2cp->errors != I2CD_NO_ERROR) - wakeup_isr(i2cp, RDY_RESET); + if (i2cp->errors != I2C_NO_ERROR) + _i2c_wakeup_error_isr(i2cp); } /*===========================================================================*/ @@ -439,27 +391,27 @@ static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint16_t sr) { * * @notapi */ -CH_IRQ_HANDLER(I2C1_EV_IRQHandler) { +OSAL_IRQ_HANDLER(I2C1_EV_IRQHandler) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); i2c_lld_serve_event_interrupt(&I2CD1); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** * @brief I2C1 error interrupt handler. */ -CH_IRQ_HANDLER(I2C1_ER_IRQHandler) { +OSAL_IRQ_HANDLER(I2C1_ER_IRQHandler) { uint16_t sr = I2CD1.i2c->SR1; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); I2CD1.i2c->SR1 = ~(sr & I2C_ERROR_MASK); i2c_lld_serve_error_interrupt(&I2CD1, sr); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif /* STM32_I2C_USE_I2C1 */ @@ -469,13 +421,13 @@ CH_IRQ_HANDLER(I2C1_ER_IRQHandler) { * * @notapi */ -CH_IRQ_HANDLER(I2C2_EV_IRQHandler) { +OSAL_IRQ_HANDLER(I2C2_EV_IRQHandler) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); i2c_lld_serve_event_interrupt(&I2CD2); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -483,15 +435,15 @@ CH_IRQ_HANDLER(I2C2_EV_IRQHandler) { * * @notapi */ -CH_IRQ_HANDLER(I2C2_ER_IRQHandler) { +OSAL_IRQ_HANDLER(I2C2_ER_IRQHandler) { uint16_t sr = I2CD2.i2c->SR1; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); I2CD2.i2c->SR1 = ~(sr & I2C_ERROR_MASK); i2c_lld_serve_error_interrupt(&I2CD2, sr); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif /* STM32_I2C_USE_I2C2 */ @@ -501,13 +453,13 @@ CH_IRQ_HANDLER(I2C2_ER_IRQHandler) { * * @notapi */ -CH_IRQ_HANDLER(I2C3_EV_IRQHandler) { +OSAL_IRQ_HANDLER(I2C3_EV_IRQHandler) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); i2c_lld_serve_event_interrupt(&I2CD3); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -515,15 +467,15 @@ CH_IRQ_HANDLER(I2C3_EV_IRQHandler) { * * @notapi */ -CH_IRQ_HANDLER(I2C3_ER_IRQHandler) { +OSAL_IRQ_HANDLER(I2C3_ER_IRQHandler) { uint16_t sr = I2CD3.i2c->SR1; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); I2CD3.i2c->SR1 = ~(sr & I2C_ERROR_MASK); i2c_lld_serve_error_interrupt(&I2CD3, sr); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif /* STM32_I2C_USE_I2C3 */ @@ -587,24 +539,22 @@ void i2c_lld_start(I2CDriver *i2cp) { #if STM32_I2C_USE_I2C1 if (&I2CD1 == i2cp) { - bool_t b; + bool b; rccResetI2C1(); b = dmaStreamAllocate(i2cp->dmarx, STM32_I2C_I2C1_IRQ_PRIORITY, (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, (void *)i2cp); - chDbgAssert(!b, "i2c_lld_start(), #1", "stream already allocated"); + osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(i2cp->dmatx, STM32_I2C_I2C1_IRQ_PRIORITY, (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, (void *)i2cp); - chDbgAssert(!b, "i2c_lld_start(), #2", "stream already allocated"); + osalDbgAssert(!b, "stream already allocated"); rccEnableI2C1(FALSE); - nvicEnableVector(I2C1_EV_IRQn, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); - nvicEnableVector(I2C1_ER_IRQn, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); + nvicEnableVector(I2C1_EV_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY); + nvicEnableVector(I2C1_ER_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY); i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY); @@ -615,24 +565,22 @@ void i2c_lld_start(I2CDriver *i2cp) { #if STM32_I2C_USE_I2C2 if (&I2CD2 == i2cp) { - bool_t b; + bool b; rccResetI2C2(); b = dmaStreamAllocate(i2cp->dmarx, STM32_I2C_I2C2_IRQ_PRIORITY, (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, (void *)i2cp); - chDbgAssert(!b, "i2c_lld_start(), #3", "stream already allocated"); + osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(i2cp->dmatx, STM32_I2C_I2C2_IRQ_PRIORITY, (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, (void *)i2cp); - chDbgAssert(!b, "i2c_lld_start(), #4", "stream already allocated"); + osalDbgAssert(!b, "stream already allocated"); rccEnableI2C2(FALSE); - nvicEnableVector(I2C2_EV_IRQn, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); - nvicEnableVector(I2C2_ER_IRQn, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY)); + nvicEnableVector(I2C2_EV_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY); + nvicEnableVector(I2C2_ER_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY); i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY); @@ -643,24 +591,22 @@ void i2c_lld_start(I2CDriver *i2cp) { #if STM32_I2C_USE_I2C3 if (&I2CD3 == i2cp) { - bool_t b; + bool b; rccResetI2C3(); b = dmaStreamAllocate(i2cp->dmarx, STM32_I2C_I2C3_IRQ_PRIORITY, (stm32_dmaisr_t)i2c_lld_serve_rx_end_irq, (void *)i2cp); - chDbgAssert(!b, "i2c_lld_start(), #5", "stream already allocated"); + osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(i2cp->dmatx, STM32_I2C_I2C3_IRQ_PRIORITY, (stm32_dmaisr_t)i2c_lld_serve_tx_end_irq, (void *)i2cp); - chDbgAssert(!b, "i2c_lld_start(), #6", "stream already allocated"); + osalDbgAssert(!b, "stream already allocated"); rccEnableI2C3(FALSE); - nvicEnableVector(I2C3_EV_IRQn, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY)); - nvicEnableVector(I2C3_ER_IRQn, - CORTEX_PRIORITY_MASK(STM32_I2C_I2C3_IRQ_PRIORITY)); + nvicEnableVector(I2C3_EV_IRQn, STM32_I2C_I2C3_IRQ_PRIORITY); + nvicEnableVector(I2C3_ER_IRQn, STM32_I2C_I2C3_IRQ_PRIORITY); i2cp->rxdmamode |= STM32_DMA_CR_CHSEL(I2C3_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_I2C_I2C3_DMA_PRIORITY); @@ -744,10 +690,10 @@ void i2c_lld_stop(I2CDriver *i2cp) { * - @a TIME_INFINITE no timeout. * . * @return The operation status. - * @retval RDY_OK if the function succeeded. - * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * @retval MSG_OK if the function succeeded. + * @retval MSG_RESET if one or more I2C errors occurred, the errors can * be retrieved using @p i2cGetErrors(). - * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a + * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a * timeout the driver must be stopped and restarted * because the bus is in an uncertain state. * @@ -757,56 +703,57 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, uint8_t *rxbuf, size_t rxbytes, systime_t timeout) { I2C_TypeDef *dp = i2cp->i2c; - VirtualTimer vt; + systime_t start, end; #if defined(STM32F1XX_I2C) - chDbgCheck((rxbytes > 1), "i2c_lld_master_receive_timeout"); + osalDbgCheck((rxbytes > 1), "i2c_lld_master_receive_timeout"); #endif - /* Global timeout for the whole operation.*/ - if (timeout != TIME_INFINITE) - chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp); - - /* Releases the lock from high level driver.*/ - chSysUnlock(); + /* Resetting error flags for this transfer.*/ + i2cp->errors = I2C_NO_ERROR; /* Initializes driver fields, LSB = 1 -> receive.*/ i2cp->addr = (addr << 1) | 0x01; - i2cp->errors = 0; + + /* Releases the lock from high level driver.*/ + osalSysUnlock(); /* RX DMA setup.*/ dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode); dmaStreamSetMemory0(i2cp->dmarx, rxbuf); dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); - /* Waits until BUSY flag is reset and the STOP from the previous operation - is completed, alternatively for a timeout condition.*/ - while ((dp->SR2 & I2C_SR2_BUSY) || (dp->CR1 & I2C_CR1_STOP)) { - chSysLock(); - if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) - return RDY_TIMEOUT; - chSysUnlock(); + /* Calculating the time window for the timeout on the busy bus condition.*/ + start = osalOsGetSystemTimeX(); + end = start + OSAL_MS2ST(STM32_I2C_BUSY_TIMEOUT); + + /* Waits until BUSY flag is reset or, alternatively, for a timeout + condition.*/ + while (true) { + osalSysLock(); + + /* If the bus is not busy then the operation can continue, note, the + loop is exited in the locked state.*/ + if (!(dp->SR2 & I2C_SR2_BUSY) && !(dp->CR1 & I2C_CR1_STOP)) + break; + + /* If the system time went outside the allowed window then a timeout + condition is returned.*/ + if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) + return MSG_TIMEOUT; + + osalSysUnlock(); } /* This lock will be released in high level driver.*/ - chSysLock(); - - /* Atomic check on the timer in order to make sure that a timeout didn't - happen outside the critical zone.*/ - if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) - return RDY_TIMEOUT; + osalSysLock(); /* Starts the operation.*/ dp->CR2 |= I2C_CR2_ITEVTEN; dp->CR1 |= I2C_CR1_START | I2C_CR1_ACK; /* Waits for the operation completion or a timeout.*/ - i2cp->thread = chThdSelf(); - chSchGoSleepS(THD_STATE_SUSPENDED); - if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt)) - chVTResetI(&vt); - - return chThdSelf()->p_u.rdymsg; + return osalThreadSuspendTimeoutS(&i2cp->thread, timeout); } /** @@ -825,10 +772,10 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, * - @a TIME_INFINITE no timeout. * . * @return The operation status. - * @retval RDY_OK if the function succeeded. - * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * @retval MSG_OK if the function succeeded. + * @retval MSG_RESET if one or more I2C errors occurred, the errors can * be retrieved using @p i2cGetErrors(). - * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a + * @retval MSG_TIMEOUT if a timeout occurred before operation end. After a * timeout the driver must be stopped and restarted * because the bus is in an uncertain state. * @@ -839,23 +786,20 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, uint8_t *rxbuf, size_t rxbytes, systime_t timeout) { I2C_TypeDef *dp = i2cp->i2c; - VirtualTimer vt; + systime_t start, end; #if defined(STM32F1XX_I2C) - chDbgCheck(((rxbytes == 0) || ((rxbytes > 1) && (rxbuf != NULL))), - "i2c_lld_master_transmit_timeout"); + osalDbgCheck(((rxbytes == 0) || ((rxbytes > 1) && (rxbuf != NULL)))); #endif - /* Global timeout for the whole operation.*/ - if (timeout != TIME_INFINITE) - chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp); + /* Resetting error flags for this transfer.*/ + i2cp->errors = I2C_NO_ERROR; + + /* Initializes driver fields, LSB = 1 -> receive.*/ + i2cp->addr = (addr << 1) | 0x01; /* Releases the lock from high level driver.*/ - chSysUnlock(); - - /* Initializes driver fields, LSB = 0 -> write.*/ - i2cp->addr = addr << 1; - i2cp->errors = 0; + osalSysUnlock(); /* TX DMA setup.*/ dmaStreamSetMode(i2cp->dmatx, i2cp->txdmamode); @@ -867,34 +811,37 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, dmaStreamSetMemory0(i2cp->dmarx, rxbuf); dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); - /* Waits until BUSY flag is reset and the STOP from the previous operation - is completed, alternatively for a timeout condition.*/ - while ((dp->SR2 & I2C_SR2_BUSY) || (dp->CR1 & I2C_CR1_STOP)) { - chSysLock(); - if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) - return RDY_TIMEOUT; - chSysUnlock(); + /* Calculating the time window for the timeout on the busy bus condition.*/ + start = osalOsGetSystemTimeX(); + end = start + OSAL_MS2ST(STM32_I2C_BUSY_TIMEOUT); + + /* Waits until BUSY flag is reset or, alternatively, for a timeout + condition.*/ + while (true) { + osalSysLock(); + + /* If the bus is not busy then the operation can continue, note, the + loop is exited in the locked state.*/ + if (!(dp->SR2 & I2C_SR2_BUSY) && !(dp->CR1 & I2C_CR1_STOP)) + break; + + /* If the system time went outside the allowed window then a timeout + condition is returned.*/ + if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) + return MSG_TIMEOUT; + + osalSysUnlock(); } /* This lock will be released in high level driver.*/ - chSysLock(); - - /* Atomic check on the timer in order to make sure that a timeout didn't - happen outside the critical zone.*/ - if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt)) - return RDY_TIMEOUT; + osalSysLock(); /* Starts the operation.*/ dp->CR2 |= I2C_CR2_ITEVTEN; dp->CR1 |= I2C_CR1_START; /* Waits for the operation completion or a timeout.*/ - i2cp->thread = chThdSelf(); - chSchGoSleepS(THD_STATE_SUSPENDED); - if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt)) - chVTResetI(&vt); - - return chThdSelf()->p_u.rdymsg; + return osalThreadSuspendTimeoutS(&i2cp->thread, timeout); } #endif /* HAL_USE_I2C */ diff --git a/os/hal/platforms/STM32/I2Cv1/i2c_lld.h b/os/hal/platforms/STM32/I2Cv1/i2c_lld.h index dcadb3278..a92e48e26 100644 --- a/os/hal/platforms/STM32/I2Cv1/i2c_lld.h +++ b/os/hal/platforms/STM32/I2Cv1/i2c_lld.h @@ -54,7 +54,7 @@ * @note The default is @p FALSE. */ #if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__) -#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C1 FALSE #endif /** @@ -63,7 +63,7 @@ * @note The default is @p FALSE. */ #if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__) -#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C2 FALSE #endif /** @@ -72,28 +72,35 @@ * @note The default is @p FALSE. */ #if !defined(STM32_I2C_USE_I2C3) || defined(__DOXYGEN__) -#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#endif + +/** + * @brief I2C timeout on busy condition in milliseconds. + */ +#if !defined(STM32_I2C_BUSY_TIMEOUT) || defined(__DOXYGEN__) +#define STM32_I2C_BUSY_TIMEOUT 50 #endif /** * @brief I2C1 interrupt priority level setting. */ #if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C1_IRQ_PRIORITY 10 +#define STM32_I2C_I2C1_IRQ_PRIORITY 10 #endif /** * @brief I2C2 interrupt priority level setting. */ #if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C2_IRQ_PRIORITY 10 +#define STM32_I2C_I2C2_IRQ_PRIORITY 10 #endif /** * @brief I2C3 interrupt priority level setting. */ #if !defined(STM32_I2C_I2C3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_I2C_I2C3_IRQ_PRIORITY 10 +#define STM32_I2C_I2C3_IRQ_PRIORITY 10 #endif /** @@ -132,7 +139,7 @@ * error can only happen because programming errors. */ #if !defined(STM32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt() +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) chSysHalt("DMA failure") #endif #if STM32_ADVANCED_DMA || defined(__DOXYGEN__) @@ -142,7 +149,7 @@ * @note This option is only available on platforms with enhanced DMA. */ #if !defined(STM32_I2C_I2C1_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) #endif /** @@ -150,7 +157,7 @@ * @note This option is only available on platforms with enhanced DMA. */ #if !defined(STM32_I2C_I2C1_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) #endif /** @@ -158,7 +165,7 @@ * @note This option is only available on platforms with enhanced DMA. */ #if !defined(STM32_I2C_I2C2_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #endif /** @@ -166,7 +173,7 @@ * @note This option is only available on platforms with enhanced DMA. */ #if !defined(STM32_I2C_I2C2_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) #endif /** @@ -174,7 +181,7 @@ * @note This option is only available on platforms with enhanced DMA. */ #if !defined(STM32_I2C_I2C3_RX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) #endif /** @@ -182,17 +189,17 @@ * @note This option is only available on platforms with enhanced DMA. */ #if !defined(STM32_I2C_I2C3_TX_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #endif #else /* !STM32_ADVANCED_DMA */ /* Fixed streams for platforms using the old DMA peripheral, the values are valid for both STM32F1xx and STM32L1xx.*/ -#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) -#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) -#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) -#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) #endif /* !STM32_ADVANCED_DMA*/ @@ -365,14 +372,10 @@ struct I2CDriver { */ i2cflags_t errors; #if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_USE_MUTEXES || defined(__DOXYGEN__) /** * @brief Mutex protecting the bus. */ - Mutex mutex; -#elif CH_USE_SEMAPHORES - Semaphore semaphore; -#endif + mutex_t mutex; #endif /* I2C_USE_MUTUAL_EXCLUSION */ #if defined(I2C_DRIVER_EXT_FIELDS) I2C_DRIVER_EXT_FIELDS @@ -381,7 +384,7 @@ struct I2CDriver { /** * @brief Thread waiting for I/O completion. */ - Thread *thread; + thread_reference_t thread; /** * @brief Current slave address without R/W bit. */ diff --git a/os/hal/platforms/STM32/I2Cv2/i2c_lld.c b/os/hal/platforms/STM32/I2Cv2/i2c_lld.c index eb5b67d47..249a6f54b 100644 --- a/os/hal/platforms/STM32/I2Cv2/i2c_lld.c +++ b/os/hal/platforms/STM32/I2Cv2/i2c_lld.c @@ -13,10 +13,6 @@ See the License for the specific language governing permissions and limitations under the License. */ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ /** * @file STM32/I2Cv2/i2c_lld.c @@ -574,14 +570,17 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, uint32_t addr_cr2 = addr & I2C_CR2_SADD; systime_t start, end; - osalDbgCheck((rxbytes > 0)); - /* Resetting error flags for this transfer.*/ i2cp->errors = I2C_NO_ERROR; /* Releases the lock from high level driver.*/ osalSysUnlock(); + /* RX DMA setup.*/ + dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode); + dmaStreamSetMemory0(i2cp->dmarx, rxbuf); + dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); + /* Calculating the time window for the timeout on the busy bus condition.*/ start = osalOsGetSystemTimeX(); end = start + OSAL_MS2ST(STM32_I2C_BUSY_TIMEOUT); @@ -593,7 +592,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, /* If the bus is not busy then the operation can continue, note, the loop is exited in the locked state.*/ - if (dp->ISR & I2C_ISR_BUSY) + if ((dp->ISR & I2C_ISR_BUSY) == 0) break; /* If the system time went outside the allowed window then a timeout @@ -612,14 +611,6 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, dp->CR2 &= ~(I2C_CR2_SADD | I2C_CR2_NBYTES); dp->CR2 |= (rxbytes << 16) | addr_cr2; - /* Initializes driver fields */ - i2cp->errors = 0; - - /* RX DMA setup.*/ - dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode); - dmaStreamSetMemory0(i2cp->dmarx, rxbuf); - dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); - /* Enable RX DMA */ dmaStreamEnable(i2cp->dmarx); @@ -664,14 +655,22 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, uint32_t addr_cr2 = addr & I2C_CR2_SADD; systime_t start, end; - osalDbgCheck(((rxbytes == 0) || ((rxbytes > 0) && (rxbuf != NULL)))); - /* Resetting error flags for this transfer.*/ i2cp->errors = I2C_NO_ERROR; /* Releases the lock from high level driver.*/ osalSysUnlock(); + /* TX DMA setup.*/ + dmaStreamSetMode(i2cp->dmatx, i2cp->txdmamode); + dmaStreamSetMemory0(i2cp->dmatx, txbuf); + dmaStreamSetTransactionSize(i2cp->dmatx, txbytes); + + /* RX DMA setup.*/ + dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode); + dmaStreamSetMemory0(i2cp->dmarx, rxbuf); + dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); + /* Calculating the time window for the timeout on the busy bus condition.*/ start = osalOsGetSystemTimeX(); end = start + OSAL_MS2ST(STM32_I2C_BUSY_TIMEOUT); @@ -683,7 +682,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, /* If the bus is not busy then the operation can continue, note, the loop is exited in the locked state.*/ - if (dp->ISR & I2C_ISR_BUSY) + if ((dp->ISR & I2C_ISR_BUSY) == 0) break; /* If the system time went outside the allowed window then a timeout @@ -702,19 +701,6 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, dp->CR2 &= ~(I2C_CR2_SADD | I2C_CR2_NBYTES); dp->CR2 |= (txbytes << 16) | addr_cr2; - /* Initializes driver fields */ - i2cp->errors = 0; - - /* TX DMA setup.*/ - dmaStreamSetMode(i2cp->dmatx, i2cp->txdmamode); - dmaStreamSetMemory0(i2cp->dmatx, txbuf); - dmaStreamSetTransactionSize(i2cp->dmatx, txbytes); - - /* RX DMA setup.*/ - dmaStreamSetMode(i2cp->dmarx, i2cp->rxdmamode); - dmaStreamSetMemory0(i2cp->dmarx, rxbuf); - dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes); - /* Enable TX DMA */ dmaStreamEnable(i2cp->dmatx); diff --git a/testhal/STM32F4xx/I2C/.project b/testhal/STM32F4xx/I2C/.project index c506abb10..a3b5ed440 100644 --- a/testhal/STM32F4xx/I2C/.project +++ b/testhal/STM32F4xx/I2C/.project @@ -27,7 +27,7 @@ board 2 - CHIBIOS/boards/NONSTANDARD_STM32F4_BARTHESS1 + CHIBIOS/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1 os diff --git a/testhal/STM32F4xx/I2C/Makefile b/testhal/STM32F4xx/I2C/Makefile index d52f5d4e8..b9c898e6b 100644 --- a/testhal/STM32F4xx/I2C/Makefile +++ b/testhal/STM32F4xx/I2C/Makefile @@ -65,12 +65,13 @@ PROJECT = ch # Imported source files and paths CHIBIOS = ../../.. -include $(CHIBIOS)/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk -include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk include $(CHIBIOS)/os/hal/hal.mk -include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk -include $(CHIBIOS)/os/kernel/kernel.mk -include $(CHIBIOS)/test/test.mk +include $(CHIBIOS)/os/hal/osal/chibios/osal.mk +include $(CHIBIOS)/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk +include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/devices/STM32F4xx/port.mk +#include $(CHIBIOS)/test/test.mk # Define linker script file here LDSCRIPT= $(PORTLD)/STM32F407xG.ld @@ -82,9 +83,9 @@ CSRC = $(PORTSRC) \ $(KERNSRC) \ $(TESTSRC) \ $(HALSRC) \ + $(OSALSRC) \ $(PLATFORMSRC) \ $(BOARDSRC) \ - $(CHIBIOS)/os/various/chprintf.c \ main.c # C++ sources that can be compiled in ARM or THUMB mode depending on the global @@ -115,7 +116,7 @@ TCPPSRC = ASMSRC = $(PORTASM) INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ - $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(HALINC) $(OSALINC) $(PLATFORMINC) $(BOARDINC) \ $(CHIBIOS)/os/various # @@ -208,8 +209,10 @@ ULIBS = ifeq ($(USE_FPU),yes) USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant DDEFS += -DCORTEX_USE_FPU=TRUE + DADEFS += -DCORTEX_USE_FPU=TRUE else DDEFS += -DCORTEX_USE_FPU=FALSE + DADEFS += -DCORTEX_USE_FPU=FALSE endif ifeq ($(USE_FWLIB),yes) @@ -219,4 +222,4 @@ ifeq ($(USE_FWLIB),yes) USE_OPT += -DUSE_STDPERIPH_DRIVER endif -include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk +include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/rules.mk diff --git a/testhal/STM32F4xx/I2C/chconf.h b/testhal/STM32F4xx/I2C/chconf.h index 9357b698c..1262f2fc5 100644 --- a/testhal/STM32F4xx/I2C/chconf.h +++ b/testhal/STM32F4xx/I2C/chconf.h @@ -28,11 +28,11 @@ #ifndef _CHCONF_H_ #define _CHCONF_H_ -//#define CORTEX_VTOR_INIT 0x000E0000 -#define CORTEX_VTOR_INIT 0x00000000 - /*===========================================================================*/ -/* Kernel parameters. */ +/** + * @name Kernel parameters and options + * @{ + */ /*===========================================================================*/ /** @@ -40,8 +40,29 @@ * @details Frequency of the system timer that drives the system ticks. This * setting also defines the system tick time unit. */ -#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) -#define CH_FREQUENCY 1000 +#if !defined(CH_CFG_ST_FREQUENCY) || defined(__DOXYGEN__) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Realtime Counter frequency. + * @details Frequency of the system counter used for realtime delays and + * measurements. + */ +#if !defined(CH_CFG_RTC_FREQUENCY) || defined(__DOXYGEN__) +#define CH_CFG_RTC_FREQUENCY 168000000 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_TIMEDELTA) || defined(__DOXYGEN__) +#define CH_CFG_TIMEDELTA 2 #endif /** @@ -51,12 +72,13 @@ * disables the preemption for threads with equal priority and the * round robin becomes cooperative. Note that higher priority * threads can still preempt, the kernel is always preemptive. - * * @note Disabling the round robin preemption makes the kernel more compact * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. */ -#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) -#define CH_TIME_QUANTUM 0//20 +#if !defined(CH_CFG_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_CFG_TIME_QUANTUM 0 #endif /** @@ -68,31 +90,29 @@ * * @note In order to let the OS manage the whole RAM the linker script must * provide the @p __heap_base__ and @p __heap_end__ symbols. - * @note Requires @p CH_USE_MEMCORE. + * @note Requires @p CH_CFG_USE_MEMCORE. */ -#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) -#define CH_MEMCORE_SIZE 0 +#if !defined(CH_CFG_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_CFG_MEMCORE_SIZE 0 #endif /** * @brief Idle thread automatic spawn suppression. * @details When this option is activated the function @p chSysInit() - * does not spawn the idle thread automatically. The application has - * then the responsibility to do one of the following: - * - Spawn a custom idle thread at priority @p IDLEPRIO. - * - Change the main() thread priority to @p IDLEPRIO then enter - * an endless loop. In this scenario the @p main() thread acts as - * the idle thread. - * . - * @note Unless an idle thread is spawned the @p main() thread must not - * enter a sleep state. - */ -#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) -#define CH_NO_IDLE_THREAD FALSE + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. */ +#if !defined(CH_CFG_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_CFG_NO_IDLE_THREAD FALSE #endif +/** @} */ + /*===========================================================================*/ -/* Performance options. */ +/** + * @name Performance options + * @{ + */ /*===========================================================================*/ /** @@ -103,22 +123,38 @@ * @note This is not related to the compiler optimization options. * @note The default is @p TRUE. */ -#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) -#define CH_OPTIMIZE_SPEED FALSE +#if !defined(CH_CFG_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_CFG_OPTIMIZE_SPEED TRUE #endif +/** @} */ + /*===========================================================================*/ -/* Subsystem options. */ +/** + * @name Subsystem options + * @{ + */ /*===========================================================================*/ +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) || defined(__DOXYGEN__) +#define CH_CFG_USE_TM TRUE +#endif + /** * @brief Threads registry APIs. * @details If enabled then the registry APIs are included in the kernel. * * @note The default is @p TRUE. */ -#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) -#define CH_USE_REGISTRY TRUE +#if !defined(CH_CFG_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_CFG_USE_REGISTRY TRUE #endif /** @@ -128,8 +164,8 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) -#define CH_USE_WAITEXIT TRUE +#if !defined(CH_CFG_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_CFG_USE_WAITEXIT TRUE #endif /** @@ -138,8 +174,8 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES TRUE +#if !defined(CH_CFG_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_CFG_USE_SEMAPHORES TRUE #endif /** @@ -147,23 +183,12 @@ * @details If enabled then the threads are enqueued on semaphores by * priority rather than in FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_SEMAPHORES. + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. */ -#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_SEMAPHORES_PRIORITY FALSE -#endif - -/** - * @brief Atomic semaphore API. - * @details If enabled then the semaphores the @p chSemSignalWait() API - * is included in the kernel. - * - * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. - */ -#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) -#define CH_USE_SEMSW TRUE +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE #endif /** @@ -172,8 +197,8 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES TRUE +#if !defined(CH_CFG_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_CFG_USE_MUTEXES TRUE #endif /** @@ -182,10 +207,10 @@ * in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_MUTEXES. + * @note Requires @p CH_CFG_USE_MUTEXES. */ -#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS FALSE +#if !defined(CH_CFG_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_CFG_USE_CONDVARS TRUE #endif /** @@ -194,10 +219,10 @@ * specification are included in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_CONDVARS. + * @note Requires @p CH_CFG_USE_CONDVARS. */ -#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_CONDVARS_TIMEOUT TRUE +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE #endif /** @@ -206,8 +231,8 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) -#define CH_USE_EVENTS TRUE +#if !defined(CH_CFG_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_CFG_USE_EVENTS TRUE #endif /** @@ -216,10 +241,10 @@ * are included in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_EVENTS. + * @note Requires @p CH_CFG_USE_EVENTS. */ -#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) -#define CH_USE_EVENTS_TIMEOUT FALSE +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE #endif /** @@ -229,8 +254,8 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES TRUE +#if !defined(CH_CFG_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_CFG_USE_MESSAGES TRUE #endif /** @@ -238,11 +263,12 @@ * @details If enabled then messages are served by priority rather than in * FIFO order. * - * @note The default is @p FALSE. Enable this if you have special requirements. - * @note Requires @p CH_USE_MESSAGES. + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. */ -#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) -#define CH_USE_MESSAGES_PRIORITY FALSE +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE #endif /** @@ -251,10 +277,10 @@ * included in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_SEMAPHORES. + * @note Requires @p CH_CFG_USE_SEMAPHORES. */ -#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) -#define CH_USE_MAILBOXES TRUE +#if !defined(CH_CFG_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_CFG_USE_MAILBOXES TRUE #endif /** @@ -263,8 +289,8 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) -#define CH_USE_QUEUES TRUE +#if !defined(CH_CFG_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_CFG_USE_QUEUES TRUE #endif /** @@ -274,8 +300,8 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) -#define CH_USE_MEMCORE TRUE +#if !defined(CH_CFG_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_CFG_USE_MEMCORE TRUE #endif /** @@ -284,26 +310,12 @@ * in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or - * @p CH_USE_SEMAPHORES. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. * @note Mutexes are recommended. */ -#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) -#define CH_USE_HEAP FALSE -#endif - -/** - * @brief C-runtime allocator. - * @details If enabled the the heap allocator APIs just wrap the C-runtime - * @p malloc() and @p free() functions. - * - * @note The default is @p FALSE. - * @note Requires @p CH_USE_HEAP. - * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the - * appropriate documentation. - */ -#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) -#define CH_USE_MALLOC_HEAP FALSE +#if !defined(CH_CFG_USE_HEAP) || defined(__DOXYGEN__) +#define CH_CFG_USE_HEAP TRUE #endif /** @@ -313,8 +325,8 @@ * * @note The default is @p TRUE. */ -#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) -#define CH_USE_MEMPOOLS TRUE +#if !defined(CH_CFG_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_CFG_USE_MEMPOOLS TRUE #endif /** @@ -323,16 +335,31 @@ * in the kernel. * * @note The default is @p TRUE. - * @note Requires @p CH_USE_WAITEXIT. - * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. */ -#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) -#define CH_USE_DYNAMIC FALSE +#if !defined(CH_CFG_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_CFG_USE_DYNAMIC TRUE #endif +/** @} */ + /*===========================================================================*/ -/* Debug options. */ +/** + * @name Debug options + * @{ + */ /*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) || defined(__DOXYGEN__) +#define CH_DBG_STATISTICS TRUE +#endif + /** * @brief Debug option, system state check. * @details If enabled the correct call protocol for system APIs is checked @@ -341,7 +368,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#define CH_DBG_SYSTEM_STATE_CHECK TRUE #endif /** @@ -352,7 +379,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_CHECKS TRUE +#define CH_DBG_ENABLE_CHECKS TRUE #endif /** @@ -364,7 +391,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_ASSERTS TRUE +#define CH_DBG_ENABLE_ASSERTS TRUE #endif /** @@ -375,7 +402,7 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_TRACE TRUE +#define CH_DBG_ENABLE_TRACE TRUE #endif /** @@ -389,7 +416,7 @@ * @p panic_msg variable set to @p NULL. */ #if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) -#define CH_DBG_ENABLE_STACK_CHECK TRUE +#define CH_DBG_ENABLE_STACK_CHECK TRUE #endif /** @@ -401,32 +428,37 @@ * @note The default is @p FALSE. */ #if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) -#define CH_DBG_FILL_THREADS TRUE +#define CH_DBG_FILL_THREADS TRUE #endif /** * @brief Debug option, threads profiling. - * @details If enabled then a field is added to the @p Thread structure that + * @details If enabled then a field is added to the @p thread_t structure that * counts the system ticks occurred while executing the thread. * - * @note The default is @p TRUE. - * @note This debug option is defaulted to TRUE because it is required by - * some test cases into the test suite. + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. */ #if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) -#define CH_DBG_THREADS_PROFILING TRUE +#define CH_DBG_THREADS_PROFILING FALSE #endif +/** @} */ + /*===========================================================================*/ -/* Kernel hooks. */ +/** + * @name Kernel hooks + * @{ + */ /*===========================================================================*/ /** * @brief Threads descriptor structure extension. - * @details User fields added to the end of the @p Thread structure. + * @details User fields added to the end of the @p thread_t structure. */ -#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) -#define THREAD_EXT_FIELDS \ +#if !defined(CH_CFG_THREAD_EXTRA_FIELDS) || defined(__DOXYGEN__) +#define CH_CFG_THREAD_EXTRA_FIELDS \ /* Add threads custom fields here.*/ #endif @@ -437,8 +469,8 @@ * @note It is invoked from within @p chThdInit() and implicitly from all * the threads creation APIs. */ -#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_INIT_HOOK(tp) { \ +#if !defined(CH_CFG_THREAD_INIT_HOOK) || defined(__DOXYGEN__) +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ /* Add threads initialization code here.*/ \ } #endif @@ -451,8 +483,8 @@ * @note It is also invoked when the threads simply return in order to * terminate. */ -#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) -#define THREAD_EXT_EXIT_HOOK(tp) { \ +#if !defined(CH_CFG_THREAD_EXIT_HOOK) || defined(__DOXYGEN__) +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ /* Add threads finalization code here.*/ \ } #endif @@ -461,18 +493,40 @@ * @brief Context switch hook. * @details This hook is invoked just before switching between threads. */ -#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) -#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ +#if !defined(CH_CFG_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ /* System halt code here.*/ \ } #endif +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#if !defined(CH_CFG_IDLE_ENTER_HOOK) || defined(__DOXYGEN__) +#define CH_CFG_IDLE_ENTER_HOOK() { \ +} +#endif + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#if !defined(CH_CFG_IDLE_LEAVE_HOOK) || defined(__DOXYGEN__) +#define CH_CFG_IDLE_LEAVE_HOOK() { \ +} +#endif + /** * @brief Idle Loop hook. * @details This hook is continuously invoked by the idle thread loop. */ -#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) -#define IDLE_LOOP_HOOK() { \ +#if !defined(CH_CFG_IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define CH_CFG_IDLE_LOOP_HOOK() { \ /* Idle loop code here.*/ \ } #endif @@ -482,8 +536,8 @@ * @details This hook is invoked in the system tick handler immediately * after processing the virtual timers queue. */ -#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) -#define SYSTEM_TICK_EVENT_HOOK() { \ +#if !defined(CH_CFG_SYSTEM_TICK_HOOK) || defined(__DOXYGEN__) +#define CH_CFG_SYSTEM_TICK_HOOK() { \ /* System tick event code here.*/ \ } #endif @@ -493,12 +547,14 @@ * @details This hook is invoked in case to a system halting error before * the system is halted. */ -#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) -#define SYSTEM_HALT_HOOK() { \ +#if !defined(CH_CFG_SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ /* System halt code here.*/ \ } #endif +/** @} */ + /*===========================================================================*/ /* Port-specific settings (override port settings defaulted in chcore.h). */ /*===========================================================================*/ diff --git a/testhal/STM32F4xx/I2C/halconf.h b/testhal/STM32F4xx/I2C/halconf.h index 8f77e1d4a..251cad3ab 100644 --- a/testhal/STM32F4xx/I2C/halconf.h +++ b/testhal/STM32F4xx/I2C/halconf.h @@ -30,13 +30,6 @@ #include "mcuconf.h" -/** - * @brief Enables the TM subsystem. - */ -#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) -#define HAL_USE_TM TRUE -#endif - /** * @brief Enables the PAL subsystem. */ @@ -62,7 +55,7 @@ * @brief Enables the EXT subsystem. */ #if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) -#define HAL_USE_EXT TRUE +#define HAL_USE_EXT FALSE #endif /** diff --git a/testhal/STM32F4xx/I2C/main.c b/testhal/STM32F4xx/I2C/main.c index e83a98ffd..b90feb138 100644 --- a/testhal/STM32F4xx/I2C/main.c +++ b/testhal/STM32F4xx/I2C/main.c @@ -109,7 +109,7 @@ static const I2CConfig i2cfg2 = { * Application entry point. */ int main(void) { - msg_t status = RDY_OK; + msg_t status = MSG_OK; systime_t tmo = MS2ST(4); /* @@ -143,7 +143,7 @@ int main(void) { status = i2cMasterTransmitTimeout(&I2CD2, mma8451_addr, txbuf, 2, rxbuf, 0, tmo); i2cReleaseBus(&I2CD2); - if (status != RDY_OK){ + if (status != MSG_OK){ errors = i2cGetErrors(&I2CD2); } @@ -159,7 +159,7 @@ int main(void) { status = i2cMasterTransmitTimeout(&I2CD2, mma8451_addr, txbuf, 1, rxbuf, 6, tmo); i2cReleaseBus(&I2CD2); - if (status != RDY_OK){ + if (status != MSG_OK){ errors = i2cGetErrors(&I2CD2); } diff --git a/testhal/STM32F4xx/I2C/mcuconf.h b/testhal/STM32F4xx/I2C/mcuconf.h index d81560814..f577a9e77 100644 --- a/testhal/STM32F4xx/I2C/mcuconf.h +++ b/testhal/STM32F4xx/I2C/mcuconf.h @@ -108,7 +108,7 @@ /* * GPT driver system settings. */ -#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM1 TRUE #define STM32_GPT_USE_TIM2 FALSE #define STM32_GPT_USE_TIM3 FALSE #define STM32_GPT_USE_TIM4 FALSE