From 1d3b6b4198265ebd42a89f5d300c00c83ea4d179 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Sun, 4 Aug 2013 16:33:19 +0000 Subject: [PATCH] git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6078 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/ARMCM4-STM32F303-DISCOVERY/halconf.h | 6 +- demos/ARMCM4-STM32F303-DISCOVERY/mcuconf.h | 14 ++-- os/halnew/platforms/STM32/SPIv2/spi_lld.c | 13 ++-- os/halnew/platforms/STM32/SPIv2/spi_lld.h | 12 ++-- os/halnew/platforms/STM32/icu_lld.c | 67 +++++++++--------- os/halnew/platforms/STM32/pwm_lld.c | 8 +-- os/halnew/platforms/STM32F30x/hal_lld.c | 1 - os/halnew/platforms/STM32F30x/stm32_dma.c | 81 +++++++++++----------- os/halnew/src/spi.c | 2 +- 9 files changed, 97 insertions(+), 107 deletions(-) diff --git a/demos/ARMCM4-STM32F303-DISCOVERY/halconf.h b/demos/ARMCM4-STM32F303-DISCOVERY/halconf.h index 8dcb3fba2..72ec926f0 100644 --- a/demos/ARMCM4-STM32F303-DISCOVERY/halconf.h +++ b/demos/ARMCM4-STM32F303-DISCOVERY/halconf.h @@ -76,7 +76,7 @@ * @brief Enables the ICU subsystem. */ #if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) -#define HAL_USE_ICU FALSE +#define HAL_USE_ICU TRUE #endif /** @@ -97,7 +97,7 @@ * @brief Enables the PWM subsystem. */ #if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) -#define HAL_USE_PWM FALSE +#define HAL_USE_PWM TRUE #endif /** @@ -132,7 +132,7 @@ * @brief Enables the SPI subsystem. */ #if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) -#define HAL_USE_SPI FALSE +#define HAL_USE_SPI TRUE #endif /** diff --git a/demos/ARMCM4-STM32F303-DISCOVERY/mcuconf.h b/demos/ARMCM4-STM32F303-DISCOVERY/mcuconf.h index 8050a5f29..b196728da 100644 --- a/demos/ARMCM4-STM32F303-DISCOVERY/mcuconf.h +++ b/demos/ARMCM4-STM32F303-DISCOVERY/mcuconf.h @@ -137,8 +137,8 @@ */ #define STM32_ICU_USE_TIM1 FALSE #define STM32_ICU_USE_TIM2 FALSE -#define STM32_ICU_USE_TIM3 FALSE -#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM3 TRUE +#define STM32_ICU_USE_TIM4 TRUE #define STM32_ICU_USE_TIM8 FALSE #define STM32_ICU_TIM1_IRQ_PRIORITY 7 #define STM32_ICU_TIM2_IRQ_PRIORITY 7 @@ -149,12 +149,12 @@ /* * PWM driver system settings. */ -#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_ADVANCED TRUE #define STM32_PWM_USE_TIM1 FALSE #define STM32_PWM_USE_TIM2 FALSE #define STM32_PWM_USE_TIM3 FALSE #define STM32_PWM_USE_TIM4 FALSE -#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM8 TRUE #define STM32_PWM_TIM1_IRQ_PRIORITY 7 #define STM32_PWM_TIM2_IRQ_PRIORITY 7 #define STM32_PWM_TIM3_IRQ_PRIORITY 7 @@ -178,9 +178,9 @@ /* * SPI driver system settings. */ -#define STM32_SPI_USE_SPI1 FALSE -#define STM32_SPI_USE_SPI2 FALSE -#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI1 TRUE +#define STM32_SPI_USE_SPI2 TRUE +#define STM32_SPI_USE_SPI3 TRUE #define STM32_SPI_SPI1_DMA_PRIORITY 1 #define STM32_SPI_SPI2_DMA_PRIORITY 1 #define STM32_SPI_SPI3_DMA_PRIORITY 1 diff --git a/os/halnew/platforms/STM32/SPIv2/spi_lld.c b/os/halnew/platforms/STM32/SPIv2/spi_lld.c index 752c2af66..712d824f6 100644 --- a/os/halnew/platforms/STM32/SPIv2/spi_lld.c +++ b/os/halnew/platforms/STM32/SPIv2/spi_lld.c @@ -22,7 +22,6 @@ * @{ */ -#include "ch.h" #include "hal.h" #if HAL_USE_SPI || defined(__DOXYGEN__) @@ -222,12 +221,12 @@ void spi_lld_start(SPIDriver *spip) { STM32_SPI_SPI1_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated"); + osalDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated"); b = dmaStreamAllocate(spip->dmatx, STM32_SPI_SPI1_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated"); + osalDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated"); rccEnableSPI1(FALSE); } #endif @@ -238,12 +237,12 @@ void spi_lld_start(SPIDriver *spip) { STM32_SPI_SPI2_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #3", "stream already allocated"); + osalDbgAssert(!b, "spi_lld_start(), #3", "stream already allocated"); b = dmaStreamAllocate(spip->dmatx, STM32_SPI_SPI2_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated"); + osalDbgAssert(!b, "spi_lld_start(), #4", "stream already allocated"); rccEnableSPI2(FALSE); } #endif @@ -254,12 +253,12 @@ void spi_lld_start(SPIDriver *spip) { STM32_SPI_SPI3_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_rx_interrupt, (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated"); + osalDbgAssert(!b, "spi_lld_start(), #5", "stream already allocated"); b = dmaStreamAllocate(spip->dmatx, STM32_SPI_SPI3_IRQ_PRIORITY, (stm32_dmaisr_t)spi_lld_serve_tx_interrupt, (void *)spip); - chDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated"); + osalDbgAssert(!b, "spi_lld_start(), #6", "stream already allocated"); rccEnableSPI3(FALSE); } #endif diff --git a/os/halnew/platforms/STM32/SPIv2/spi_lld.h b/os/halnew/platforms/STM32/SPIv2/spi_lld.h index f4cc67da5..fc2b39fa5 100644 --- a/os/halnew/platforms/STM32/SPIv2/spi_lld.h +++ b/os/halnew/platforms/STM32/SPIv2/spi_lld.h @@ -339,19 +339,15 @@ struct SPIDriver{ const SPIConfig *config; #if SPI_USE_WAIT || defined(__DOXYGEN__) /** - * @brief Waiting thread. + * @brief Waiting thread. */ - Thread *thread; + thread_reference_t thread; #endif /* SPI_USE_WAIT */ #if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_USE_MUTEXES || defined(__DOXYGEN__) /** - * @brief Mutex protecting the bus. + * @brief Mutex protecting the peripheral. */ - Mutex mutex; -#elif CH_USE_SEMAPHORES - Semaphore semaphore; -#endif + mutex_t mutex; #endif /* SPI_USE_MUTUAL_EXCLUSION */ #if defined(SPI_DRIVER_EXT_FIELDS) SPI_DRIVER_EXT_FIELDS diff --git a/os/halnew/platforms/STM32/icu_lld.c b/os/halnew/platforms/STM32/icu_lld.c index 2e3c4334b..7941c7a44 100644 --- a/os/halnew/platforms/STM32/icu_lld.c +++ b/os/halnew/platforms/STM32/icu_lld.c @@ -26,7 +26,6 @@ * @{ */ -#include "ch.h" #include "hal.h" #if HAL_USE_ICU || defined(__DOXYGEN__) @@ -145,13 +144,13 @@ static void icu_lld_serve_interrupt(ICUDriver *icup) { * * @isr */ -CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) { +OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); icu_lld_serve_interrupt(&ICUD1); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #if !defined(STM32_TIM1_CC_HANDLER) @@ -165,13 +164,13 @@ CH_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) { * * @isr */ -CH_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) { +OSAL_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); icu_lld_serve_interrupt(&ICUD1); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif /* STM32_ICU_USE_TIM1 */ @@ -187,13 +186,13 @@ CH_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) { * * @isr */ -CH_IRQ_HANDLER(STM32_TIM2_HANDLER) { +OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); icu_lld_serve_interrupt(&ICUD2); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif /* STM32_ICU_USE_TIM2 */ @@ -209,13 +208,13 @@ CH_IRQ_HANDLER(STM32_TIM2_HANDLER) { * * @isr */ -CH_IRQ_HANDLER(STM32_TIM3_HANDLER) { +OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); icu_lld_serve_interrupt(&ICUD3); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif /* STM32_ICU_USE_TIM3 */ @@ -231,13 +230,13 @@ CH_IRQ_HANDLER(STM32_TIM3_HANDLER) { * * @isr */ -CH_IRQ_HANDLER(STM32_TIM4_HANDLER) { +OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); icu_lld_serve_interrupt(&ICUD4); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif /* STM32_ICU_USE_TIM4 */ @@ -253,13 +252,13 @@ CH_IRQ_HANDLER(STM32_TIM4_HANDLER) { * * @isr */ -CH_IRQ_HANDLER(STM32_TIM5_HANDLER) { +OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); icu_lld_serve_interrupt(&ICUD5); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif /* STM32_ICU_USE_TIM5 */ @@ -275,13 +274,13 @@ CH_IRQ_HANDLER(STM32_TIM5_HANDLER) { * * @isr */ -CH_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) { +OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); icu_lld_serve_interrupt(&ICUD8); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #if !defined(STM32_TIM8_CC_HANDLER) @@ -295,13 +294,13 @@ CH_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) { * * @isr */ -CH_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) { +OSAL_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); icu_lld_serve_interrupt(&ICUD8); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif /* STM32_ICU_USE_TIM8 */ @@ -317,13 +316,13 @@ CH_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) { * * @isr */ -CH_IRQ_HANDLER(STM32_TIM9_HANDLER) { +OSAL_IRQ_HANDLER(STM32_TIM9_HANDLER) { - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); icu_lld_serve_interrupt(&ICUD9); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } #endif /* STM32_ICU_USE_TIM9 */ @@ -391,9 +390,9 @@ void icu_lld_init(void) { void icu_lld_start(ICUDriver *icup) { uint32_t psc; - chDbgAssert((icup->config->channel == ICU_CHANNEL_1) || - (icup->config->channel == ICU_CHANNEL_2), - "icu_lld_start(), #1", "invalid input"); + osalDbgAssert((icup->config->channel == ICU_CHANNEL_1) || + (icup->config->channel == ICU_CHANNEL_2), + "icu_lld_start(), #1", "invalid input"); if (icup->state == ICU_STOP) { /* Clock activation and timer reset.*/ @@ -477,9 +476,9 @@ void icu_lld_start(ICUDriver *icup) { /* Timer configuration.*/ psc = (icup->clock / icup->config->frequency) - 1; - chDbgAssert((psc <= 0xFFFF) && - ((psc + 1) * icup->config->frequency) == icup->clock, - "icu_lld_start(), #1", "invalid frequency"); + osalDbgAssert((psc <= 0xFFFF) && + ((psc + 1) * icup->config->frequency) == icup->clock, + "icu_lld_start(), #1", "invalid frequency"); icup->tim->PSC = (uint16_t)psc; icup->tim->ARR = 0xFFFF; diff --git a/os/halnew/platforms/STM32/pwm_lld.c b/os/halnew/platforms/STM32/pwm_lld.c index 1e9e0adfb..cd5bb4e57 100644 --- a/os/halnew/platforms/STM32/pwm_lld.c +++ b/os/halnew/platforms/STM32/pwm_lld.c @@ -22,7 +22,6 @@ * @{ */ -#include "ch.h" #include "hal.h" #if HAL_USE_PWM || defined(__DOXYGEN__) @@ -100,10 +99,9 @@ PWMDriver PWMD9; /*===========================================================================*/ #if STM32_PWM_USE_TIM2 || STM32_PWM_USE_TIM3 || STM32_PWM_USE_TIM4 || \ - STM32_PWM_USE_TIM5 || STM32_PWM_USE_TIM8 || STM32_PWM_USE_TIM9 || \ - defined(__DOXYGEN__) + STM32_PWM_USE_TIM5 || STM32_PWM_USE_TIM9 || defined(__DOXYGEN__) /** - * @brief Common TIM2...TIM5 IRQ handler. + * @brief Common TIM2...TIM5,TIM9 IRQ handler. * @note It is assumed that the various sources are only activated if the * associated callback pointer is not equal to @p NULL in order to not * perform an extra check in a potentially critical interrupt handler. @@ -127,7 +125,7 @@ static void pwm_lld_serve_interrupt(PWMDriver *pwmp) { if ((sr & TIM_SR_UIF) != 0) pwmp->config->callback(pwmp); } -#endif /* STM32_PWM_USE_TIM2 || ... || STM32_PWM_USE_TIM5 */ +#endif /*===========================================================================*/ /* Driver interrupt handlers. */ diff --git a/os/halnew/platforms/STM32F30x/hal_lld.c b/os/halnew/platforms/STM32F30x/hal_lld.c index f536cae08..46ca8a7f9 100644 --- a/os/halnew/platforms/STM32F30x/hal_lld.c +++ b/os/halnew/platforms/STM32F30x/hal_lld.c @@ -22,7 +22,6 @@ * @{ */ -#include "ch.h" #include "hal.h" /*===========================================================================*/ diff --git a/os/halnew/platforms/STM32F30x/stm32_dma.c b/os/halnew/platforms/STM32F30x/stm32_dma.c index 71777583d..6b09cceb3 100644 --- a/os/halnew/platforms/STM32F30x/stm32_dma.c +++ b/os/halnew/platforms/STM32F30x/stm32_dma.c @@ -29,7 +29,6 @@ * @{ */ -#include "ch.h" #include "hal.h" /* The following macro is only defined if some driver requiring DMA services @@ -116,17 +115,17 @@ static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS]; * * @isr */ -CH_IRQ_HANDLER(Vector6C) { +OSAL_IRQ_HANDLER(Vector6C) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 0; if (dma_isr_redir[0].dma_func) dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -134,17 +133,17 @@ CH_IRQ_HANDLER(Vector6C) { * * @isr */ -CH_IRQ_HANDLER(Vector70) { +OSAL_IRQ_HANDLER(Vector70) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 4; if (dma_isr_redir[1].dma_func) dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -152,17 +151,17 @@ CH_IRQ_HANDLER(Vector70) { * * @isr */ -CH_IRQ_HANDLER(Vector74) { +OSAL_IRQ_HANDLER(Vector74) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 8; if (dma_isr_redir[2].dma_func) dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -170,17 +169,17 @@ CH_IRQ_HANDLER(Vector74) { * * @isr */ -CH_IRQ_HANDLER(Vector78) { +OSAL_IRQ_HANDLER(Vector78) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 12; if (dma_isr_redir[3].dma_func) dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -188,17 +187,17 @@ CH_IRQ_HANDLER(Vector78) { * * @isr */ -CH_IRQ_HANDLER(Vector7C) { +OSAL_IRQ_HANDLER(Vector7C) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 16; if (dma_isr_redir[4].dma_func) dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -206,17 +205,17 @@ CH_IRQ_HANDLER(Vector7C) { * * @isr */ -CH_IRQ_HANDLER(Vector80) { +OSAL_IRQ_HANDLER(Vector80) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 20; if (dma_isr_redir[5].dma_func) dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -224,17 +223,17 @@ CH_IRQ_HANDLER(Vector80) { * * @isr */ -CH_IRQ_HANDLER(Vector84) { +OSAL_IRQ_HANDLER(Vector84) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK; DMA1->IFCR = STM32_DMA_ISR_MASK << 24; if (dma_isr_redir[6].dma_func) dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -242,17 +241,17 @@ CH_IRQ_HANDLER(Vector84) { * * @isr */ -CH_IRQ_HANDLER(Vector120) { +OSAL_IRQ_HANDLER(Vector120) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK; DMA2->IFCR = STM32_DMA_ISR_MASK << 0; if (dma_isr_redir[7].dma_func) dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -260,17 +259,17 @@ CH_IRQ_HANDLER(Vector120) { * * @isr */ -CH_IRQ_HANDLER(Vector124) { +OSAL_IRQ_HANDLER(Vector124) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK; DMA2->IFCR = STM32_DMA_ISR_MASK << 4; if (dma_isr_redir[8].dma_func) dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -278,17 +277,17 @@ CH_IRQ_HANDLER(Vector124) { * * @isr */ -CH_IRQ_HANDLER(Vector128) { +OSAL_IRQ_HANDLER(Vector128) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK; DMA2->IFCR = STM32_DMA_ISR_MASK << 8; if (dma_isr_redir[9].dma_func) dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -296,17 +295,17 @@ CH_IRQ_HANDLER(Vector128) { * * @isr */ -CH_IRQ_HANDLER(Vector12C) { +OSAL_IRQ_HANDLER(Vector12C) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK; DMA2->IFCR = STM32_DMA_ISR_MASK << 12; if (dma_isr_redir[10].dma_func) dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /** @@ -314,17 +313,17 @@ CH_IRQ_HANDLER(Vector12C) { * * @isr */ -CH_IRQ_HANDLER(Vector130) { +OSAL_IRQ_HANDLER(Vector130) { uint32_t flags; - CH_IRQ_PROLOGUE(); + OSAL_IRQ_PROLOGUE(); flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK; DMA2->IFCR = STM32_DMA_ISR_MASK << 16; if (dma_isr_redir[11].dma_func) dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags); - CH_IRQ_EPILOGUE(); + OSAL_IRQ_EPILOGUE(); } /*===========================================================================*/ @@ -379,7 +378,7 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, stm32_dmaisr_t func, void *param) { - chDbgCheck(dmastp != NULL, "dmaStreamAllocate"); + osalDbgCheck(dmastp != NULL); /* Checks if the stream is already taken.*/ if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0) @@ -424,11 +423,11 @@ bool_t dmaStreamAllocate(const stm32_dma_stream_t *dmastp, */ void dmaStreamRelease(const stm32_dma_stream_t *dmastp) { - chDbgCheck(dmastp != NULL, "dmaStreamRelease"); + osalDbgCheck(dmastp != NULL); /* Check if the streams is not taken.*/ - chDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, - "dmaStreamRelease(), #1", "not allocated"); + osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0, + "dmaStreamRelease(), #1", "not allocated"); /* Disables the associated IRQ vector.*/ nvicDisableVector(dmastp->vector); diff --git a/os/halnew/src/spi.c b/os/halnew/src/spi.c index b9b4c866a..cd7124bd3 100644 --- a/os/halnew/src/spi.c +++ b/os/halnew/src/spi.c @@ -77,7 +77,7 @@ void spiObjectInit(SPIDriver *spip) { spip->thread = NULL; #endif /* SPI_USE_WAIT */ #if SPI_USE_MUTUAL_EXCLUSION - osalMutexInit(&spip->mutex); + osalMutexObjectInit(&spip->mutex); #endif /* SPI_USE_MUTUAL_EXCLUSION */ #if defined(SPI_DRIVER_EXT_INIT_HOOK) SPI_DRIVER_EXT_INIT_HOOK(spip);