git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4976 35acf78f-673a-0410-8e92-d51de3d6d3f4
gdisirio
parent
cc94e31e38
commit
1c4914bb0d
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@ -35,12 +35,6 @@
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/* Driver local definitions. */
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/*===========================================================================*/
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#if STM32_ADC_USE_ADC12 || STM32_ADC_USE_ADC34
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#define STM32_ADC_DUAL_MODE TRUE
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#else
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#define STM32_ADC_DUAL_MODE FALSE
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#endif
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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@ -50,6 +44,11 @@
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ADCDriver ADCD1;
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#endif
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/** @brief ADC1 driver identifier.*/
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#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
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ADCDriver ADCD3;
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#endif
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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@ -78,7 +77,7 @@ static void adc_lld_stop_adc(ADC_TypeDef *adc) {
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* @param[in] adcp pointer to the @p ADCDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*/
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static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
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static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) {
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/* DMA errors handling.*/
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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@ -102,44 +101,102 @@ static void adc_lld_serve_rx_interrupt(ADCDriver *adcp, uint32_t flags) {
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}
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}
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/**
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* @brief ADC ISR service routine.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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* @param[in] isr pre-shifted content of the ISR register
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*/
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static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) {
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/* It could be a spurious interrupt caused by overflows after DMA disabling,
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just ignore it in this case.*/
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if (adcp->grpp != NULL) {
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/* Note, an overflow may occur after the conversion ended before the driver
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is able to stop the ADC, this is why the DMA channel is checked too.*/
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if ((isr & ADC_ISR_OVR) &&
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(dmaStreamGetTransactionSize(adcp->dmastp) > 0)) {
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/* ADC overflow condition, this could happen only if the DMA is unable
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to read data fast enough.*/
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_adc_isr_error_code(adcp, ADC_ERR_OVERFLOW);
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}
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if (isr & ADC_ISR_AWD) {
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/* Analog watchdog error.*/
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_adc_isr_error_code(adcp, ADC_ERR_AWD);
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}
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}
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
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/**
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* @brief ADC interrupt handler.
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* @brief ADC1/ADC2 interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(ADC1_COMP_IRQHandler) {
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CH_IRQ_HANDLER(Vector88) {
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uint32_t isr;
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CH_IRQ_PROLOGUE();
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isr = ADC1->ISR;
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#if STM32_ADC_DUAL_MODE
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isr = ADC1->ISR;
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isr |= ADC2->ISR;
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ADC1->ISR = isr;
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ADC2->ISR = isr;
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#else /* !STM32_ADC_DUAL_MODE */
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isr = ADC1->ISR;
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ADC1->ISR = isr;
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#endif /* !STM32_ADC_DUAL_MODE */
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/* It could be a spurious interrupt caused by overflows after DMA disabling,
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just ignore it in this case.*/
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if (ADCD1.grpp != NULL) {
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/* Note, an overflow may occur after the conversion ended before the driver
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is able to stop the ADC, this is why the DMA channel is checked too.*/
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if ((isr & ADC_ISR_OVR) &&
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(dmaStreamGetTransactionSize(ADCD1.dmastp) > 0)) {
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/* ADC overflow condition, this could happen only if the DMA is unable
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to read data fast enough.*/
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_adc_isr_error_code(&ADCD1, ADC_ERR_OVERFLOW);
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}
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if (isr & ADC_ISR_AWD) {
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/* Analog watchdog error.*/
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_adc_isr_error_code(&ADCD1, ADC_ERR_AWD);
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}
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}
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adc_lld_serve_interrupt(&ADCD1, isr);
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CH_IRQ_EPILOGUE();
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}
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#endif
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#endif /* STM32_ADC_USE_ADC1 */
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#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
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/**
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* @brief ADC3 interrupt handler.
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*
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* @isr
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*/
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CH_IRQ_HANDLER(VectorFC) {
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uint32_t isr;
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CH_IRQ_PROLOGUE();
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isr = ADC3->ISR;
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ADC3->ISR = isr;
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adc_lld_serve_interrupt(&ADCD3, isr);
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CH_IRQ_EPILOGUE();
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}
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#if STM32_ADC_DUAL_MODE
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/**
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* @brief ADC4 interrupt handler (as ADC3 slave).
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*
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* @isr
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*/
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CH_IRQ_HANDLER(Vector134) {
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uint32_t isr;
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CH_IRQ_PROLOGUE();
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isr = ADC4->ISR;
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ADC4->ISR = isr;
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adc_lld_serve_interrupt(&ADCD3, isr);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_ADC_DUAL_MODE */
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#endif /* STM32_ADC_USE_ADC3 */
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/*===========================================================================*/
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/* Driver exported functions. */
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@ -194,7 +251,7 @@ void adc_lld_start(ADCDriver *adcp) {
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bool_t b;
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b = dmaStreamAllocate(adcp->dmastp,
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STM32_ADC_ADC1_DMA_IRQ_PRIORITY,
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(stm32_dmaisr_t)adc_lld_serve_rx_interrupt,
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(stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
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(void *)adcp);
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chDbgAssert(!b, "adc_lld_start(), #1", "stream already allocated");
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dmaStreamSetPeripheral(adcp->dmastp, &ADC1->DR);
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@ -152,14 +152,7 @@
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#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
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#define STM32_ADC_USE_ADC1 FALSE
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#endif
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/**
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* @brief ADC1+ADC2 driver enable switch.
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* @details If set to @p TRUE the support for ADC1+ADC2 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_ADC_USE_ADC12) || defined(__DOXYGEN__)
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#define STM32_ADC_USE_ADC12 FALSE
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#endif
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/**
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* @brief ADC3 driver enable switch.
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* @details If set to @p TRUE the support for ADC3 is included.
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@ -168,69 +161,68 @@
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#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__)
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#define STM32_ADC_USE_ADC3 FALSE
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#endif
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/**
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* @brief ADC3+ADC4 driver enable switch.
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* @details If set to @p TRUE the support for ADC3+ADC4 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_ADC_USE_ADC34) || defined(__DOXYGEN__)
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#define STM32_ADC_USE_ADC34 FALSE
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#endif
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/**
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* @brief ADC1/ADC2 DMA priority (0..3|lowest..highest).
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*/
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#if !defined(STM32_ADC_ADC12_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC12_DMA_PRIORITY 2
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#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#endif
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/**
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* @brief ADC3/ADC4 DMA priority (0..3|lowest..highest).
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*/
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#if !defined(STM32_ADC_ADC34_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC34_DMA_PRIORITY 2
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#if !defined(STM32_ADC_ADC3_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC3_DMA_PRIORITY 2
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#endif
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/**
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* @brief ADC1/ADC2 interrupt priority level setting.
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*/
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#if !defined(STM32_ADC_ADC12_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC12_IRQ_PRIORITY 2
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#if !defined(STM32_ADC_ADC1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC1_IRQ_PRIORITY 2
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#endif
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/**
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* @brief ADC3/ADC4 interrupt priority level setting.
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*/
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#if !defined(STM32_ADC34_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC34_IRQ_PRIORITY 2
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#if !defined(STM32_ADC3_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC3_IRQ_PRIORITY 2
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#endif
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/**
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* @brief ADC1/ADC2 DMA interrupt priority level setting.
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*/
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#if !defined(STM32_ADC_ADC12_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY 2
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#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
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#endif
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/**
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* @brief ADC3/ADC4 DMA interrupt priority level setting.
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*/
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#if !defined(STM32_ADC_ADC34_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY 2
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#if !defined(STM32_ADC_ADC3_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 2
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#endif
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/**
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* @brief ADC1/ADC2 clock source and mode.
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*/
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#if !defined(STM32_ADC_ADC12_CLOCK_MODE) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
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#if !defined(STM32_ADC_ADC1_CLOCK_MODE) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
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#endif
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/**
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* @brief ADC3/ADC4 clock source and mode.
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*/
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#if !defined(STM32_ADC_ADC34_CLOCK_MODE) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC34_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
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#if !defined(STM32_ADC_ADC3_CLOCK_MODE) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
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#endif
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/**
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* @brief Enables the ADC master/slave mode.
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*/
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#if !defined(STM32_ADC_DUAL_MODE) || defined(__DOXYGEN__)
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#define STM32_ADC_DUAL_MODE FALSE
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#endif
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/** @} */
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@ -242,113 +234,74 @@
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#error "ADC1 not present in the selected device"
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#endif
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#if STM32_ADC_USE_ADC12 && (!STM32_HAS_ADC1 || !STM32_HAS_ADC2)
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#error "ADC12 not present in the selected device"
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#endif
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#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3
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#error "ADC3 not present in the selected device"
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#endif
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#if STM32_ADC_USE_ADC34 && (!STM32_HAS_ADC3 || !STM32_HAS_ADC4)
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#error "ADC34 not present in the selected device"
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#endif
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#if !STM32_ADC_USE_ADC1 || !STM32_ADC_USE_ADC12 || \
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!STM32_ADC_USE_ADC3 || !STM32_ADC_USE_ADC34
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#if !STM32_ADC_USE_ADC1 ||!STM32_ADC_USE_ADC3
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#error "ADC driver activated but no ADC peripheral assigned"
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#endif
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#if STM32_ADC_USE_ADC1 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY)
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to ADC1"
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#endif
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#if STM32_ADC_USE_ADC1 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_DMA_IRQ_PRIORITY)
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to ADC1 DMA"
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#endif
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#if STM32_ADC_USE_ADC1 && \
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!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC12_DMA_PRIORITY)
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!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to ADC1"
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#endif
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#if STM32_ADC_USE_ADC12 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to ADC12"
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#endif
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#if STM32_ADC_USE_ADC12 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_DMA_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to ADC12 DMA"
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#endif
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#if STM32_ADC_USE_ADC12 && \
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!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC12_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to ADC12"
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#endif
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#if STM32_ADC_USE_ADC3 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_IRQ_PRIORITY)
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC3_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to ADC3"
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#endif
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#if STM32_ADC_USE_ADC3 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_DMA_IRQ_PRIORITY)
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC3_DMA_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to ADC3 DMA"
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#endif
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#if STM32_ADC_USE_ADC3 && \
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!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC34_DMA_PRIORITY)
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!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC3_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to ADC3"
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#endif
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#if STM32_ADC_USE_ADC34 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to ADC34"
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#endif
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#if STM32_ADC_USE_ADC34 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_DMA_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to ADC34 DMA"
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#endif
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#if STM32_ADC_USE_ADC34 && \
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!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC34_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to ADC34"
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#endif
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#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
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#define STM32_ADC12_CLOCK STM32ADC12CLK
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#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
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#define STM32_ADC12_CLOCK (STM32_HCLK / 1)
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#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
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#define STM32_ADC12_CLOCK (STM32_HCLK / 2)
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#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
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#define STM32_ADC12_CLOCK (STM32_HCLK / 4)
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#if STM32_ADC_ADC1_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
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#define STM32_ADC1_CLOCK STM32ADC1CLK
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#elif STM32_ADC_ADC1_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
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#define STM32_ADC1_CLOCK (STM32_HCLK / 1)
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#elif STM32_ADC_ADC1_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
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#define STM32_ADC1_CLOCK (STM32_HCLK / 2)
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#elif STM32_ADC_ADC1_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
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#define STM32_ADC1_CLOCK (STM32_HCLK / 4)
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#else
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#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
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#error "invalid clock mode selected for STM32_ADC_ADC1_CLOCK_MODE"
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#endif
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#if STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
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#define STM32_ADC34_CLOCK STM32ADC34CLK
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#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
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#define STM32_ADC34_CLOCK (STM32_HCLK / 1)
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#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
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#define STM32_ADC34_CLOCK (STM32_HCLK / 2)
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#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
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#define STM32_ADC34_CLOCK (STM32_HCLK / 4)
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#if STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
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#define STM32_ADC3_CLOCK STM32ADC3CLK
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#elif STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
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#define STM32_ADC3_CLOCK (STM32_HCLK / 1)
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#elif STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
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#define STM32_ADC3_CLOCK (STM32_HCLK / 2)
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#elif STM32_ADC_ADC3_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
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#define STM32_ADC3_CLOCK (STM32_HCLK / 4)
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#else
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#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
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#error "invalid clock mode selected for STM32_ADC_ADC1_CLOCK_MODE"
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||||
#endif
|
||||
|
||||
#if STM32_ADC12_CLOCK > 72000000
|
||||
#error "STM32_ADC12_CLOCK exceeding maximum frequency (72000000)"
|
||||
#if STM32_ADC1_CLOCK > 72000000
|
||||
#error "STM32_ADC1_CLOCK exceeding maximum frequency (72000000)"
|
||||
#endif
|
||||
|
||||
#if STM32_ADC34_CLOCK > 72000000
|
||||
#error "STM32_ADC34_CLOCK exceeding maximum frequency (72000000)"
|
||||
#if STM32_ADC3_CLOCK > 72000000
|
||||
#error "STM32_ADC3_CLOCK exceeding maximum frequency (72000000)"
|
||||
#endif
|
||||
|
||||
#if !defined(STM32_DMA_REQUIRED)
|
||||
|
|
@ -442,37 +395,24 @@ typedef struct {
|
|||
*/
|
||||
uint32_t tr1;
|
||||
/**
|
||||
* @brief ADC SMPR1 register initialization data.
|
||||
* @details In this field must be specified the sample times for channels
|
||||
* 0...9.
|
||||
* @brief ADC SMPRx registers initialization data.
|
||||
*/
|
||||
uint32_t smpr1;
|
||||
uint32_t smpr[2];
|
||||
/**
|
||||
* @brief ADC SMPR2 register initialization data.
|
||||
* @details In this field must be specified the sample times for channels
|
||||
* 10...18.
|
||||
* @brief ADC SQRx register initialization data.
|
||||
*/
|
||||
uint32_t smpr2;
|
||||
uint32_t sqr[4];
|
||||
#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief ADC SQR1 register initialization data.
|
||||
* @details Conversion group sequence 1...4 + sequence length.
|
||||
* @brief Slave ADC SMPRx registers initialization data.
|
||||
*/
|
||||
uint32_t sqr1;
|
||||
uint32_t ssmpr[2];
|
||||
/**
|
||||
* @brief ADC SQR2 register initialization data.
|
||||
* @details Conversion group sequence 5...9.
|
||||
* @brief Slave ADC SQRx register initialization data.
|
||||
*/
|
||||
uint32_t sqr2;
|
||||
/**
|
||||
* @brief ADC SQR3 register initialization data.
|
||||
* @details Conversion group sequence 10...15.
|
||||
*/
|
||||
uint32_t sqr3;
|
||||
/**
|
||||
* @brief ADC SQR4 register initialization data.
|
||||
* @details Conversion group sequence 16...17.
|
||||
*/
|
||||
uint32_t sqr4;
|
||||
uint32_t ssqr[4];
|
||||
|
||||
#endif /* STM32_ADC_DUAL_MODE */
|
||||
} ADCConversionGroup;
|
||||
|
||||
/**
|
||||
|
|
@ -531,10 +471,12 @@ struct ADCDriver {
|
|||
* @brief Pointer to the master ADCx registers block.
|
||||
*/
|
||||
ADC_TypeDef *adcm;
|
||||
#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)
|
||||
/**
|
||||
* @brief Pointer to the slave ADCx registers block.
|
||||
*/
|
||||
ADC_TypeDef *adcs;
|
||||
#endif /* STM32_ADC_DUAL_MODE */
|
||||
/**
|
||||
* @brief Pointer to associated DMA channel.
|
||||
*/
|
||||
|
|
@ -612,18 +554,10 @@ struct ADCDriver {
|
|||
extern ADCDriver ADCD1;
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC12 && !defined(__DOXYGEN__)
|
||||
extern ADCDriver ADCD12;
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__)
|
||||
extern ADCDriver ADCD3;
|
||||
#endif
|
||||
|
||||
#if STM32_ADC_USE_ADC34 && !defined(__DOXYGEN__)
|
||||
extern ADCDriver ADCD34;
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -67,10 +67,25 @@
|
|||
#define STM32_USB_CLOCK_REQUIRED TRUE
|
||||
#define STM32_USBPRE STM32_USBPRE_DIV1P5
|
||||
|
||||
/*
|
||||
* ADC driver system settings.
|
||||
*/
|
||||
#define STM32_ADC_USE_ADC1 FALSE
|
||||
#define STM32_ADC_USE_ADC3 FALSE
|
||||
#define STM32_ADC_ADC1_DMA_PRIORITY 2
|
||||
#define STM32_ADC_ADC3_DMA_PRIORITY 2
|
||||
#define STM32_ADC_ADC1_IRQ_PRIORITY 2
|
||||
#define STM32_ADC_ADC3_IRQ_PRIORITY 2
|
||||
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
|
||||
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 2
|
||||
#define STM32_ADC_ADC1_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
|
||||
#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_AHB_DIV1
|
||||
#define STM32_ADC_DUAL_MODE FALSE
|
||||
|
||||
/*
|
||||
* CAN driver system settings.
|
||||
*/
|
||||
#define STM32_CAN_USE_CAN1 TRUE
|
||||
#define STM32_CAN_USE_CAN1 FALSE
|
||||
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
|
||||
|
||||
/*
|
||||
|
|
|
|||
Loading…
Reference in New Issue