From 1af4c11ea944cf8e0fd9646758cccf52f3783f33 Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Mon, 23 Nov 2009 21:48:24 +0000
Subject: [PATCH] git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1321
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/io/platforms/STM32/adc_lld.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/os/io/platforms/STM32/adc_lld.c b/os/io/platforms/STM32/adc_lld.c
index 7e362e50b..567b03a2a 100644
--- a/os/io/platforms/STM32/adc_lld.c
+++ b/os/io/platforms/STM32/adc_lld.c
@@ -117,6 +117,7 @@ void adc_lld_init(void) {
   ADCD1.ad_dmaprio = STM32_ADC1_DMA_PRIORITY << 12;
 
   /* Temporary activation.*/
+  RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;
   ADC1->CR1 = 0;
   ADC1->CR2 = ADC_CR2_ADON;
 
@@ -132,6 +133,7 @@ void adc_lld_init(void) {
 
   /* Return the ADC in low power mode.*/
   ADC1->CR2 = 0;
+  RCC->APB2ENR &= ~RCC_APB2ENR_ADC1EN;
 #endif
 }
 
@@ -149,8 +151,6 @@ void adc_lld_start(ADCDriver *adcp) {
       dmaEnable(DMA1_ID);   /* NOTE: Must be enabled before the IRQs.*/
       NVICEnableVector(DMA1_Channel1_IRQn, STM32_ADC1_IRQ_PRIORITY);
       DMA1_Channel1->CPAR = (uint32_t)&ADC1->DR;
-/*      RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_ADCPRE) |
-                  adcp->ad_config->ac_prescaler;*/
       RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;
     }
 #endif