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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5863 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2013-06-17 07:01:48 +00:00
parent e02105736d
commit 1a76b0008f
15 changed files with 144 additions and 60 deletions
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6
demos/PPC-SPC560D-GCC/mcuconf.h
View File

@ -215,6 +215,12 @@
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID 4
#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID 5
#define SPC5_SPI_DSPI0_RX_DMA_CH_ID 6
#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 7
#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 8
#define SPC5_SPI_DSPI1_RX_DMA_CH_ID 9
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI0_IRQ_PRIO 10

15
demos/PPC-SPC560P-GCC/mcuconf.h
View File

@ -222,6 +222,21 @@
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID 4
#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID 5
#define SPC5_SPI_DSPI0_RX_DMA_CH_ID 6
#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 7
#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 8
#define SPC5_SPI_DSPI1_RX_DMA_CH_ID 9
#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID 10
#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID 11
#define SPC5_SPI_DSPI2_RX_DMA_CH_ID 12
#define SPC5_SPI_DSPI3_TX1_DMA_CH_ID 13
#define SPC5_SPI_DSPI3_TX2_DMA_CH_ID 14
#define SPC5_SPI_DSPI3_RX_DMA_CH_ID 15
#define SPC5_SPI_DSPI4_TX1_DMA_CH_ID 1
#define SPC5_SPI_DSPI4_TX2_DMA_CH_ID 2
#define SPC5_SPI_DSPI4_RX_DMA_CH_ID 3
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10

9
demos/PPC-SPC56EL-GCC/mcuconf.h
View File

@ -259,6 +259,15 @@
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID 4
#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID 5
#define SPC5_SPI_DSPI0_RX_DMA_CH_ID 6
#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 7
#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 8
#define SPC5_SPI_DSPI1_RX_DMA_CH_ID 9
#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID 10
#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID 11
#define SPC5_SPI_DSPI2_RX_DMA_CH_ID 12
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10

6
os/hal/platforms/SPC560Dxx/spc560d_registry.h
View File

@ -42,12 +42,6 @@
#define SPC5_DSPI_FIFO_DEPTH 4
#define SPC5_DSPI0_PCTL 4
#define SPC5_DSPI1_PCTL 5
#define SPC5_DSPI0_TX1_DMA_CH_ID 4
#define SPC5_DSPI0_TX2_DMA_CH_ID 5
#define SPC5_DSPI0_RX_DMA_CH_ID 6
#define SPC5_DSPI1_TX1_DMA_CH_ID 7
#define SPC5_DSPI1_TX2_DMA_CH_ID 8
#define SPC5_DSPI1_RX_DMA_CH_ID 9
#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
#define SPC5_DSPI0_RX_DMA_DEV_ID 2

15
os/hal/platforms/SPC560Pxx/spc560p_registry.h
View File

@ -93,15 +93,6 @@
#define SPC5_DSPI0_PCTL 4
#define SPC5_DSPI1_PCTL 5
#define SPC5_DSPI2_PCTL 6
#define SPC5_DSPI0_TX1_DMA_CH_ID 4
#define SPC5_DSPI0_TX2_DMA_CH_ID 5
#define SPC5_DSPI0_RX_DMA_CH_ID 6
#define SPC5_DSPI1_TX1_DMA_CH_ID 7
#define SPC5_DSPI1_TX2_DMA_CH_ID 8
#define SPC5_DSPI1_RX_DMA_CH_ID 9
#define SPC5_DSPI2_TX1_DMA_CH_ID 10
#define SPC5_DSPI2_TX2_DMA_CH_ID 11
#define SPC5_DSPI2_RX_DMA_CH_ID 12
#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
#define SPC5_DSPI0_RX_DMA_DEV_ID 2
@ -133,9 +124,6 @@
#if defined(_SPC560PXX_MEDIUM_) || defined(_SPC560PXX_LARGE_)
#define SPC5_HAS_DSPI3 TRUE
#define SPC5_DSPI3_PCTL 7
#define SPC5_DSPI3_TX1_DMA_CH_ID 13
#define SPC5_DSPI3_TX2_DMA_CH_ID 14
#define SPC5_DSPI3_RX_DMA_CH_ID 15
#define SPC5_DSPI3_TX1_DMA_DEV_ID 7
#define SPC5_DSPI3_TX2_DMA_DEV_ID 0
#define SPC5_DSPI3_RX_DMA_DEV_ID 8
@ -152,9 +140,6 @@
#if defined(_SPC560PXX_LARGE_)
#define SPC5_HAS_DSPI4 TRUE
#define SPC5_DSPI4_PCTL 8
#define SPC5_DSPI4_TX1_DMA_CH_ID 1
#define SPC5_DSPI4_TX2_DMA_CH_ID 2
#define SPC5_DSPI4_RX_DMA_CH_ID 3
#define SPC5_DSPI4_TX1_DMA_DEV_ID 15
#define SPC5_DSPI4_TX2_DMA_DEV_ID 0
#define SPC5_DSPI4_RX_DMA_DEV_ID 21

12
os/hal/platforms/SPC563Mxx/spc563m_registry.h
View File

@ -40,12 +40,6 @@
#define SPC5_HAS_DSPI3 FALSE
#define SPC5_HAS_DSPI4 FALSE
#define SPC5_DSPI_FIFO_DEPTH 16
#define SPC5_DSPI1_TX1_DMA_CH_ID 12
#define SPC5_DSPI1_TX2_DMA_CH_ID 25
#define SPC5_DSPI1_RX_DMA_CH_ID 13
#define SPC5_DSPI2_TX1_DMA_CH_ID 14
#define SPC5_DSPI2_TX2_DMA_CH_ID 26
#define SPC5_DSPI2_RX_DMA_CH_ID 15
#define SPC5_DSPI1_EOQF_HANDLER vector132
#define SPC5_DSPI1_EOQF_NUMBER 132
#define SPC5_DSPI1_TFFF_HANDLER vector133
@ -63,6 +57,12 @@
#define SPC5_HAS_EDMA TRUE
#define SPC5_EDMA_NCHANNELS 32
#define SPC5_EDMA_HAS_MUX FALSE
#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 12
#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 25
#define SPC5_SPI_DSPI1_RX_DMA_CH_ID 13
#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID 14
#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID 26
#define SPC5_SPI_DSPI2_RX_DMA_CH_ID 15
/* eQADC attributes.*/
#define SPC5_HAS_EQADC TRUE

18
os/hal/platforms/SPC564Axx/spc564a_registry.h
View File

@ -54,15 +54,6 @@
#define SPC5_HAS_DSPI3 TRUE
#define SPC5_HAS_DSPI4 FALSE
#define SPC5_DSPI_FIFO_DEPTH 16
#define SPC5_DSPI1_TX1_DMA_CH_ID 12
#define SPC5_DSPI1_TX2_DMA_CH_ID 24
#define SPC5_DSPI1_RX_DMA_CH_ID 13
#define SPC5_DSPI2_TX1_DMA_CH_ID 14
#define SPC5_DSPI2_TX2_DMA_CH_ID 25
#define SPC5_DSPI2_RX_DMA_CH_ID 15
#define SPC5_DSPI3_TX1_DMA_CH_ID 16
#define SPC5_DSPI3_TX2_DMA_CH_ID 26
#define SPC5_DSPI3_RX_DMA_CH_ID 17
#define SPC5_DSPI1_EOQF_HANDLER vector132
#define SPC5_DSPI1_EOQF_NUMBER 132
#define SPC5_DSPI1_TFFF_HANDLER vector133
@ -86,6 +77,15 @@
#define SPC5_HAS_EDMA TRUE
#define SPC5_EDMA_NCHANNELS 64
#define SPC5_EDMA_HAS_MUX FALSE
#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 12
#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 24
#define SPC5_SPI_DSPI1_RX_DMA_CH_ID 13
#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID 14
#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID 25
#define SPC5_SPI_DSPI2_RX_DMA_CH_ID 15
#define SPC5_SPI_DSPI3_TX1_DMA_CH_ID 16
#define SPC5_SPI_DSPI3_TX2_DMA_CH_ID 26
#define SPC5_SPI_DSPI3_RX_DMA_CH_ID 17
/* eQADC attributes.*/
#define SPC5_HAS_EQADC TRUE

9
os/hal/platforms/SPC56ELxx/spc56el_registry.h
View File

@ -48,15 +48,6 @@
#define SPC5_DSPI0_PCTL 4
#define SPC5_DSPI1_PCTL 5
#define SPC5_DSPI2_PCTL 6
#define SPC5_DSPI0_TX1_DMA_CH_ID 4
#define SPC5_DSPI0_TX2_DMA_CH_ID 5
#define SPC5_DSPI0_RX_DMA_CH_ID 6
#define SPC5_DSPI1_TX1_DMA_CH_ID 7
#define SPC5_DSPI1_TX2_DMA_CH_ID 8
#define SPC5_DSPI1_RX_DMA_CH_ID 9
#define SPC5_DSPI2_TX1_DMA_CH_ID 10
#define SPC5_DSPI2_TX2_DMA_CH_ID 11
#define SPC5_DSPI2_RX_DMA_CH_ID 12
#define SPC5_DSPI0_TX1_DMA_DEV_ID 1
#define SPC5_DSPI0_TX2_DMA_DEV_ID 0
#define SPC5_DSPI0_RX_DMA_DEV_ID 2

30
os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.c
View File

@ -94,7 +94,7 @@ SPIDriver SPID5;
* @brief DMA configuration for DSPI0 TX1.
*/
static const edma_channel_config_t spi_dspi0_tx1_dma_config = {
SPC5_DSPI0_TX1_DMA_CH_ID,
SPC5_SPI_DSPI0_TX1_DMA_CH_ID,
#if SPC5_EDMA_HAS_MUX
SPC5_DSPI0_TX1_DMA_DEV_ID,
#endif
@ -106,7 +106,7 @@ static const edma_channel_config_t spi_dspi0_tx1_dma_config = {
* @brief DMA configuration for DSPI0 TX2.
*/
static const edma_channel_config_t spi_dspi0_tx2_dma_config = {
SPC5_DSPI0_TX2_DMA_CH_ID,
SPC5_SPI_DSPI0_TX2_DMA_CH_ID,
#if SPC5_EDMA_HAS_MUX
0,
#endif
@ -118,7 +118,7 @@ static const edma_channel_config_t spi_dspi0_tx2_dma_config = {
* @brief DMA configuration for DSPI0 RX.
*/
static const edma_channel_config_t spi_dspi0_rx_dma_config = {
SPC5_DSPI0_RX_DMA_CH_ID,
SPC5_SPI_DSPI0_RX_DMA_CH_ID,
#if SPC5_EDMA_HAS_MUX
SPC5_DSPI0_RX_DMA_DEV_ID,
#endif
@ -132,7 +132,7 @@ static const edma_channel_config_t spi_dspi0_rx_dma_config = {
* @brief DMA configuration for DSPI1 TX1.
*/
static const edma_channel_config_t spi_dspi1_tx1_dma_config = {
SPC5_DSPI1_TX1_DMA_CH_ID,
SPC5_SPI_DSPI1_TX1_DMA_CH_ID,
#if SPC5_EDMA_HAS_MUX
SPC5_DSPI1_TX1_DMA_DEV_ID,
#endif
@ -144,7 +144,7 @@ static const edma_channel_config_t spi_dspi1_tx1_dma_config = {
* @brief DMA configuration for DSPI1 TX2.
*/
static const edma_channel_config_t spi_dspi1_tx2_dma_config = {
SPC5_DSPI1_TX2_DMA_CH_ID,
SPC5_SPI_DSPI1_TX2_DMA_CH_ID,
#if SPC5_EDMA_HAS_MUX
0,
#endif
@ -156,7 +156,7 @@ static const edma_channel_config_t spi_dspi1_tx2_dma_config = {
* @brief DMA configuration for DSPI1 RX.
*/
static const edma_channel_config_t spi_dspi1_rx_dma_config = {
SPC5_DSPI1_RX_DMA_CH_ID,
SPC5_SPI_DSPI1_RX_DMA_CH_ID,
#if SPC5_EDMA_HAS_MUX
SPC5_DSPI1_RX_DMA_DEV_ID,
#endif
@ -170,7 +170,7 @@ static const edma_channel_config_t spi_dspi1_rx_dma_config = {
* @brief DMA configuration for DSPI2 TX1.
*/
static const edma_channel_config_t spi_dspi2_tx1_dma_config = {
SPC5_DSPI2_TX1_DMA_CH_ID,
SPC5_SPI_DSPI2_TX1_DMA_CH_ID,
#if SPC5_EDMA_HAS_MUX
SPC5_DSPI2_TX1_DMA_DEV_ID,
#endif
@ -182,7 +182,7 @@ static const edma_channel_config_t spi_dspi2_tx1_dma_config = {
* @brief DMA configuration for DSPI2 TX2.
*/
static const edma_channel_config_t spi_dspi2_tx2_dma_config = {
SPC5_DSPI2_TX2_DMA_CH_ID,
SPC5_SPI_DSPI2_TX2_DMA_CH_ID,
#if SPC5_EDMA_HAS_MUX
0,
#endif
@ -194,7 +194,7 @@ static const edma_channel_config_t spi_dspi2_tx2_dma_config = {
* @brief DMA configuration for DSPI2 RX.
*/
static const edma_channel_config_t spi_dspi2_rx_dma_config = {
SPC5_DSPI2_RX_DMA_CH_ID,
SPC5_SPI_DSPI2_RX_DMA_CH_ID,
#if SPC5_EDMA_HAS_MUX
SPC5_DSPI2_RX_DMA_DEV_ID,
#endif
@ -208,7 +208,7 @@ static const edma_channel_config_t spi_dspi2_rx_dma_config = {
* @brief DMA configuration for DSPI3 TX1.
*/
static const edma_channel_config_t spi_dspi3_tx1_dma_config = {
SPC5_DSPI3_TX1_DMA_CH_ID,
SPC5_SPI_DSPI3_TX1_DMA_CH_ID,
#if SPC5_EDMA_HAS_MUX
SPC5_DSPI3_TX1_DMA_DEV_ID,
#endif
@ -220,7 +220,7 @@ static const edma_channel_config_t spi_dspi3_tx1_dma_config = {
* @brief DMA configuration for DSPI3 TX2.
*/
static const edma_channel_config_t spi_dspi3_tx2_dma_config = {
SPC5_DSPI3_TX2_DMA_CH_ID,
SPC5_SPI_DSPI3_TX2_DMA_CH_ID,
#if SPC5_EDMA_HAS_MUX
0,
#endif
@ -232,7 +232,7 @@ static const edma_channel_config_t spi_dspi3_tx2_dma_config = {
* @brief DMA configuration for DSPI3 RX.
*/
static const edma_channel_config_t spi_dspi3_rx_dma_config = {
SPC5_DSPI3_RX_DMA_CH_ID,
SPC5_SPI_DSPI3_RX_DMA_CH_ID,
#if SPC5_EDMA_HAS_MUX
SPC5_DSPI3_RX_DMA_DEV_ID,
#endif
@ -246,7 +246,7 @@ static const edma_channel_config_t spi_dspi3_rx_dma_config = {
* @brief DMA configuration for DSPI4 TX1.
*/
static const edma_channel_config_t spi_dspi4_tx1_dma_config = {
SPC5_DSPI4_TX1_DMA_CH_ID,
SPC5_SPI_DSPI4_TX1_DMA_CH_ID,
#if SPC5_EDMA_HAS_MUX
SPC5_DSPI4_TX1_DMA_DEV_ID,
#endif
@ -258,7 +258,7 @@ static const edma_channel_config_t spi_dspi4_tx1_dma_config = {
* @brief DMA configuration for DSPI4 TX2.
*/
static const edma_channel_config_t spi_dspi4_tx2_dma_config = {
SPC5_DSPI4_TX2_DMA_CH_ID,
SPC5_SPI_DSPI4_TX2_DMA_CH_ID,
#if SPC5_EDMA_HAS_MUX
0,
#endif
@ -270,7 +270,7 @@ static const edma_channel_config_t spi_dspi4_tx2_dma_config = {
* @brief DMA configuration for DSPI4 RX.
*/
static const edma_channel_config_t spi_dspi4_rx_dma_config = {
SPC5_DSPI4_RX_DMA_CH_ID,
SPC5_SPI_DSPI4_RX_DMA_CH_ID,
#if SPC5_EDMA_HAS_MUX
SPC5_DSPI4_RX_DMA_DEV_ID,
#endif

30
os/hal/platforms/SPC5xx/DSPI_v1/spi_lld.h
View File

@ -369,6 +369,36 @@
#error "SPI driver activated but no DSPI peripheral assigned"
#endif
#if SPC5_SPI_USE_DSPI0 && (!defined(SPC5_SPI_DSPI0_TX1_DMA_CH_ID) || \
!defined(SPC5_SPI_DSPI0_TX2_DMA_CH_ID) || \
!defined(SPC5_SPI_DSPI0_RX_DMA_CH_ID))
#error "DMA channels not defined for DSPI0, check mcuconf.h"
#endif
#if SPC5_SPI_USE_DSPI1 && (!defined(SPC5_SPI_DSPI1_TX1_DMA_CH_ID) || \
!defined(SPC5_SPI_DSPI1_TX2_DMA_CH_ID) || \
!defined(SPC5_SPI_DSPI1_RX_DMA_CH_ID))
#error "DMA channels not defined for DSPI1, check mcuconf.h"
#endif
#if SPC5_SPI_USE_DSPI2 && (!defined(SPC5_SPI_DSPI2_TX1_DMA_CH_ID) || \
!defined(SPC5_SPI_DSPI2_TX2_DMA_CH_ID) || \
!defined(SPC5_SPI_DSPI2_RX_DMA_CH_ID))
#error "DMA channels not defined for DSPI2, check mcuconf.h"
#endif
#if SPC5_SPI_USE_DSPI3 && (!defined(SPC5_SPI_DSPI3_TX1_DMA_CH_ID) || \
!defined(SPC5_SPI_DSPI3_TX2_DMA_CH_ID) || \
!defined(SPC5_SPI_DSPI3_RX_DMA_CH_ID))
#error "DMA channels not defined for DSPI3, check mcuconf.h"
#endif
#if SPC5_SPI_USE_DSPI4 && (!defined(SPC5_SPI_DSPI4_TX1_DMA_CH_ID) || \
!defined(SPC5_SPI_DSPI4_TX2_DMA_CH_ID) || \
!defined(SPC5_SPI_DSPI4_RX_DMA_CH_ID))
#error "DMA channels not defined for DSPI4, check mcuconf.h"
#endif
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/

6
testhal/SPC560Dxx/SPI/mcuconf.h
View File

@ -215,6 +215,12 @@
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID 4
#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID 5
#define SPC5_SPI_DSPI0_RX_DMA_CH_ID 6
#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 7
#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 8
#define SPC5_SPI_DSPI1_RX_DMA_CH_ID 9
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI0_IRQ_PRIO 10

15
testhal/SPC560Pxx/PWM-ICU/mcuconf.h
View File

@ -265,6 +265,21 @@
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID 4
#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID 5
#define SPC5_SPI_DSPI0_RX_DMA_CH_ID 6
#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 7
#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 8
#define SPC5_SPI_DSPI1_RX_DMA_CH_ID 9
#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID 10
#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID 11
#define SPC5_SPI_DSPI2_RX_DMA_CH_ID 12
#define SPC5_SPI_DSPI3_TX1_DMA_CH_ID 13
#define SPC5_SPI_DSPI3_TX2_DMA_CH_ID 14
#define SPC5_SPI_DSPI3_RX_DMA_CH_ID 15
#define SPC5_SPI_DSPI4_TX1_DMA_CH_ID 1
#define SPC5_SPI_DSPI4_TX2_DMA_CH_ID 2
#define SPC5_SPI_DSPI4_RX_DMA_CH_ID 3
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10

15
testhal/SPC560Pxx/SPI/mcuconf.h
View File

@ -265,6 +265,21 @@
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID 4
#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID 5
#define SPC5_SPI_DSPI0_RX_DMA_CH_ID 6
#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 7
#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 8
#define SPC5_SPI_DSPI1_RX_DMA_CH_ID 9
#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID 10
#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID 11
#define SPC5_SPI_DSPI2_RX_DMA_CH_ID 12
#define SPC5_SPI_DSPI3_TX1_DMA_CH_ID 13
#define SPC5_SPI_DSPI3_TX2_DMA_CH_ID 14
#define SPC5_SPI_DSPI3_RX_DMA_CH_ID 15
#define SPC5_SPI_DSPI4_TX1_DMA_CH_ID 1
#define SPC5_SPI_DSPI4_TX2_DMA_CH_ID 2
#define SPC5_SPI_DSPI4_RX_DMA_CH_ID 3
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10

9
testhal/SPC56ELxx/PWM-ICU/mcuconf.h
View File

@ -259,6 +259,15 @@
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID 4
#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID 5
#define SPC5_SPI_DSPI0_RX_DMA_CH_ID 6
#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 7
#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 8
#define SPC5_SPI_DSPI1_RX_DMA_CH_ID 9
#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID 10
#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID 11
#define SPC5_SPI_DSPI2_RX_DMA_CH_ID 12
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10

9
testhal/SPC56ELxx/SPI/mcuconf.h
View File

@ -259,6 +259,15 @@
SPC5_MCR_PCSIS5 | \
SPC5_MCR_PCSIS6 | \
SPC5_MCR_PCSIS7)
#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID 4
#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID 5
#define SPC5_SPI_DSPI0_RX_DMA_CH_ID 6
#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 7
#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 8
#define SPC5_SPI_DSPI1_RX_DMA_CH_ID 9
#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID 10
#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID 11
#define SPC5_SPI_DSPI2_RX_DMA_CH_ID 12
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10