STM32 serial driver improvements.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1051 35acf78f-673a-0410-8e92-d51de3d6d3f4master
gdisirio
parent
255aea8bd2
commit
1a4bff432f
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@ -63,13 +63,13 @@ static uint8_t ob3[SERIAL_BUFFERS_SIZE];
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static void SetError(uint16_t sr, FullDuplexDriver *com) {
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dflags_t sts = 0;
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if (sr & SR_ORE)
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if (sr & USART_SR_ORE)
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sts |= SD_OVERRUN_ERROR;
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if (sr & SR_PE)
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if (sr & USART_SR_PE)
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sts |= SD_PARITY_ERROR;
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if (sr & SR_FE)
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if (sr & USART_SR_FE)
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sts |= SD_FRAMING_ERROR;
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if (sr & SR_LBD)
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if (sr & USART_SR_LBD)
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sts |= SD_BREAK_DETECTED;
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chSysLockFromIsr();
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chFDDAddFlagsI(com, sts);
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@ -84,19 +84,19 @@ static void SetError(uint16_t sr, FullDuplexDriver *com) {
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static void ServeInterrupt(USART_TypeDef *u, FullDuplexDriver *com) {
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uint16_t sr = u->SR;
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if (sr & (SR_ORE | SR_FE | SR_PE | SR_LBD))
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if (sr & (USART_SR_ORE | USART_SR_FE | USART_SR_PE | USART_SR_LBD))
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SetError(sr, com);
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if (sr & SR_RXNE) {
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if (sr & USART_SR_RXNE) {
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chSysLockFromIsr();
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chFDDIncomingDataI(com, u->DR);
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chSysUnlockFromIsr();
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}
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if (sr & SR_TXE) {
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if (sr & USART_SR_TXE) {
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chSysLockFromIsr();
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msg_t b = chFDDRequestDataI(com);
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chSysUnlockFromIsr();
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if (b < Q_OK)
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u->CR1 &= ~CR1_TXEIE;
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u->CR1 &= ~USART_CR1_TXEIE;
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else
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u->DR = b;
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}
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@ -130,7 +130,7 @@ CH_IRQ_HANDLER(VectorD8) {
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static void OutNotify2(void) {
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USART2->CR1 |= CR1_TXEIE;
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USART2->CR1 |= USART_CR1_TXEIE;
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}
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#endif
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@ -175,9 +175,10 @@ void usart_setup(USART_TypeDef *u, uint32_t speed, uint16_t cr1,
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/*
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* Note that some bits are enforced.
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*/
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u->CR1 = cr1 | CR1_UE | CR1_PEIE | CR1_RXNEIE | CR1_TE | CR1_RE;
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u->CR1 = cr1 | USART_CR1_UE | USART_CR1_PEIE | USART_CR1_RXNEIE |
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USART_CR1_TE | USART_CR1_RE;
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u->CR2 = cr2;
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u->CR3 = cr3 | CR3_EIE;
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u->CR3 = cr3 | USART_CR3_EIE;
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}
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/**
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@ -193,27 +194,27 @@ void serial_init(uint32_t prio1, uint32_t prio2, uint32_t prio3) {
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#if USE_STM32_USART1
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chFDDInit(&COM1, ib1, sizeof ib1, NULL, ob1, sizeof ob1, OutNotify1);
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RCC->APB2ENR |= 0x00004000;
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RCC->APB2ENR |= RCC_APB2ENR_USART1EN;
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usart_setup(USART1, DEFAULT_USART_BITRATE, 0,
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CR2_STOP1_BITS | CR2_LINEN, 0);
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USART_CR2_STOP1_BITS | USART_CR2_LINEN, 0);
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GPIOA->CRH = (GPIOA->CRH & 0xFFFFF00F) | 0x000004B0;
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NVICEnableVector(USART1_IRQChannel, prio1);
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#endif
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#if USE_STM32_USART2
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chFDDInit(&COM2, ib2, sizeof ib2, NULL, ob2, sizeof ob2, OutNotify2);
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RCC->APB1ENR |= 0x00020000;
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RCC->APB1ENR |= RCC_APB1ENR_USART2EN;
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usart_setup(USART2, DEFAULT_USART_BITRATE, 0,
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CR2_STOP1_BITS | CR2_LINEN, 0);
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USART_CR2_STOP1_BITS | USART_CR2_LINEN, 0);
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GPIOA->CRL = (GPIOA->CRL & 0xFFFF00FF) | 0x00004B00;
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NVICEnableVector(USART2_IRQChannel, prio2);
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#endif
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#if USE_STM32_USART3
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chFDDInit(&COM3, ib3, sizeof ib3, NULL, ob3, sizeof ob3, OutNotify3);
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RCC->APB1ENR |= 0x00040000;
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RCC->APB1ENR |= RCC_APB1ENR_USART3EN;
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usart_setup(USART3, DEFAULT_USART_BITRATE, 0,
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CR2_STOP1_BITS | CR2_LINEN, 0);
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USART_CR2_STOP1_BITS | USART_CR2_LINEN, 0);
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GPIOB->CRH = (GPIOB->CRH & 0xFFFF00FF) | 0x00004B00;
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NVICEnableVector(USART3_IRQChannel, prio3);
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#endif
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@ -27,6 +27,18 @@
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#ifndef _STM32_SERIAL_H_
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#define _STM32_SERIAL_H_
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/*
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* Tricks required to make the TRUE/FALSE declaration inside the library
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* compatible.
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*/
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#ifndef __STM32F10x_MAP_H
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#undef FALSE
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#undef TRUE
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#include "stm32f10x_map.h"
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#define FALSE 0
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#define TRUE (!FALSE)
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#endif
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/**
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* @brief Serial buffers size.
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* @details Configuration parameter, you can change the depth of the queue
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@ -76,59 +88,12 @@
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#endif
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/*
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* USARTs definitions here.
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* Extra USARTs definitions here (missing from the ST header file).
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*/
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#define SR_PE (1 << 0) /**< @brief SR PE bit.*/
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#define SR_FE (1 << 1) /**< @brief SR FE bit.*/
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#define SR_NE (1 << 2) /**< @brief SR NE bit.*/
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#define SR_ORE (1 << 3) /**< @brief SR ORE bit.*/
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#define SR_IDLE (1 << 4) /**< @brief SR IDLE bit.*/
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#define SR_RXNE (1 << 5) /**< @brief SR RXNE bit.*/
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#define SR_TC (1 << 6) /**< @brief SR TC bit.*/
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#define SR_TXE (1 << 7) /**< @brief SR TXE bit.*/
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#define SR_LBD (1 << 8) /**< @brief SR LBD bit.*/
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#define SR_CTS (1 << 9) /**< @brief SR CTS bit.*/
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#define CR1_SBK (1 << 0) /**< @brief CR1 SBK bit.*/
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#define CR1_RWU (1 << 1) /**< @brief CR1 RWU bit.*/
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#define CR1_RE (1 << 2) /**< @brief CR1 RE bit.*/
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#define CR1_TE (1 << 3) /**< @brief CR1 TE bit.*/
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#define CR1_IDLEIE (1 << 4) /**< @brief CR1 IDLEIE bit.*/
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#define CR1_RXNEIE (1 << 5) /**< @brief CR1 RXNEIE bit.*/
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#define CR1_TCIE (1 << 6) /**< @brief CR1 TCTE bit.*/
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#define CR1_TXEIE (1 << 7) /**< @brief CR1 TXEIE bit.*/
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#define CR1_PEIE (1 << 8) /**< @brief CR1 PEIE bit.*/
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#define CR1_PS (1 << 9) /**< @brief CR1 PS bit.*/
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#define CR1_PCE (1 << 10) /**< @brief CR1 PCE bit.*/
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#define CR1_WAKE (1 << 11) /**< @brief CR1 WAKE bit.*/
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#define CR1_M (1 << 12) /**< @brief CR1 M bit.*/
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#define CR1_UE (1 << 13) /**< @brief CR1 UE bit.*/
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#define CR2_ADD_MASK (15 << 0) /**< @brief CR2 ADD field mask.*/
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#define CR2_LBDL (1 << 5) /**< @brief CR2 LBDL bit.*/
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#define CR2_LBDIE (1 << 6) /**< @brief CR2 LBDIE bit.*/
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#define CR2_CBCL (1 << 8) /**< @brief CR2 CBCL bit.*/
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#define CR2_CPHA (1 << 9) /**< @brief CR2 CPHA bit.*/
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#define CR2_CPOL (1 << 10) /**< @brief CR2 CPOL bit.*/
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#define CR2_CLKEN (1 << 11) /**< @brief CR2 CLKEN bit.*/
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#define CR2_STOP_MASK (3 << 12) /**< @brief CR2 STOP field mask.*/
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#define CR2_STOP1_BITS (0 << 12) /**< @brief CR2 1 stop bit value.*/
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#define CR2_STOP0P5_BITS (1 << 12) /**< @brief CR2 0.5 stop bit value.*/
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#define CR2_STOP2_BITS (2 << 12) /**< @brief CR2 2 stop bit value.*/
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#define CR2_STOP1P5_BITS (3 << 12) /**< @brief CR2 1.5 stop bit value.*/
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#define CR2_LINEN (1 << 14) /**< @brief CR2 LINEN bit.*/
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#define CR3_EIE (1 << 0) /**< @brief CR3 EIE bit.*/
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#define CR3_IREN (1 << 1) /**< @brief CR3 IREN bit.*/
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#define CR3_IRLP (1 << 2) /**< @brief CR3 IRLP bit.*/
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#define CR3_HDSEL (1 << 3) /**< @brief CR3 HDSEL bit.*/
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#define CR3_NACK (1 << 4) /**< @brief CR3 NACK bit.*/
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#define CR3_SCEN (1 << 5) /**< @brief CR3 SCEN bit.*/
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#define CR3_DMAR (1 << 6) /**< @brief CR3 DMAR bit.*/
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#define CR3_DMAT (1 << 7) /**< @brief CR3 DMAT bit.*/
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#define CR3_RTSE (1 << 8) /**< @brief CR3 RTSE bit.*/
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#define CR3_CTSE (1 << 9) /**< @brief CR3 CTSE bit.*/
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#define CR3_CTSIE (1 << 10) /**< @brief CR3 CTSIE bit.*/
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#define USART_CR2_STOP1_BITS (0 << 12) /**< @brief CR2 1 stop bit value.*/
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#define USART_CR2_STOP0P5_BITS (1 << 12) /**< @brief CR2 0.5 stop bit value.*/
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#define USART_CR2_STOP2_BITS (2 << 12) /**< @brief CR2 2 stop bit value.*/
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#define USART_CR2_STOP1P5_BITS (3 << 12) /**< @brief CR2 1.5 stop bit value.*/
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/** @cond never*/
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#if USE_STM32_USART1
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@ -75,7 +75,7 @@ GNU-Linux-GCC - ChibiOS/RT simulator for x86 Linux systems, it is
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not supported because its "sparse" registers layout, it would not be
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efficient enough for my taste.
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- Modified the STM32 demo to use the bit definitions in the ST header file,
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removed the bit definitions in board.h.
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removed the bit definitions in board.h and stm32_serial.h.
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- Documentation section reorganization and fixes.
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- Changed the STM32 demo stack sizes, it was incorrectly adjusted in version
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1.3.0 but it did not create problems (not a bug).
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