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Fixed bug 3598720. 

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4982 35acf78f-673a-0410-8e92-d51de3d6d3f4
master
gdisirio 2012-12-28 10:41:04 +00:00
parent d38b79b7b2
commit 17d265e3ba
22 changed files with 242 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
demos/ARMCM4-STM32F407-DISCOVERY-MEMS/mcuconf.h
View File

@ -163,6 +163,17 @@
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/* /*
* PWM driver system settings. * PWM driver system settings.
*/ */

11
demos/ARMCM4-STM32F407-DISCOVERY/mcuconf.h
View File

@ -163,6 +163,17 @@
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/* /*
* PWM driver system settings. * PWM driver system settings.
*/ */

22
demos/ARMCM4-STM32F407-LWIP-FATFS-USB/mcuconf.h
View File

@ -163,6 +163,28 @@
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/* /*
* PWM driver system settings. * PWM driver system settings.
*/ */

11
demos/ARMCM4-STM32F407-LWIP/mcuconf.h
View File

@ -163,6 +163,17 @@
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/* /*
* PWM driver system settings. * PWM driver system settings.
*/ */

19
os/hal/platforms/STM32/mac_lld.c
View File

@ -272,7 +272,7 @@ void mac_lld_init(void) {
; ;
#endif #endif
#if STM32_ETH1_CHANGE_PHY_STATE #if STM32_MAC_ETH1_CHANGE_PHY_STATE
/* PHY in power down mode until the driver will be started.*/ /* PHY in power down mode until the driver will be started.*/
mii_write(&ETHD1, MII_BMCR, mii_read(&ETHD1, MII_BMCR) | BMCR_PDOWN); mii_write(&ETHD1, MII_BMCR, mii_read(&ETHD1, MII_BMCR) | BMCR_PDOWN);
#endif #endif
@ -306,9 +306,10 @@ void mac_lld_start(MACDriver *macp) {
; ;
/* ISR vector enabled.*/ /* ISR vector enabled.*/
nvicEnableVector(ETH_IRQn, CORTEX_PRIORITY_MASK(STM32_ETH1_IRQ_PRIORITY)); nvicEnableVector(ETH_IRQn,
CORTEX_PRIORITY_MASK(STM32_MAC_ETH1_IRQ_PRIORITY));
#if STM32_ETH1_CHANGE_PHY_STATE #if STM32_MAC_ETH1_CHANGE_PHY_STATE
/* PHY in power up mode.*/ /* PHY in power up mode.*/
mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN); mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN);
#endif #endif
@ -327,7 +328,7 @@ void mac_lld_start(MACDriver *macp) {
/* Transmitter and receiver enabled. /* Transmitter and receiver enabled.
Note that the complete setup of the MAC is performed when the link Note that the complete setup of the MAC is performed when the link
status is detected.*/ status is detected.*/
#if STM32_IP_CHECKSUM_OFFLOAD #if STM32_MAC_IP_CHECKSUM_OFFLOAD
ETH->MACCR = ETH_MACCR_IPCO | ETH_MACCR_RE | ETH_MACCR_TE; ETH->MACCR = ETH_MACCR_IPCO | ETH_MACCR_RE | ETH_MACCR_TE;
#else #else
ETH->MACCR = ETH_MACCR_RE | ETH_MACCR_TE; ETH->MACCR = ETH_MACCR_RE | ETH_MACCR_TE;
@ -365,7 +366,7 @@ void mac_lld_start(MACDriver *macp) {
void mac_lld_stop(MACDriver *macp) { void mac_lld_stop(MACDriver *macp) {
if (macp->state != MAC_STOP) { if (macp->state != MAC_STOP) {
#if STM32_ETH1_CHANGE_PHY_STATE #if STM32_MAC_ETH1_CHANGE_PHY_STATE
/* PHY in power down mode until the driver will be restarted.*/ /* PHY in power down mode until the driver will be restarted.*/
mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN); mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN);
#endif #endif
@ -482,7 +483,7 @@ void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) {
/* Unlocks the descriptor and returns it to the DMA engine.*/ /* Unlocks the descriptor and returns it to the DMA engine.*/
tdp->physdesc->tdes1 = tdp->offset; tdp->physdesc->tdes1 = tdp->offset;
tdp->physdesc->tdes0 = STM32_TDES0_CIC(STM32_IP_CHECKSUM_OFFLOAD) | tdp->physdesc->tdes0 = STM32_TDES0_CIC(STM32_MAC_IP_CHECKSUM_OFFLOAD) |
STM32_TDES0_IC | STM32_TDES0_LS | STM32_TDES0_FS | STM32_TDES0_IC | STM32_TDES0_LS | STM32_TDES0_FS |
STM32_TDES0_TCH | STM32_TDES0_OWN; STM32_TDES0_TCH | STM32_TDES0_OWN;
@ -519,9 +520,9 @@ msg_t mac_lld_get_receive_descriptor(MACDriver *macp,
frames are discarded.*/ frames are discarded.*/
while (!(rdes->rdes0 & STM32_RDES0_OWN)) { while (!(rdes->rdes0 & STM32_RDES0_OWN)) {
if (!(rdes->rdes0 & (STM32_RDES0_AFM | STM32_RDES0_ES)) if (!(rdes->rdes0 & (STM32_RDES0_AFM | STM32_RDES0_ES))
#if STM32_IP_CHECKSUM_OFFLOAD #if STM32_MAC_IP_CHECKSUM_OFFLOAD
&& !(rdes->rdes0 & STM32_RDES0_FT & (STM32_RDES0_IPHCE | && (rdes->rdes0 & STM32_RDES0_FT)
STM32_RDES0_PCE)) && !(rdes->rdes0 & (STM32_RDES0_IPHCE | STM32_RDES0_PCE))
#endif #endif
&& (rdes->rdes0 & STM32_RDES0_FS) && (rdes->rdes0 & STM32_RDES0_LS)) { && (rdes->rdes0 & STM32_RDES0_FS) && (rdes->rdes0 & STM32_RDES0_LS)) {
/* Found a valid one.*/ /* Found a valid one.*/

20
os/hal/platforms/STM32/mac_lld.h
View File

@ -124,21 +124,21 @@
* @brief Number of available transmit buffers. * @brief Number of available transmit buffers.
*/ */
#if !defined(STM32_MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__) #if !defined(STM32_MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__)
#define STM32_MAC_TRANSMIT_BUFFERS 2 #define STM32_MAC_TRANSMIT_BUFFERS 2
#endif #endif
/** /**
* @brief Number of available receive buffers. * @brief Number of available receive buffers.
*/ */
#if !defined(STM32_MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__) #if !defined(STM32_MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__)
#define STM32_MAC_RECEIVE_BUFFERS 4 #define STM32_MAC_RECEIVE_BUFFERS 4
#endif #endif
/** /**
* @brief Maximum supported frame size. * @brief Maximum supported frame size.
*/ */
#if !defined(STM32_MAC_BUFFERS_SIZE) || defined(__DOXYGEN__) #if !defined(STM32_MAC_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define STM32_MAC_BUFFERS_SIZE 1522 #define STM32_MAC_BUFFERS_SIZE 1522
#endif #endif
/** /**
@ -151,21 +151,21 @@
* single search path is performed. * single search path is performed.
*/ */
#if !defined(STM32_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__) #if !defined(STM32_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__)
#define STM32_MAC_PHY_TIMEOUT 100 #define STM32_MAC_PHY_TIMEOUT 100
#endif #endif
/** /**
* @brief Change the PHY power state inside the driver. * @brief Change the PHY power state inside the driver.
*/ */
#if !defined(STM32_ETH1_CHANGE_PHY_STATE) || defined(__DOXYGEN__) #if !defined(STM32_MAC_ETH1_CHANGE_PHY_STATE) || defined(__DOXYGEN__)
#define STM32_ETH1_CHANGE_PHY_STATE TRUE #define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#endif #endif
/** /**
* @brief ETHD1 interrupt priority level setting. * @brief ETHD1 interrupt priority level setting.
*/ */
#if !defined(STM32_ETH1_IRQ_PRIORITY) || defined(__DOXYGEN__) #if !defined(STM32_MAC_ETH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ETH1_IRQ_PRIORITY 13 #define STM32_MAC_ETH1_IRQ_PRIORITY 13
#endif #endif
/** /**
@ -181,8 +181,8 @@
* calculated in hardware. * calculated in hardware.
* . * .
*/ */
#if !defined(STM32_IP_CHECKSUM_OFFLOAD) || defined(__DOXYGEN__) #if !defined(STM32_MAC_IP_CHECKSUM_OFFLOAD) || defined(__DOXYGEN__)
#define STM32_IP_CHECKSUM_OFFLOAD 0 #define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
#endif #endif
/** @} */ /** @} */

2
readme.txt
View File

@ -82,6 +82,8 @@
***************************************************************************** *****************************************************************************
*** 2.5.2 *** *** 2.5.2 ***
- FIX: Fixed wrong condition in checksum offload of STM32 MAC driver (bug
3598720)(backported to 2.4.4).
- FIX: Fixed error in STM32 MAC driver degrades performance (bug 3598719) - FIX: Fixed error in STM32 MAC driver degrades performance (bug 3598719)
(backported to 2.4.4). (backported to 2.4.4).
- FIX: Fixed warning in STM32 ICU driver using IAR compiler (bug 3598177) - FIX: Fixed warning in STM32 ICU driver using IAR compiler (bug 3598177)

11
testhal/STM32F4xx/ADC/mcuconf.h
View File

@ -163,6 +163,17 @@
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/* /*
* PWM driver system settings. * PWM driver system settings.
*/ */

11
testhal/STM32F4xx/CAN/mcuconf.h
View File

@ -163,6 +163,17 @@
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/* /*
* PWM driver system settings. * PWM driver system settings.
*/ */

11
testhal/STM32F4xx/DMA_STORM/mcuconf.h
View File

@ -163,6 +163,17 @@
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/* /*
* PWM driver system settings. * PWM driver system settings.
*/ */

11
testhal/STM32F4xx/EXT/mcuconf.h
View File

@ -163,6 +163,17 @@
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/* /*
* PWM driver system settings. * PWM driver system settings.
*/ */

11
testhal/STM32F4xx/GPT/mcuconf.h
View File

@ -163,6 +163,17 @@
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/* /*
* PWM driver system settings. * PWM driver system settings.
*/ */

11
testhal/STM32F4xx/I2C/mcuconf.h
View File

@ -163,6 +163,17 @@
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/* /*
* PWM driver system settings. * PWM driver system settings.
*/ */

11
testhal/STM32F4xx/IRQ_STORM/mcuconf.h
View File

@ -163,6 +163,17 @@
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/* /*
* PWM driver system settings. * PWM driver system settings.
*/ */

11
testhal/STM32F4xx/IRQ_STORM_FPU/mcuconf.h
View File

@ -163,6 +163,17 @@
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/* /*
* PWM driver system settings. * PWM driver system settings.
*/ */

11
testhal/STM32F4xx/PWM-ICU/mcuconf.h
View File

@ -163,6 +163,17 @@
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/* /*
* PWM driver system settings. * PWM driver system settings.
*/ */

11
testhal/STM32F4xx/RTC/mcuconf.h
View File

@ -163,6 +163,17 @@
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/* /*
* PWM driver system settings. * PWM driver system settings.
*/ */

11
testhal/STM32F4xx/RTC_FATTIME/mcuconf.h
View File

@ -163,6 +163,17 @@
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/* /*
* PWM driver system settings. * PWM driver system settings.
*/ */

11
testhal/STM32F4xx/SDC/mcuconf.h
View File

@ -163,6 +163,17 @@
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/* /*
* PWM driver system settings. * PWM driver system settings.
*/ */

11
testhal/STM32F4xx/SPI/mcuconf.h
View File

@ -163,6 +163,17 @@
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/* /*
* PWM driver system settings. * PWM driver system settings.
*/ */

11
testhal/STM32F4xx/UART/mcuconf.h
View File

@ -163,6 +163,17 @@
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/* /*
* PWM driver system settings. * PWM driver system settings.
*/ */

11
testhal/STM32F4xx/USB_CDC/mcuconf.h
View File

@ -163,6 +163,17 @@
#define STM32_ICU_TIM5_IRQ_PRIORITY 7 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/* /*
* PWM driver system settings. * PWM driver system settings.
*/ */