diff --git a/os/hal/platforms/STM32/serial_lld.c b/os/hal/platforms/STM32/USARTv1/serial_lld.c
similarity index 76%
rename from os/hal/platforms/STM32/serial_lld.c
rename to os/hal/platforms/STM32/USARTv1/serial_lld.c
index 92ef8c5ef..1f069b34a 100644
--- a/os/hal/platforms/STM32/serial_lld.c
+++ b/os/hal/platforms/STM32/USARTv1/serial_lld.c
@@ -82,125 +82,6 @@ static const SerialConfig default_config =
 /* Driver local functions.                                                   */
 /*===========================================================================*/
 
-/* Local functions have different implementations depending on the USART type,
-   STM32F0xx devices and newer have an enhanced peripheral with slightly
-   different register interface.*/
-
-#if defined(STM32F0XX)
-
-/**
- * @brief   USART initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] config    the architecture-dependent serial driver configuration
- */
-static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
-  USART_TypeDef *u = sdp->usart;
-
-  /* Baud rate setting.*/
-  if (sdp->usart == USART1)
-    u->BRR = STM32_USART1CLK / config->sc_speed;
-  else
-    u->BRR = STM32_PCLK / config->sc_speed;
-
-  /* Note that some bits are enforced.*/
-  u->CR1 = config->sc_cr1 | USART_CR1_UE | USART_CR1_PEIE |
-                            USART_CR1_RXNEIE | USART_CR1_TE |
-                            USART_CR1_RE;
-  u->CR2 = config->sc_cr2 | USART_CR2_LBDIE;
-  u->CR3 = config->sc_cr3 | USART_CR3_EIE;
-  u->ICR = 0xFFFFFFFF;
-}
-
-/**
- * @brief   USART de-initialization.
- * @details This function must be invoked with interrupts disabled.
- *
- * @param[in] u         pointer to an USART I/O block
- */
-static void usart_deinit(USART_TypeDef *u) {
-
-  u->CR1 = 0;
-  u->CR2 = 0;
-  u->CR3 = 0;
-}
-
-/**
- * @brief   Error handling routine.
- *
- * @param[in] sdp       pointer to a @p SerialDriver object
- * @param[in] isr       USART ISR register value
- */
-static void set_error(SerialDriver *sdp, uint16_t isr) {
-  flagsmask_t sts = 0;
-
-  if (isr & USART_ISR_ORE)
-    sts |= SD_OVERRUN_ERROR;
-  if (isr & USART_ISR_PE)
-    sts |= SD_PARITY_ERROR;
-  if (isr & USART_ISR_FE)
-    sts |= SD_FRAMING_ERROR;
-  if (isr & USART_ISR_NE)
-    sts |= SD_NOISE_ERROR;
-  chSysLockFromIsr();
-  chnAddFlagsI(sdp, sts);
-  chSysUnlockFromIsr();
-}
-
-/**
- * @brief   Common IRQ handler.
- *
- * @param[in] sdp       communication channel associated to the USART
- */
-static void serve_interrupt(SerialDriver *sdp) {
-  USART_TypeDef *u = sdp->usart;
-  uint16_t cr1 = u->CR1;
-  uint16_t isr;
-
-  /* Reading and clearing status.*/
-  isr = u->ISR;
-  u->ICR = isr;
-
-  /* Error condition detection.*/
-  if (isr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE  | USART_ISR_PE))
-    set_error(sdp, isr);
-  /* Special case, LIN break detection.*/
-  if (isr & USART_ISR_LBD) {
-    chSysLockFromIsr();
-    chnAddFlagsI(sdp, SD_BREAK_DETECTED);
-    chSysUnlockFromIsr();
-  }
-  /* Data available.*/
-  if (isr & USART_ISR_RXNE) {
-    chSysLockFromIsr();
-    sdIncomingDataI(sdp, (uint8_t)u->RDR);
-    chSysUnlockFromIsr();
-  }
-  /* Transmission buffer empty.*/
-  if ((cr1 & USART_CR1_TXEIE) && (isr & USART_ISR_TXE)) {
-    msg_t b;
-    chSysLockFromIsr();
-    b = chOQGetI(&sdp->oqueue);
-    if (b < Q_OK) {
-      chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
-      u->CR1 = (cr1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE;
-    }
-    else
-      u->TDR = b;
-    chSysUnlockFromIsr();
-  }
-  /* Physical transmission end.*/
-  if (isr & USART_ISR_TC) {
-    chSysLockFromIsr();
-    chnAddFlagsI(sdp, CHN_TRANSMISSION_END);
-    chSysUnlockFromIsr();
-    u->CR1 = cr1 & ~USART_CR1_TCIE;
-  }
-}
-
-#else /* !defined(STM32F0XX) */
-
 /**
  * @brief   USART initialization.
  * @details This function must be invoked with interrupts disabled.
@@ -317,8 +198,6 @@ static void serve_interrupt(SerialDriver *sdp) {
   }
 }
 
-#endif /* !defined(STM32F0XX) */
-
 #if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
 static void notify1(GenericQueue *qp) {
 
diff --git a/os/hal/platforms/STM32/serial_lld.h b/os/hal/platforms/STM32/USARTv1/serial_lld.h
similarity index 100%
rename from os/hal/platforms/STM32/serial_lld.h
rename to os/hal/platforms/STM32/USARTv1/serial_lld.h
diff --git a/os/hal/platforms/STM32/USARTv2/serial_lld.c b/os/hal/platforms/STM32/USARTv2/serial_lld.c
new file mode 100644
index 000000000..b48996f45
--- /dev/null
+++ b/os/hal/platforms/STM32/USARTv2/serial_lld.c
@@ -0,0 +1,526 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32/serial_lld.c
+ * @brief   STM32 low level serial driver code.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief USART1 serial driver identifier.*/
+#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
+SerialDriver SD1;
+#endif
+
+/** @brief USART2 serial driver identifier.*/
+#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
+SerialDriver SD2;
+#endif
+
+/** @brief USART3 serial driver identifier.*/
+#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
+SerialDriver SD3;
+#endif
+
+/** @brief UART4 serial driver identifier.*/
+#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+SerialDriver SD4;
+#endif
+
+/** @brief UART5 serial driver identifier.*/
+#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+SerialDriver SD5;
+#endif
+
+/** @brief USART6 serial driver identifier.*/
+#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
+SerialDriver SD6;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+/** @brief Driver default configuration.*/
+static const SerialConfig default_config =
+{
+  SERIAL_DEFAULT_BITRATE,
+  0,
+  USART_CR2_STOP1_BITS | USART_CR2_LINEN,
+  0
+};
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   USART initialization.
+ * @details This function must be invoked with interrupts disabled.
+ *
+ * @param[in] sdp       pointer to a @p SerialDriver object
+ * @param[in] config    the architecture-dependent serial driver configuration
+ */
+static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
+  USART_TypeDef *u = sdp->usart;
+
+  /* Baud rate setting.*/
+  if (sdp->usart == USART1)
+    u->BRR = STM32_USART1CLK / config->sc_speed;
+  else
+    u->BRR = STM32_PCLK / config->sc_speed;
+
+  /* Note that some bits are enforced.*/
+  u->CR2 = config->sc_cr2 | USART_CR2_LBDIE;
+  u->CR3 = config->sc_cr3 | USART_CR3_EIE;
+  u->CR1 = config->sc_cr1 | USART_CR1_UE | USART_CR1_PEIE |
+                            USART_CR1_RXNEIE | USART_CR1_TE |
+                            USART_CR1_RE;
+  u->ICR = 0xFFFFFFFF;
+}
+
+/**
+ * @brief   USART de-initialization.
+ * @details This function must be invoked with interrupts disabled.
+ *
+ * @param[in] u         pointer to an USART I/O block
+ */
+static void usart_deinit(USART_TypeDef *u) {
+
+  u->CR1 = 0;
+  u->CR2 = 0;
+  u->CR3 = 0;
+}
+
+/**
+ * @brief   Error handling routine.
+ *
+ * @param[in] sdp       pointer to a @p SerialDriver object
+ * @param[in] isr       USART ISR register value
+ */
+static void set_error(SerialDriver *sdp, uint32_t isr) {
+  flagsmask_t sts = 0;
+
+  if (isr & USART_ISR_ORE)
+    sts |= SD_OVERRUN_ERROR;
+  if (isr & USART_ISR_PE)
+    sts |= SD_PARITY_ERROR;
+  if (isr & USART_ISR_FE)
+    sts |= SD_FRAMING_ERROR;
+  if (isr & USART_ISR_NE)
+    sts |= SD_NOISE_ERROR;
+  chSysLockFromIsr();
+  chnAddFlagsI(sdp, sts);
+  chSysUnlockFromIsr();
+}
+
+/**
+ * @brief   Common IRQ handler.
+ *
+ * @param[in] sdp       communication channel associated to the USART
+ */
+static void serve_interrupt(SerialDriver *sdp) {
+  USART_TypeDef *u = sdp->usart;
+  uint32_t cr1 = u->CR1;
+  uint32_t isr;
+
+  /* Reading and clearing status.*/
+  isr = u->ISR;
+  u->ICR = isr;
+
+  /* Error condition detection.*/
+  if (isr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE  | USART_ISR_PE))
+    set_error(sdp, isr);
+  /* Special case, LIN break detection.*/
+  if (isr & USART_ISR_LBD) {
+    chSysLockFromIsr();
+    chnAddFlagsI(sdp, SD_BREAK_DETECTED);
+    chSysUnlockFromIsr();
+  }
+  /* Data available.*/
+  if (isr & USART_ISR_RXNE) {
+    chSysLockFromIsr();
+    sdIncomingDataI(sdp, (uint8_t)u->RDR);
+    chSysUnlockFromIsr();
+  }
+  /* Transmission buffer empty.*/
+  if ((cr1 & USART_CR1_TXEIE) && (isr & USART_ISR_TXE)) {
+    msg_t b;
+    chSysLockFromIsr();
+    b = chOQGetI(&sdp->oqueue);
+    if (b < Q_OK) {
+      chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
+      u->CR1 = (cr1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE;
+    }
+    else
+      u->TDR = b;
+    chSysUnlockFromIsr();
+  }
+  /* Physical transmission end.*/
+  if (isr & USART_ISR_TC) {
+    chSysLockFromIsr();
+    chnAddFlagsI(sdp, CHN_TRANSMISSION_END);
+    chSysUnlockFromIsr();
+    u->CR1 = cr1 & ~USART_CR1_TCIE;
+  }
+}
+
+#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
+static void notify1(GenericQueue *qp) {
+
+  (void)qp;
+  USART1->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
+static void notify2(GenericQueue *qp) {
+
+  (void)qp;
+  USART2->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
+static void notify3(GenericQueue *qp) {
+
+  (void)qp;
+  USART3->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+static void notify4(GenericQueue *qp) {
+
+  (void)qp;
+  UART4->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+static void notify5(GenericQueue *qp) {
+
+  (void)qp;
+  UART5->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
+static void notify6(GenericQueue *qp) {
+
+  (void)qp;
+  USART6->CR1 |= USART_CR1_TXEIE;
+}
+#endif
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
+#if !defined(STM32_USART1_HANDLER)
+#error "STM32_USART1_HANDLER not defined"
+#endif
+/**
+ * @brief   USART1 interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(STM32_USART1_HANDLER) {
+
+  CH_IRQ_PROLOGUE();
+
+  serve_interrupt(&SD1);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
+#if !defined(STM32_USART2_HANDLER)
+#error "STM32_USART2_HANDLER not defined"
+#endif
+/**
+ * @brief   USART2 interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(STM32_USART2_HANDLER) {
+
+  CH_IRQ_PROLOGUE();
+
+  serve_interrupt(&SD2);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
+#if !defined(STM32_USART3_HANDLER)
+#error "STM32_USART3_HANDLER not defined"
+#endif
+/**
+ * @brief   USART3 interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(STM32_USART3_HANDLER) {
+
+  CH_IRQ_PROLOGUE();
+
+  serve_interrupt(&SD3);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+#if !defined(STM32_UART4_HANDLER)
+#error "STM32_UART4_HANDLER not defined"
+#endif
+/**
+ * @brief   UART4 interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(STM32_UART4_HANDLER) {
+
+  CH_IRQ_PROLOGUE();
+
+  serve_interrupt(&SD4);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+#if !defined(STM32_UART5_HANDLER)
+#error "STM32_UART5_HANDLER not defined"
+#endif
+/**
+ * @brief   UART5 interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(STM32_UART5_HANDLER) {
+
+  CH_IRQ_PROLOGUE();
+
+  serve_interrupt(&SD5);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif
+
+#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
+#if !defined(STM32_USART6_HANDLER)
+#error "STM32_USART6_HANDLER not defined"
+#endif
+/**
+ * @brief   USART1 interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(STM32_USART6_HANDLER) {
+
+  CH_IRQ_PROLOGUE();
+
+  serve_interrupt(&SD6);
+
+  CH_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level serial driver initialization.
+ *
+ * @notapi
+ */
+void sd_lld_init(void) {
+
+#if STM32_SERIAL_USE_USART1
+  sdObjectInit(&SD1, NULL, notify1);
+  SD1.usart = USART1;
+#endif
+
+#if STM32_SERIAL_USE_USART2
+  sdObjectInit(&SD2, NULL, notify2);
+  SD2.usart = USART2;
+#endif
+
+#if STM32_SERIAL_USE_USART3
+  sdObjectInit(&SD3, NULL, notify3);
+  SD3.usart = USART3;
+#endif
+
+#if STM32_SERIAL_USE_UART4
+  sdObjectInit(&SD4, NULL, notify4);
+  SD4.usart = UART4;
+#endif
+
+#if STM32_SERIAL_USE_UART5
+  sdObjectInit(&SD5, NULL, notify5);
+  SD5.usart = UART5;
+#endif
+
+#if STM32_SERIAL_USE_USART6
+  sdObjectInit(&SD6, NULL, notify6);
+  SD6.usart = USART6;
+#endif
+}
+
+/**
+ * @brief   Low level serial driver configuration and (re)start.
+ *
+ * @param[in] sdp       pointer to a @p SerialDriver object
+ * @param[in] config    the architecture-dependent serial driver configuration.
+ *                      If this parameter is set to @p NULL then a default
+ *                      configuration is used.
+ *
+ * @notapi
+ */
+void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
+
+  if (config == NULL)
+    config = &default_config;
+
+  if (sdp->state == SD_STOP) {
+#if STM32_SERIAL_USE_USART1
+    if (&SD1 == sdp) {
+      rccEnableUSART1(FALSE);
+      nvicEnableVector(STM32_USART1_NUMBER,
+                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART1_PRIORITY));
+    }
+#endif
+#if STM32_SERIAL_USE_USART2
+    if (&SD2 == sdp) {
+      rccEnableUSART2(FALSE);
+      nvicEnableVector(STM32_USART2_NUMBER,
+                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART2_PRIORITY));
+    }
+#endif
+#if STM32_SERIAL_USE_USART3
+    if (&SD3 == sdp) {
+      rccEnableUSART3(FALSE);
+      nvicEnableVector(STM32_USART3_NUMBER,
+                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART3_PRIORITY));
+    }
+#endif
+#if STM32_SERIAL_USE_UART4
+    if (&SD4 == sdp) {
+      rccEnableUART4(FALSE);
+      nvicEnableVector(STM32_UART4_NUMBER,
+                       CORTEX_PRIORITY_MASK(STM32_SERIAL_UART4_PRIORITY));
+    }
+#endif
+#if STM32_SERIAL_USE_UART5
+    if (&SD5 == sdp) {
+      rccEnableUART5(FALSE);
+      nvicEnableVector(STM32_UART5_NUMBER,
+                       CORTEX_PRIORITY_MASK(STM32_SERIAL_UART5_PRIORITY));
+    }
+#endif
+#if STM32_SERIAL_USE_USART6
+    if (&SD6 == sdp) {
+      rccEnableUSART6(FALSE);
+      nvicEnableVector(STM32_USART6_NUMBER,
+                       CORTEX_PRIORITY_MASK(STM32_SERIAL_USART6_PRIORITY));
+    }
+#endif
+  }
+  usart_init(sdp, config);
+}
+
+/**
+ * @brief   Low level serial driver stop.
+ * @details De-initializes the USART, stops the associated clock, resets the
+ *          interrupt vector.
+ *
+ * @param[in] sdp       pointer to a @p SerialDriver object
+ *
+ * @notapi
+ */
+void sd_lld_stop(SerialDriver *sdp) {
+
+  if (sdp->state == SD_READY) {
+    usart_deinit(sdp->usart);
+#if STM32_SERIAL_USE_USART1
+    if (&SD1 == sdp) {
+      rccDisableUSART1(FALSE);
+      nvicDisableVector(STM32_USART1_NUMBER);
+      return;
+    }
+#endif
+#if STM32_SERIAL_USE_USART2
+    if (&SD2 == sdp) {
+      rccDisableUSART2(FALSE);
+      nvicDisableVector(STM32_USART2_NUMBER);
+      return;
+    }
+#endif
+#if STM32_SERIAL_USE_USART3
+    if (&SD3 == sdp) {
+      rccDisableUSART3(FALSE);
+      nvicDisableVector(STM32_USART3_NUMBER);
+      return;
+    }
+#endif
+#if STM32_SERIAL_USE_UART4
+    if (&SD4 == sdp) {
+      rccDisableUART4(FALSE);
+      nvicDisableVector(STM32_UART4_NUMBER);
+      return;
+    }
+#endif
+#if STM32_SERIAL_USE_UART5
+    if (&SD5 == sdp) {
+      rccDisableUART5(FALSE);
+      nvicDisableVector(STM32_UART5_NUMBER);
+      return;
+    }
+#endif
+#if STM32_SERIAL_USE_USART6
+    if (&SD6 == sdp) {
+      rccDisableUSART6(FALSE);
+      nvicDisableVector(STM32_USART6_NUMBER);
+      return;
+    }
+#endif
+  }
+}
+
+#endif /* HAL_USE_SERIAL */
+
+/** @} */
diff --git a/os/hal/platforms/STM32/USARTv2/serial_lld.h b/os/hal/platforms/STM32/USARTv2/serial_lld.h
new file mode 100644
index 000000000..d98cb14bd
--- /dev/null
+++ b/os/hal/platforms/STM32/USARTv2/serial_lld.h
@@ -0,0 +1,306 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+                 2011,2012 Giovanni Di Sirio.
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32/serial_lld.h
+ * @brief   STM32 low level serial driver header.
+ *
+ * @addtogroup SERIAL
+ * @{
+ */
+
+#ifndef _SERIAL_LLD_H_
+#define _SERIAL_LLD_H_
+
+#if HAL_USE_SERIAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   USART1 driver enable switch.
+ * @details If set to @p TRUE the support for USART1 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_SERIAL_USE_USART1) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_USART1             FALSE
+#endif
+
+/**
+ * @brief   USART2 driver enable switch.
+ * @details If set to @p TRUE the support for USART2 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_SERIAL_USE_USART2) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_USART2             FALSE
+#endif
+
+/**
+ * @brief   USART3 driver enable switch.
+ * @details If set to @p TRUE the support for USART3 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_SERIAL_USE_USART3) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_USART3             FALSE
+#endif
+
+/**
+ * @brief   UART4 driver enable switch.
+ * @details If set to @p TRUE the support for UART4 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_SERIAL_USE_UART4) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_UART4              FALSE
+#endif
+
+/**
+ * @brief   UART5 driver enable switch.
+ * @details If set to @p TRUE the support for UART5 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_SERIAL_USE_UART5) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_UART5              FALSE
+#endif
+
+/**
+ * @brief   USART6 driver enable switch.
+ * @details If set to @p TRUE the support for USART6 is included.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(STM32_SERIAL_USE_USART6) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USE_USART6             FALSE
+#endif
+
+/**
+ * @brief   USART1 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_USART1_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART1_PRIORITY        12
+#endif
+
+/**
+ * @brief   USART2 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_USART2_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART2_PRIORITY        12
+#endif
+
+/**
+ * @brief   USART3 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_USART3_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART3_PRIORITY        12
+#endif
+
+/**
+ * @brief   UART4 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_UART4_PRIORITY         12
+#endif
+
+/**
+ * @brief   UART5 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_UART5_PRIORITY         12
+#endif
+
+/**
+ * @brief   USART6 interrupt priority level setting.
+ */
+#if !defined(STM32_SERIAL_USART6_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_SERIAL_USART6_PRIORITY        12
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_SERIAL_USE_USART1 && !STM32_HAS_USART1
+#error "USART1 not present in the selected device"
+#endif
+
+#if STM32_SERIAL_USE_USART2 && !STM32_HAS_USART2
+#error "USART2 not present in the selected device"
+#endif
+
+#if STM32_SERIAL_USE_USART3 && !STM32_HAS_USART3
+#error "USART3 not present in the selected device"
+#endif
+
+#if STM32_SERIAL_USE_UART4 && !STM32_HAS_UART4
+#error "UART4 not present in the selected device"
+#endif
+
+#if STM32_SERIAL_USE_UART5 && !STM32_HAS_UART5
+#error "UART5 not present in the selected device"
+#endif
+
+#if STM32_SERIAL_USE_USART6 && !STM32_HAS_USART6
+#error "USART6 not present in the selected device"
+#endif
+
+#if !STM32_SERIAL_USE_USART1 && !STM32_SERIAL_USE_USART2 &&                 \
+    !STM32_SERIAL_USE_USART3 && !STM32_SERIAL_USE_UART4  &&                 \
+    !STM32_SERIAL_USE_UART5  && !STM32_SERIAL_USE_USART6
+#error "SERIAL driver activated but no USART/UART peripheral assigned"
+#endif
+
+#if STM32_SERIAL_USE_USART1 &&                                              \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART1_PRIORITY)
+#error "Invalid IRQ priority assigned to USART1"
+#endif
+
+#if STM32_SERIAL_USE_USART2 &&                                              \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART2_PRIORITY)
+#error "Invalid IRQ priority assigned to USART2"
+#endif
+
+#if STM32_SERIAL_USE_USART3 &&                                              \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART3_PRIORITY)
+#error "Invalid IRQ priority assigned to USART3"
+#endif
+
+#if STM32_SERIAL_USE_UART4 &&                                               \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART4_PRIORITY)
+#error "Invalid IRQ priority assigned to UART4"
+#endif
+
+#if STM32_SERIAL_USE_UART5 &&                                               \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_UART5_PRIORITY)
+#error "Invalid IRQ priority assigned to UART5"
+#endif
+
+#if STM32_SERIAL_USE_USART6 &&                                              \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_SERIAL_USART6_PRIORITY)
+#error "Invalid IRQ priority assigned to USART6"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 Serial Driver configuration structure.
+ * @details An instance of this structure must be passed to @p sdStart()
+ *          in order to configure and start a serial driver operations.
+ * @note    This structure content is architecture dependent, each driver
+ *          implementation defines its own version and the custom static
+ *          initializers.
+ */
+typedef struct {
+  /**
+   * @brief Bit rate.
+   */
+  uint32_t                  sc_speed;
+  /**
+   * @brief Initialization value for the CR1 register.
+   */
+  uint16_t                  sc_cr1;
+  /**
+   * @brief Initialization value for the CR2 register.
+   */
+  uint16_t                  sc_cr2;
+  /**
+   * @brief Initialization value for the CR3 register.
+   */
+  uint16_t                  sc_cr3;
+} SerialConfig;
+
+/**
+ * @brief   @p SerialDriver specific data.
+ */
+#define _serial_driver_data                                                 \
+  _base_asynchronous_channel_data                                           \
+  /* Driver state.*/                                                        \
+  sdstate_t                 state;                                          \
+  /* Input queue.*/                                                         \
+  InputQueue                iqueue;                                         \
+  /* Output queue.*/                                                        \
+  OutputQueue               oqueue;                                         \
+  /* Input circular buffer.*/                                               \
+  uint8_t                   ib[SERIAL_BUFFERS_SIZE];                        \
+  /* Output circular buffer.*/                                              \
+  uint8_t                   ob[SERIAL_BUFFERS_SIZE];                        \
+  /* End of the mandatory fields.*/                                         \
+  /* Pointer to the USART registers block.*/                                \
+  USART_TypeDef             *usart;
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*
+ * Extra USARTs definitions here (missing from the ST header file).
+ */
+#define USART_CR2_STOP1_BITS    (0 << 12)   /**< @brief CR2 1 stop bit value.*/
+#define USART_CR2_STOP0P5_BITS  (1 << 12)   /**< @brief CR2 0.5 stop bit value.*/
+#define USART_CR2_STOP2_BITS    (2 << 12)   /**< @brief CR2 2 stop bit value.*/
+#define USART_CR2_STOP1P5_BITS  (3 << 12)   /**< @brief CR2 1.5 stop bit value.*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_SERIAL_USE_USART1 && !defined(__DOXYGEN__)
+extern SerialDriver SD1;
+#endif
+#if STM32_SERIAL_USE_USART2 && !defined(__DOXYGEN__)
+extern SerialDriver SD2;
+#endif
+#if STM32_SERIAL_USE_USART3 && !defined(__DOXYGEN__)
+extern SerialDriver SD3;
+#endif
+#if STM32_SERIAL_USE_UART4 && !defined(__DOXYGEN__)
+extern SerialDriver SD4;
+#endif
+#if STM32_SERIAL_USE_UART5 && !defined(__DOXYGEN__)
+extern SerialDriver SD5;
+#endif
+#if STM32_SERIAL_USE_USART6 && !defined(__DOXYGEN__)
+extern SerialDriver SD6;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void sd_lld_init(void);
+  void sd_lld_start(SerialDriver *sdp, const SerialConfig *config);
+  void sd_lld_stop(SerialDriver *sdp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SERIAL */
+
+#endif /* _SERIAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32F0xx/platform.mk b/os/hal/platforms/STM32F0xx/platform.mk
index 8586a6990..54b05bdbc 100644
--- a/os/hal/platforms/STM32F0xx/platform.mk
+++ b/os/hal/platforms/STM32F0xx/platform.mk
@@ -7,9 +7,9 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F0xx/stm32_dma.c \
               ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/uart_lld.c
 
 # Required include directories
diff --git a/os/hal/platforms/STM32F1xx/platform.mk b/os/hal/platforms/STM32F1xx/platform.mk
index 80b65fd9a..7e3fc6c1a 100644
--- a/os/hal/platforms/STM32F1xx/platform.mk
+++ b/os/hal/platforms/STM32F1xx/platform.mk
@@ -9,12 +9,12 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F1xx/stm32_dma.c \
               ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
 			  ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv1/pal_lld.c \
 			  ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/RTCv1/rtc_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c
 
diff --git a/os/hal/platforms/STM32F3xx/platform.mk b/os/hal/platforms/STM32F3xx/platform.mk
index 77418721a..0dc6f1892 100644
--- a/os/hal/platforms/STM32F3xx/platform.mk
+++ b/os/hal/platforms/STM32F3xx/platform.mk
@@ -1,7 +1,7 @@
 # List of all the STM32F3xx platform files.
 PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F3xx/hal_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c
+              ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/USARTv2/serial_lld.c
 
 # Required include directories
 PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F3xx \
diff --git a/os/hal/platforms/STM32F4xx/platform.mk b/os/hal/platforms/STM32F4xx/platform.mk
index e39dbda59..2c64a4a17 100644
--- a/os/hal/platforms/STM32F4xx/platform.mk
+++ b/os/hal/platforms/STM32F4xx/platform.mk
@@ -10,12 +10,12 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/stm32_dma.c \
               ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
  			  ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/OTGv1/usb_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/RTCv2/rtc_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c
 
 # Required include directories
diff --git a/os/hal/platforms/STM32L1xx/platform.mk b/os/hal/platforms/STM32L1xx/platform.mk
index f54f5fec3..ea5166a0f 100644
--- a/os/hal/platforms/STM32L1xx/platform.mk
+++ b/os/hal/platforms/STM32L1xx/platform.mk
@@ -7,10 +7,10 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/stm32_dma.c \
               ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
-              ${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
  			  ${CHIBIOS}/os/hal/platforms/STM32/I2Cv1/i2c_lld.c \
+              ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/serial_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/USARTv1/uart_lld.c \
               ${CHIBIOS}/os/hal/platforms/STM32/USBv1/usb_lld.c
 
diff --git a/readme.txt b/readme.txt
index e4b631a57..8af436f34 100644
--- a/readme.txt
+++ b/readme.txt
@@ -161,6 +161,10 @@
   ARMCMx port, now it can support multiple core types.
 - NEW: Updated the Power Architecture rules.mk file to put object and listing
   files into a ./build directory like ARM ports already do.
+- CHANGE: The STM32 Serial driver has been split in two distinct versions,
+  one for older devices up the STM32F4xx, the other for new devices starting
+  from the STM32F0xx.
+  (TODO: Update IAR and Keil projects because different paths).
 
 *** 2.5.0 ***
 - FIX: Fixed anomaly in USB enumeration (bug 3565325)(backported to 2.4.3).