git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@1934 35acf78f-673a-0410-8e92-d51de3d6d3f4
gdisirio
parent
88d93ba5bf
commit
14b049404f
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@ -11,8 +11,8 @@ The currently included items are:
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1. uip-1.0, a minimal TCP/IP implementation: http://www.sics.se/~adam/uip/
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1. uip-1.0, a minimal TCP/IP implementation: http://www.sics.se/~adam/uip/
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2. lwip-1.3.1, lightweight TCP/IP stack: http://savannah.nongnu.org/projects/lwip/
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2. lwip-1.3.1, lightweight TCP/IP stack: http://savannah.nongnu.org/projects/lwip/
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3. STM32 firmware library 3.1.2 (partial) the full download is available from
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3. STM32 firmware library 3.3.0 (partial, library only) the full download is
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http://www.st.com
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available from http://www.st.com
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4. FatFS 0.7e (patched), the original version is available from
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4. FatFS 0.7e (patched), the original version is available from
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http://elm-chan.org/fsw/ff/00index_e.html
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http://elm-chan.org/fsw/ff/00index_e.html
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Binary file not shown.
Binary file not shown.
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@ -44,18 +44,18 @@
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*/
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*/
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#if defined(STM32F10X_MD) || defined(__DOXYGEN__)
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#if defined(STM32F10X_MD) || defined(__DOXYGEN__)
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#define PLATFORM_NAME "STM32 MD"
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#define PLATFORM_NAME "STM32 MD"
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#include "hal_lld_F10x.h"
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#include "hal_lld_F103.h"
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#elif defined(STM32F10X_LD)
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#elif defined(STM32F10X_LD)
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#define PLATFORM_NAME "STM32 LD"
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#define PLATFORM_NAME "STM32 LD"
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#include "hal_lld_F10x.h"
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#include "hal_lld_F103.h"
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#elif defined(STM32F10X_HD)
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#elif defined(STM32F10X_HD)
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#define PLATFORM_NAME "STM32 HD"
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#define PLATFORM_NAME "STM32 HD"
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#include "hal_lld_F10x.h"
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#include "hal_lld_F103.h"
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#elif defined(STM32F10X_CL)
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#elif defined(STM32F10X_CL)
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#define PLATFORM_NAME "STM32 CL"
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#define PLATFORM_NAME "STM32 CL"
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#include "hal_lld_F107.h"
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#include "hal_lld_f105_f107.h"
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#else
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#else
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#error "STM32 platform not specified"
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#error "STM32 platform unknown or not specified"
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#endif
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#endif
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/*===========================================================================*/
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/*===========================================================================*/
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@ -18,15 +18,15 @@
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*/
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*/
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/**
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/**
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* @file STM32/hal_lld_F10x.h
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* @file STM32/hal_lld_f103.h
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* @brief STM32F10x HAL subsystem low level driver header.
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* @brief STM32F103 HAL subsystem low level driver header.
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*
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*
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* @addtogroup STM32F10x_HAL
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* @addtogroup STM32F103_HAL
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* @{
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* @{
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*/
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*/
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#ifndef _HAL_LLD_F10X_H_
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#ifndef _HAL_LLD_F103_H_
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#define _HAL_LLD_F10X_H_
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#define _HAL_LLD_F103_H_
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver constants. */
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/* Driver constants. */
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@ -335,6 +335,6 @@
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#define STM32_FLASHBITS 0x00000012
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#define STM32_FLASHBITS 0x00000012
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#endif
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#endif
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#endif /* _HAL_LLD_F10X_H_ */
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#endif /* _HAL_LLD_F103_H_ */
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/** @} */
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/** @} */
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@ -18,15 +18,15 @@
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*/
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*/
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/**
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/**
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* @file STM32/hal_lld_F107.h
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* @file STM32/hal_lld_f105_f107.h
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* @brief STM32F107 HAL subsystem low level driver header.
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* @brief STM32F10x Connectivity Line HAL subsystem low level driver header.
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*
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*
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* @addtogroup STM32F107_HAL
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* @addtogroup STM32F10X_CL_HAL
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* @{
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* @{
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*/
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*/
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#ifndef _HAL_LLD_F107_H_
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#ifndef _HAL_LLD_F105_F107_H_
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#define _HAL_LLD_F107_H_
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#define _HAL_LLD_F105_F107_H_
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver constants. */
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/* Driver constants. */
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@ -433,6 +433,6 @@
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#define STM32_FLASHBITS 0x00000012
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#define STM32_FLASHBITS 0x00000012
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#endif
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#endif
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#endif /* _HAL_LLD_F107_H_ */
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#endif /* _HAL_LLD_F105_F107_H_ */
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/** @} */
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/** @} */
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@ -2,12 +2,13 @@
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******************************************************************************
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******************************************************************************
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* @file stm32f10x.h
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* @file stm32f10x.h
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* @author MCD Application Team
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* @author MCD Application Team
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* @version V3.1.0
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* @version V3.3.0
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* @date 06/19/2009
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* @date 04/16/2010
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
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* This file contains all the peripheral register's definitions, bits
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* This file contains all the peripheral register's definitions, bits
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* definitions and memory mapping for STM32F10x Connectivity line, High
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* definitions and memory mapping for STM32F10x Connectivity line, High
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* density, Medium density and Low density devices.
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* density, Medium density, Medium density Value line, Low density
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* and Low density Value line and XL-density devices.
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******************************************************************************
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******************************************************************************
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*
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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@ -17,7 +18,7 @@
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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*
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* <h2><center>© COPYRIGHT 2009 STMicroelectronics</center></h2>
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* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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******************************************************************************
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******************************************************************************
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*/
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*/
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@ -44,10 +45,13 @@
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application
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application
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*/
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*/
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#if !defined (STM32F10X_LD) && !defined (STM32F10X_MD) && !defined (STM32F10X_HD) && !defined (STM32F10X_CL)
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#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
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/* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */
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/* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */
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#define STM32F10X_MD /*!< STM32F10X_MD: STM32 Medium density devices */
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/* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */
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/* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */
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/* #define STM32F10X_MD_VL */ /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */
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/* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */
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/* #define STM32F10X_HD */ /*!< STM32F10X_HD: STM32 High density devices */
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#define STM32F10X_XL /*!< STM32F10X_XL: STM32 XL-density devices */
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/* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */
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/* #define STM32F10X_CL */ /*!< STM32F10X_CL: STM32 Connectivity line devices */
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#endif
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#endif
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/* Tip: To avoid modifying this file each time you need to switch between these
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/* Tip: To avoid modifying this file each time you need to switch between these
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- Low density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
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- Low density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
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where the Flash memory density ranges between 16 and 32 Kbytes.
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where the Flash memory density ranges between 16 and 32 Kbytes.
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- Low-density value line devices are STM32F100xx microcontrollers where the Flash
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memory density ranges between 16 and 32 Kbytes.
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- Medium density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
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- Medium density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
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where the Flash memory density ranges between 64 and 128 Kbytes.
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where the Flash memory density ranges between 64 and 128 Kbytes.
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- Medium-density value line devices are STM32F100xx microcontrollers where the
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Flash memory density ranges between 64 and 128 Kbytes.
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- High density devices are STM32F101xx and STM32F103xx microcontrollers where
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- High density devices are STM32F101xx and STM32F103xx microcontrollers where
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the Flash memory density ranges between 256 and 512 Kbytes.
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the Flash memory density ranges between 256 and 512 Kbytes.
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- XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
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the Flash memory density ranges between 512 and 1024 Kbytes.
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- Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
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- Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
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*/
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*/
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@ -78,28 +88,28 @@
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Tip: To avoid modifying this file each time you need to use different HSE, you
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Tip: To avoid modifying this file each time you need to use different HSE, you
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can define the HSE value in your toolchain compiler preprocessor.
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can define the HSE value in your toolchain compiler preprocessor.
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*/
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*/
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#if !defined HSE_Value
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#if !defined HSE_VALUE
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#ifdef STM32F10X_CL
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#ifdef STM32F10X_CL
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#define HSE_Value ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
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#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
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#else
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#else
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#define HSE_Value ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
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#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
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#endif /* STM32F10X_CL */
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#endif /* STM32F10X_CL */
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#endif /* HSE_Value */
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#endif /* HSE_VALUE */
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/**
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/**
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* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
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* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
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Timeout value
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Timeout value
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*/
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*/
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#define HSEStartUp_TimeOut ((uint16_t)0x0500) /*!< Time out for HSE start up */
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#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */
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#define HSI_Value ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
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#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/
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/**
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/**
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* @brief STM32F10x Standard Peripheral Library version number
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* @brief STM32F10x Standard Peripheral Library version number
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*/
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*/
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#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */
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#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:16] STM32F10x Standard Peripheral Library main version */
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#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x01) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */
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#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x03) /*!< [15:8] STM32F10x Standard Peripheral Library sub1 version */
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#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */
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#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [7:0] STM32F10x Standard Peripheral Library sub2 version */
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#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\
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#define __STM32F10X_STDPERIPH_VERSION ((__STM32F10X_STDPERIPH_VERSION_MAIN << 16)\
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| (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\
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| (__STM32F10X_STDPERIPH_VERSION_SUB1 << 8)\
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/**
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/**
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* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
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* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
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*/
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*/
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#define __MPU_PRESENT 0 /*!< STM32 does not provide an MPU */
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#ifdef STM32F10X_XL
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#define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */
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#else
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#define __MPU_PRESENT 0 /*!< Other STM32 devices does not provide an MPU */
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#endif /* STM32F10X_XL */
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#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
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#define __NVIC_PRIO_BITS 4 /*!< STM32 uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
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DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
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DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
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DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
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DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
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DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
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ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
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#ifdef STM32F10X_LD
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#ifdef STM32F10X_LD
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ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
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USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
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USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
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USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
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USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
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CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
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CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
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USART2_IRQn = 38, /*!< USART2 global Interrupt */
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USART2_IRQn = 38, /*!< USART2 global Interrupt */
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EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
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RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
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USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
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USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
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#endif /* STM32F10X_LD */
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#endif /* STM32F10X_LD */
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#ifdef STM32F10X_LD_VL
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ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
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EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
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TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
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TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
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TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
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TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
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TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
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TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
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I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
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I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
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SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
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USART1_IRQn = 37, /*!< USART1 global Interrupt */
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USART2_IRQn = 38, /*!< USART2 global Interrupt */
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EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
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CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
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TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
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TIM7_IRQn = 55 /*!< TIM7 Interrupt */
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#endif /* STM32F10X_LD_VL */
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#ifdef STM32F10X_MD
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#ifdef STM32F10X_MD
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ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
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USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
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USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
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USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
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USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
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CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
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CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
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USART3_IRQn = 39, /*!< USART3 global Interrupt */
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USART3_IRQn = 39, /*!< USART3 global Interrupt */
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EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
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RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
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RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
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USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
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USBWakeUp_IRQn = 42 /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
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#endif /* STM32F10X_MD */
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#endif /* STM32F10X_MD */
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#ifdef STM32F10X_MD_VL
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ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
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EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
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TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
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TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
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TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
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|
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
|
||||||
|
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
|
||||||
|
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
|
||||||
|
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
|
||||||
|
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
|
||||||
|
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
|
||||||
|
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
|
||||||
|
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
|
||||||
|
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
|
||||||
|
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
|
||||||
|
USART1_IRQn = 37, /*!< USART1 global Interrupt */
|
||||||
|
USART2_IRQn = 38, /*!< USART2 global Interrupt */
|
||||||
|
USART3_IRQn = 39, /*!< USART3 global Interrupt */
|
||||||
|
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
|
||||||
|
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
|
||||||
|
CEC_IRQn = 42, /*!< HDMI-CEC Interrupt */
|
||||||
|
TIM6_DAC_IRQn = 54, /*!< TIM6 and DAC underrun Interrupt */
|
||||||
|
TIM7_IRQn = 55 /*!< TIM7 Interrupt */
|
||||||
|
#endif /* STM32F10X_MD_VL */
|
||||||
|
|
||||||
#ifdef STM32F10X_HD
|
#ifdef STM32F10X_HD
|
||||||
|
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
|
||||||
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
|
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
|
||||||
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
|
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
|
||||||
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
|
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
|
||||||
|
|
@ -250,7 +313,53 @@ typedef enum IRQn
|
||||||
DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
|
DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
|
||||||
#endif /* STM32F10X_HD */
|
#endif /* STM32F10X_HD */
|
||||||
|
|
||||||
|
#ifdef STM32F10X_XL
|
||||||
|
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
|
||||||
|
USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
|
||||||
|
USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
|
||||||
|
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
|
||||||
|
CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
|
||||||
|
EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
|
||||||
|
TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break Interrupt and TIM9 global Interrupt */
|
||||||
|
TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global Interrupt */
|
||||||
|
TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
|
||||||
|
TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
|
||||||
|
TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
|
||||||
|
TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
|
||||||
|
TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
|
||||||
|
I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
|
||||||
|
I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
|
||||||
|
I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
|
||||||
|
I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
|
||||||
|
SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
|
||||||
|
SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
|
||||||
|
USART1_IRQn = 37, /*!< USART1 global Interrupt */
|
||||||
|
USART2_IRQn = 38, /*!< USART2 global Interrupt */
|
||||||
|
USART3_IRQn = 39, /*!< USART3 global Interrupt */
|
||||||
|
EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
|
||||||
|
RTCAlarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
|
||||||
|
USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
|
||||||
|
TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global Interrupt */
|
||||||
|
TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global Interrupt */
|
||||||
|
TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
|
||||||
|
TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
|
||||||
|
ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
|
||||||
|
FSMC_IRQn = 48, /*!< FSMC global Interrupt */
|
||||||
|
SDIO_IRQn = 49, /*!< SDIO global Interrupt */
|
||||||
|
TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
|
||||||
|
SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
|
||||||
|
UART4_IRQn = 52, /*!< UART4 global Interrupt */
|
||||||
|
UART5_IRQn = 53, /*!< UART5 global Interrupt */
|
||||||
|
TIM6_IRQn = 54, /*!< TIM6 global Interrupt */
|
||||||
|
TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
|
||||||
|
DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
|
||||||
|
DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
|
||||||
|
DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
|
||||||
|
DMA2_Channel4_5_IRQn = 59 /*!< DMA2 Channel 4 and Channel 5 global Interrupt */
|
||||||
|
#endif /* STM32F10X_XL */
|
||||||
|
|
||||||
#ifdef STM32F10X_CL
|
#ifdef STM32F10X_CL
|
||||||
|
ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
|
||||||
CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
|
CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
|
||||||
CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
|
CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
|
||||||
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
|
CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
|
||||||
|
|
@ -301,7 +410,7 @@ typedef enum IRQn
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#include "core_cm3.h"
|
#include "core_cm3.h"
|
||||||
//#include "system_stm32f10x.h"
|
/*#include "system_stm32f10x.h"*/
|
||||||
#include <stdint.h>
|
#include <stdint.h>
|
||||||
|
|
||||||
/** @addtogroup Exported_types
|
/** @addtogroup Exported_types
|
||||||
|
|
@ -352,6 +461,10 @@ typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
|
||||||
|
|
||||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
|
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
|
||||||
|
|
||||||
|
/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */
|
||||||
|
#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT
|
||||||
|
#define HSE_Value HSE_VALUE
|
||||||
|
#define HSI_Value HSI_VALUE
|
||||||
/**
|
/**
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
@ -555,6 +668,20 @@ typedef struct
|
||||||
#endif /* STM32F10X_CL */
|
#endif /* STM32F10X_CL */
|
||||||
} CAN_TypeDef;
|
} CAN_TypeDef;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Consumer Electronics Control (CEC)
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IO uint32_t CFGR;
|
||||||
|
__IO uint32_t OAR;
|
||||||
|
__IO uint32_t PRES;
|
||||||
|
__IO uint32_t ESR;
|
||||||
|
__IO uint32_t CSR;
|
||||||
|
__IO uint32_t TXD;
|
||||||
|
__IO uint32_t RXD;
|
||||||
|
} CEC_TypeDef;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* @brief CRC calculation unit
|
* @brief CRC calculation unit
|
||||||
*/
|
*/
|
||||||
|
|
@ -587,6 +714,9 @@ typedef struct
|
||||||
__IO uint32_t DHR8RD;
|
__IO uint32_t DHR8RD;
|
||||||
__IO uint32_t DOR1;
|
__IO uint32_t DOR1;
|
||||||
__IO uint32_t DOR2;
|
__IO uint32_t DOR2;
|
||||||
|
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)
|
||||||
|
__IO uint32_t SR;
|
||||||
|
#endif
|
||||||
} DAC_TypeDef;
|
} DAC_TypeDef;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -717,6 +847,14 @@ typedef struct
|
||||||
__IO uint32_t RESERVED;
|
__IO uint32_t RESERVED;
|
||||||
__IO uint32_t OBR;
|
__IO uint32_t OBR;
|
||||||
__IO uint32_t WRPR;
|
__IO uint32_t WRPR;
|
||||||
|
#ifdef STM32F10X_XL
|
||||||
|
uint32_t RESERVED1[8];
|
||||||
|
__IO uint32_t KEYR2;
|
||||||
|
uint32_t RESERVED2;
|
||||||
|
__IO uint32_t SR2;
|
||||||
|
__IO uint32_t CR2;
|
||||||
|
__IO uint32_t AR2;
|
||||||
|
#endif /* STM32F10X_XL */
|
||||||
} FLASH_TypeDef;
|
} FLASH_TypeDef;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -818,6 +956,8 @@ typedef struct
|
||||||
__IO uint32_t EVCR;
|
__IO uint32_t EVCR;
|
||||||
__IO uint32_t MAPR;
|
__IO uint32_t MAPR;
|
||||||
__IO uint32_t EXTICR[4];
|
__IO uint32_t EXTICR[4];
|
||||||
|
uint32_t RESERVED0;
|
||||||
|
__IO uint32_t MAPR2;
|
||||||
} AFIO_TypeDef;
|
} AFIO_TypeDef;
|
||||||
/**
|
/**
|
||||||
* @brief Inter-integrated Circuit Interface
|
* @brief Inter-integrated Circuit Interface
|
||||||
|
|
@ -883,10 +1023,16 @@ typedef struct
|
||||||
__IO uint32_t APB1ENR;
|
__IO uint32_t APB1ENR;
|
||||||
__IO uint32_t BDCR;
|
__IO uint32_t BDCR;
|
||||||
__IO uint32_t CSR;
|
__IO uint32_t CSR;
|
||||||
|
|
||||||
#ifdef STM32F10X_CL
|
#ifdef STM32F10X_CL
|
||||||
__IO uint32_t AHBRSTR;
|
__IO uint32_t AHBRSTR;
|
||||||
__IO uint32_t CFGR2;
|
__IO uint32_t CFGR2;
|
||||||
#endif /* STM32F10X_CL */
|
#endif /* STM32F10X_CL */
|
||||||
|
|
||||||
|
#if defined STM32F10X_LD_VL || defined STM32F10X_MD_VL
|
||||||
|
uint32_t RESERVED0;
|
||||||
|
__IO uint32_t CFGR2;
|
||||||
|
#endif /* STM32F10X_LD_VL || STM32F10X_MD_VL */
|
||||||
} RCC_TypeDef;
|
} RCC_TypeDef;
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
|
@ -1063,8 +1209,8 @@ typedef struct
|
||||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */
|
#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the alias region */
|
||||||
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */
|
#define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the alias region */
|
||||||
|
|
||||||
#define SRAM_BASE ((uint32_t)0x20000000) /*!< Peripheral base address in the bit-band region */
|
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the bit-band region */
|
||||||
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< SRAM base address in the bit-band region */
|
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the bit-band region */
|
||||||
|
|
||||||
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
|
#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
|
||||||
|
|
||||||
|
|
@ -1079,6 +1225,9 @@ typedef struct
|
||||||
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
|
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
|
||||||
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
|
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
|
||||||
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
|
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
|
||||||
|
#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
|
||||||
|
#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
|
||||||
|
#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
|
||||||
#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
|
#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
|
||||||
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
|
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
|
||||||
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
|
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
|
||||||
|
|
@ -1095,6 +1244,7 @@ typedef struct
|
||||||
#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
|
#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
|
||||||
#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
|
#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
|
||||||
#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
|
#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
|
||||||
|
#define CEC_BASE (APB1PERIPH_BASE + 0x7800)
|
||||||
|
|
||||||
#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
|
#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
|
||||||
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
|
#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
|
||||||
|
|
@ -1112,6 +1262,12 @@ typedef struct
|
||||||
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
|
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
|
||||||
#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
|
#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
|
||||||
#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
|
#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
|
||||||
|
#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
|
||||||
|
#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
|
||||||
|
#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
|
||||||
|
#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00)
|
||||||
|
#define TIM10_BASE (APB2PERIPH_BASE + 0x5000)
|
||||||
|
#define TIM11_BASE (APB2PERIPH_BASE + 0x5400)
|
||||||
|
|
||||||
#define SDIO_BASE (PERIPH_BASE + 0x18000)
|
#define SDIO_BASE (PERIPH_BASE + 0x18000)
|
||||||
|
|
||||||
|
|
@ -1163,6 +1319,9 @@ typedef struct
|
||||||
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
|
#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
|
||||||
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
|
#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
|
||||||
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
|
#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
|
||||||
|
#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
|
||||||
|
#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
|
||||||
|
#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
|
||||||
#define RTC ((RTC_TypeDef *) RTC_BASE)
|
#define RTC ((RTC_TypeDef *) RTC_BASE)
|
||||||
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
|
#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
|
||||||
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
|
#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
|
||||||
|
|
@ -1179,6 +1338,7 @@ typedef struct
|
||||||
#define BKP ((BKP_TypeDef *) BKP_BASE)
|
#define BKP ((BKP_TypeDef *) BKP_BASE)
|
||||||
#define PWR ((PWR_TypeDef *) PWR_BASE)
|
#define PWR ((PWR_TypeDef *) PWR_BASE)
|
||||||
#define DAC ((DAC_TypeDef *) DAC_BASE)
|
#define DAC ((DAC_TypeDef *) DAC_BASE)
|
||||||
|
#define CEC ((CEC_TypeDef *) CEC_BASE)
|
||||||
#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
|
#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
|
||||||
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
|
||||||
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
|
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
|
||||||
|
|
@ -1195,6 +1355,12 @@ typedef struct
|
||||||
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
|
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
|
||||||
#define USART1 ((USART_TypeDef *) USART1_BASE)
|
#define USART1 ((USART_TypeDef *) USART1_BASE)
|
||||||
#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
|
#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
|
||||||
|
#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
|
||||||
|
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
|
||||||
|
#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
|
||||||
|
#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
|
||||||
|
#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
|
||||||
|
#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
|
||||||
#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
|
#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
|
||||||
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
|
#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
|
||||||
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
|
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
|
||||||
|
|
@ -1580,6 +1746,40 @@ typedef struct
|
||||||
#define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/
|
#define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /*!< PLL3 clock divided by 2 selected as MCO source*/
|
||||||
#define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
|
#define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */
|
||||||
#define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */
|
#define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /*!< PLL3 clock selected as MCO source */
|
||||||
|
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)
|
||||||
|
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
|
||||||
|
#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */
|
||||||
|
|
||||||
|
#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
|
||||||
|
#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
|
||||||
|
|
||||||
|
#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
|
||||||
|
#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
|
||||||
|
#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
|
||||||
|
#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
|
||||||
|
#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
|
||||||
|
#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
|
||||||
|
#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
|
||||||
|
#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
|
||||||
|
#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
|
||||||
|
#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
|
||||||
|
#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
|
||||||
|
#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
|
||||||
|
#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
|
||||||
|
#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
|
||||||
|
#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
|
||||||
|
|
||||||
|
/*!< MCO configuration */
|
||||||
|
#define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
|
||||||
|
#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
|
||||||
|
#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
|
||||||
|
#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
|
||||||
|
|
||||||
|
#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
|
||||||
|
#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
|
||||||
|
#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
|
||||||
|
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
|
||||||
|
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
|
||||||
#else
|
#else
|
||||||
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
|
#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
|
||||||
#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */
|
#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE clock selected as PLL entry clock source */
|
||||||
|
|
@ -1646,27 +1846,43 @@ typedef struct
|
||||||
#endif /* STM32F10X_CL */
|
#endif /* STM32F10X_CL */
|
||||||
|
|
||||||
/***************** Bit definition for RCC_APB2RSTR register *****************/
|
/***************** Bit definition for RCC_APB2RSTR register *****************/
|
||||||
#define RCC_APB2RSTR_AFIORST ((uint16_t)0x0001) /*!< Alternate Function I/O reset */
|
#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /*!< Alternate Function I/O reset */
|
||||||
#define RCC_APB2RSTR_IOPARST ((uint16_t)0x0004) /*!< I/O port A reset */
|
#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /*!< I/O port A reset */
|
||||||
#define RCC_APB2RSTR_IOPBRST ((uint16_t)0x0008) /*!< I/O port B reset */
|
#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /*!< I/O port B reset */
|
||||||
#define RCC_APB2RSTR_IOPCRST ((uint16_t)0x0010) /*!< I/O port C reset */
|
#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /*!< I/O port C reset */
|
||||||
#define RCC_APB2RSTR_IOPDRST ((uint16_t)0x0020) /*!< I/O port D reset */
|
#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /*!< I/O port D reset */
|
||||||
#define RCC_APB2RSTR_ADC1RST ((uint16_t)0x0200) /*!< ADC 1 interface reset */
|
#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC 1 interface reset */
|
||||||
#define RCC_APB2RSTR_ADC2RST ((uint16_t)0x0400) /*!< ADC 2 interface reset */
|
|
||||||
#define RCC_APB2RSTR_TIM1RST ((uint16_t)0x0800) /*!< TIM1 Timer reset */
|
|
||||||
#define RCC_APB2RSTR_SPI1RST ((uint16_t)0x1000) /*!< SPI 1 reset */
|
|
||||||
#define RCC_APB2RSTR_USART1RST ((uint16_t)0x4000) /*!< USART1 reset */
|
|
||||||
|
|
||||||
#ifndef STM32F10X_LD
|
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL)
|
||||||
#define RCC_APB2RSTR_IOPERST ((uint16_t)0x0040) /*!< I/O port E reset */
|
#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /*!< ADC 2 interface reset */
|
||||||
#endif /* STM32F10X_HD */
|
#endif
|
||||||
|
|
||||||
#ifdef STM32F10X_HD
|
#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 Timer reset */
|
||||||
#define RCC_APB2RSTR_IOPFRST ((uint16_t)0x0080) /*!< I/O port F reset */
|
#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI 1 reset */
|
||||||
#define RCC_APB2RSTR_IOPGRST ((uint16_t)0x0100) /*!< I/O port G reset */
|
#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
|
||||||
#define RCC_APB2RSTR_TIM8RST ((uint16_t)0x2000) /*!< TIM8 Timer reset */
|
|
||||||
#define RCC_APB2RSTR_ADC3RST ((uint16_t)0x8000) /*!< ADC3 interface reset */
|
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)
|
||||||
#endif /* STM32F10X_HD */
|
#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 Timer reset */
|
||||||
|
#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 Timer reset */
|
||||||
|
#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 Timer reset */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
|
||||||
|
#define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /*!< I/O port E reset */
|
||||||
|
#endif /* STM32F10X_LD && STM32F10X_LD_VL */
|
||||||
|
|
||||||
|
#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
|
||||||
|
#define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /*!< I/O port F reset */
|
||||||
|
#define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /*!< I/O port G reset */
|
||||||
|
#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 Timer reset */
|
||||||
|
#define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /*!< ADC3 interface reset */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef STM32F10X_XL
|
||||||
|
#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /*!< TIM9 Timer reset */
|
||||||
|
#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /*!< TIM10 Timer reset */
|
||||||
|
#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /*!< TIM11 Timer reset */
|
||||||
|
#endif /* STM32F10X_XL */
|
||||||
|
|
||||||
/***************** Bit definition for RCC_APB1RSTR register *****************/
|
/***************** Bit definition for RCC_APB1RSTR register *****************/
|
||||||
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
|
#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
|
||||||
|
|
@ -1674,22 +1890,26 @@ typedef struct
|
||||||
#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
|
#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
|
||||||
#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
|
#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
|
||||||
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
|
#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
|
||||||
|
|
||||||
|
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL)
|
||||||
#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */
|
#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN1 reset */
|
||||||
|
#endif
|
||||||
|
|
||||||
#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */
|
#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /*!< Backup interface reset */
|
||||||
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
|
#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
|
||||||
|
|
||||||
#ifndef STM32F10X_LD
|
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
|
||||||
#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
|
#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
|
||||||
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
|
#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
|
||||||
#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */
|
#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< RUSART 3 reset */
|
||||||
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
|
#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
|
||||||
#endif /* STM32F10X_HD */
|
#endif /* STM32F10X_LD && STM32F10X_LD_VL */
|
||||||
|
|
||||||
#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
|
#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD) || defined (STM32F10X_XL)
|
||||||
#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */
|
#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB Device reset */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if defined (STM32F10X_HD) || defined (STM32F10X_CL)
|
#if defined (STM32F10X_HD) || defined (STM32F10X_CL) || defined (STM32F10X_XL)
|
||||||
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
|
#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
|
||||||
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
|
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
|
||||||
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
|
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
|
||||||
|
|
@ -1699,10 +1919,23 @@ typedef struct
|
||||||
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
|
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)
|
||||||
|
#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
|
||||||
|
#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
|
||||||
|
#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
|
||||||
|
#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC interface reset */
|
||||||
|
#endif
|
||||||
|
|
||||||
#ifdef STM32F10X_CL
|
#ifdef STM32F10X_CL
|
||||||
#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x08000000) /*!< CAN2 reset */
|
#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /*!< CAN2 reset */
|
||||||
#endif /* STM32F10X_CL */
|
#endif /* STM32F10X_CL */
|
||||||
|
|
||||||
|
#ifdef STM32F10X_XL
|
||||||
|
#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /*!< TIM12 Timer reset */
|
||||||
|
#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /*!< TIM13 Timer reset */
|
||||||
|
#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< TIM14 Timer reset */
|
||||||
|
#endif /* STM32F10X_XL */
|
||||||
|
|
||||||
/****************** Bit definition for RCC_AHBENR register ******************/
|
/****************** Bit definition for RCC_AHBENR register ******************/
|
||||||
#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */
|
#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /*!< DMA1 clock enable */
|
||||||
#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */
|
#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /*!< SRAM interface clock enable */
|
||||||
|
|
@ -1713,10 +1946,10 @@ typedef struct
|
||||||
#define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */
|
#define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /*!< DMA2 clock enable */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifdef STM32F10X_HD
|
#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
|
||||||
#define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */
|
#define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /*!< FSMC clock enable */
|
||||||
#define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */
|
#define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /*!< SDIO clock enable */
|
||||||
#endif /* STM32F10X_HD */
|
#endif
|
||||||
|
|
||||||
#ifdef STM32F10X_CL
|
#ifdef STM32F10X_CL
|
||||||
#define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */
|
#define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /*!< USB OTG FS clock enable */
|
||||||
|
|
@ -1726,27 +1959,43 @@ typedef struct
|
||||||
#endif /* STM32F10X_CL */
|
#endif /* STM32F10X_CL */
|
||||||
|
|
||||||
/****************** Bit definition for RCC_APB2ENR register *****************/
|
/****************** Bit definition for RCC_APB2ENR register *****************/
|
||||||
#define RCC_APB2ENR_AFIOEN ((uint16_t)0x0001) /*!< Alternate Function I/O clock enable */
|
#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /*!< Alternate Function I/O clock enable */
|
||||||
#define RCC_APB2ENR_IOPAEN ((uint16_t)0x0004) /*!< I/O port A clock enable */
|
#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /*!< I/O port A clock enable */
|
||||||
#define RCC_APB2ENR_IOPBEN ((uint16_t)0x0008) /*!< I/O port B clock enable */
|
#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /*!< I/O port B clock enable */
|
||||||
#define RCC_APB2ENR_IOPCEN ((uint16_t)0x0010) /*!< I/O port C clock enable */
|
#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /*!< I/O port C clock enable */
|
||||||
#define RCC_APB2ENR_IOPDEN ((uint16_t)0x0020) /*!< I/O port D clock enable */
|
#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /*!< I/O port D clock enable */
|
||||||
#define RCC_APB2ENR_ADC1EN ((uint16_t)0x0200) /*!< ADC 1 interface clock enable */
|
#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC 1 interface clock enable */
|
||||||
#define RCC_APB2ENR_ADC2EN ((uint16_t)0x0400) /*!< ADC 2 interface clock enable */
|
|
||||||
#define RCC_APB2ENR_TIM1EN ((uint16_t)0x0800) /*!< TIM1 Timer clock enable */
|
|
||||||
#define RCC_APB2ENR_SPI1EN ((uint16_t)0x1000) /*!< SPI 1 clock enable */
|
|
||||||
#define RCC_APB2ENR_USART1EN ((uint16_t)0x4000) /*!< USART1 clock enable */
|
|
||||||
|
|
||||||
#ifndef STM32F10X_LD
|
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL)
|
||||||
#define RCC_APB2ENR_IOPEEN ((uint16_t)0x0040) /*!< I/O port E clock enable */
|
#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /*!< ADC 2 interface clock enable */
|
||||||
#endif /* STM32F10X_HD */
|
#endif
|
||||||
|
|
||||||
#ifdef STM32F10X_HD
|
#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 Timer clock enable */
|
||||||
#define RCC_APB2ENR_IOPFEN ((uint16_t)0x0080) /*!< I/O port F clock enable */
|
#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI 1 clock enable */
|
||||||
#define RCC_APB2ENR_IOPGEN ((uint16_t)0x0100) /*!< I/O port G clock enable */
|
#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
|
||||||
#define RCC_APB2ENR_TIM8EN ((uint16_t)0x2000) /*!< TIM8 Timer clock enable */
|
|
||||||
#define RCC_APB2ENR_ADC3EN ((uint16_t)0x8000) /*!< DMA1 clock enable */
|
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)
|
||||||
#endif /* STM32F10X_HD */
|
#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 Timer clock enable */
|
||||||
|
#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 Timer clock enable */
|
||||||
|
#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 Timer clock enable */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
|
||||||
|
#define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /*!< I/O port E clock enable */
|
||||||
|
#endif /* STM32F10X_LD && STM32F10X_LD_VL */
|
||||||
|
|
||||||
|
#if defined (STM32F10X_HD) || defined (STM32F10X_XL)
|
||||||
|
#define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /*!< I/O port F clock enable */
|
||||||
|
#define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /*!< I/O port G clock enable */
|
||||||
|
#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 Timer clock enable */
|
||||||
|
#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /*!< DMA1 clock enable */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef STM32F10X_XL
|
||||||
|
#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /*!< TIM9 Timer clock enable */
|
||||||
|
#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /*!< TIM10 Timer clock enable */
|
||||||
|
#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /*!< TIM11 Timer clock enable */
|
||||||
|
#endif
|
||||||
|
|
||||||
/***************** Bit definition for RCC_APB1ENR register ******************/
|
/***************** Bit definition for RCC_APB1ENR register ******************/
|
||||||
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
|
#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
|
||||||
|
|
@ -1754,16 +2003,20 @@ typedef struct
|
||||||
#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
|
#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
|
||||||
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
|
#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
|
||||||
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
|
#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
|
||||||
|
|
||||||
|
#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL)
|
||||||
#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */
|
#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN1 clock enable */
|
||||||
|
#endif
|
||||||
|
|
||||||
#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */
|
#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /*!< Backup interface clock enable */
|
||||||
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
|
#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
|
||||||
|
|
||||||
#ifndef STM32F10X_LD
|
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
|
||||||
#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
|
#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
|
||||||
#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
|
#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
|
||||||
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
|
#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
|
||||||
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
|
#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
|
||||||
#endif /* STM32F10X_HD */
|
#endif /* STM32F10X_LD && STM32F10X_LD_VL */
|
||||||
|
|
||||||
#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
|
#if defined (STM32F10X_HD) || defined (STM32F10X_MD) || defined (STM32F10X_LD)
|
||||||
#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */
|
#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB Device clock enable */
|
||||||
|
|
@ -1779,10 +2032,23 @@ typedef struct
|
||||||
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
|
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)
|
||||||
|
#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
|
||||||
|
#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
|
||||||
|
#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
|
||||||
|
#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC interface clock enable */
|
||||||
|
#endif
|
||||||
|
|
||||||
#ifdef STM32F10X_CL
|
#ifdef STM32F10X_CL
|
||||||
#define RCC_APB1ENR_CAN2EN ((uint32_t)0x08000000) /*!< CAN2 clock enable */
|
#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /*!< CAN2 clock enable */
|
||||||
#endif /* STM32F10X_CL */
|
#endif /* STM32F10X_CL */
|
||||||
|
|
||||||
|
#ifdef STM32F10X_XL
|
||||||
|
#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /*!< TIM12 Timer clock enable */
|
||||||
|
#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /*!< TIM13 Timer clock enable */
|
||||||
|
#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< TIM14 Timer clock enable */
|
||||||
|
#endif /* STM32F10X_XL */
|
||||||
|
|
||||||
/******************* Bit definition for RCC_BDCR register *******************/
|
/******************* Bit definition for RCC_BDCR register *******************/
|
||||||
#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
|
#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
|
||||||
#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
|
#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
|
||||||
|
|
@ -1907,6 +2173,33 @@ typedef struct
|
||||||
#define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */
|
#define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /*!< I2S3 clock source */
|
||||||
#endif /* STM32F10X_CL */
|
#endif /* STM32F10X_CL */
|
||||||
|
|
||||||
|
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)
|
||||||
|
/******************* Bit definition for RCC_CFGR2 register ******************/
|
||||||
|
/*!< PREDIV1 configuration */
|
||||||
|
#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
|
||||||
|
#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
|
||||||
|
#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
|
||||||
|
#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
|
||||||
|
#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
|
||||||
|
|
||||||
|
#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
|
||||||
|
#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
|
||||||
|
#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
|
||||||
|
#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
|
||||||
|
#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
|
||||||
|
#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
|
||||||
|
#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
|
||||||
|
#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
|
||||||
|
#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
|
||||||
|
#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
|
||||||
|
#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
|
||||||
|
#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
|
||||||
|
#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
|
||||||
|
#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
|
||||||
|
#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
|
||||||
|
#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
|
||||||
|
#endif
|
||||||
|
|
||||||
/******************************************************************************/
|
/******************************************************************************/
|
||||||
/* */
|
/* */
|
||||||
/* General Purpose and Alternate Function I/O */
|
/* General Purpose and Alternate Function I/O */
|
||||||
|
|
@ -2460,6 +2753,25 @@ typedef struct
|
||||||
#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
|
#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
|
||||||
#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */
|
#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!< PG[15] pin */
|
||||||
|
|
||||||
|
#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL)
|
||||||
|
/****************** Bit definition for AFIO_MAPR2 register ******************/
|
||||||
|
#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /*!< TIM15 remapping */
|
||||||
|
#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /*!< TIM16 remapping */
|
||||||
|
#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /*!< TIM17 remapping */
|
||||||
|
#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /*!< CEC remapping */
|
||||||
|
#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /*!< TIM1_DMA remapping */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef STM32F10X_XL
|
||||||
|
/****************** Bit definition for AFIO_MAPR2 register ******************/
|
||||||
|
#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /*!< TIM9 remapping */
|
||||||
|
#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /*!< TIM10 remapping */
|
||||||
|
#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /*!< TIM11 remapping */
|
||||||
|
#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /*!< TIM13 remapping */
|
||||||
|
#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /*!< TIM14 remapping */
|
||||||
|
#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /*!< FSMC NADV remapping */
|
||||||
|
#endif
|
||||||
|
|
||||||
/******************************************************************************/
|
/******************************************************************************/
|
||||||
/* */
|
/* */
|
||||||
/* SystemTick */
|
/* SystemTick */
|
||||||
|
|
@ -3712,6 +4024,56 @@ typedef struct
|
||||||
/******************* Bit definition for DAC_DOR2 register *******************/
|
/******************* Bit definition for DAC_DOR2 register *******************/
|
||||||
#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
|
#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
|
||||||
|
|
||||||
|
/******************** Bit definition for DAC_SR register ********************/
|
||||||
|
#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
|
||||||
|
#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/* */
|
||||||
|
/* CEC */
|
||||||
|
/* */
|
||||||
|
/******************************************************************************/
|
||||||
|
/******************** Bit definition for CEC_CFGR register ******************/
|
||||||
|
#define CEC_CFGR_PE ((uint16_t)0x0001) /*!< Peripheral Enable */
|
||||||
|
#define CEC_CFGR_IE ((uint16_t)0x0002) /*!< Interrupt Enable */
|
||||||
|
#define CEC_CFGR_BTEM ((uint16_t)0x0004) /*!< Bit Timing Error Mode */
|
||||||
|
#define CEC_CFGR_BPEM ((uint16_t)0x0008) /*!< Bit Period Error Mode */
|
||||||
|
|
||||||
|
/******************** Bit definition for CEC_OAR register ******************/
|
||||||
|
#define CEC_OAR_OA ((uint16_t)0x000F) /*!< OA[3:0]: Own Address */
|
||||||
|
#define CEC_OAR_OA_0 ((uint16_t)0x0001) /*!< Bit 0 */
|
||||||
|
#define CEC_OAR_OA_1 ((uint16_t)0x0002) /*!< Bit 1 */
|
||||||
|
#define CEC_OAR_OA_2 ((uint16_t)0x0004) /*!< Bit 2 */
|
||||||
|
#define CEC_OAR_OA_3 ((uint16_t)0x0008) /*!< Bit 3 */
|
||||||
|
|
||||||
|
/******************** Bit definition for CEC_PRES register ******************/
|
||||||
|
#define CEC_PRES_PRES ((uint16_t)0x3FFF) /*!< Prescaler Counter Value */
|
||||||
|
|
||||||
|
/******************** Bit definition for CEC_ESR register ******************/
|
||||||
|
#define CEC_ESR_BTE ((uint16_t)0x0001) /*!< Bit Timing Error */
|
||||||
|
#define CEC_ESR_BPE ((uint16_t)0x0002) /*!< Bit Period Error */
|
||||||
|
#define CEC_ESR_RBTFE ((uint16_t)0x0004) /*!< Rx Block Transfer Finished Error */
|
||||||
|
#define CEC_ESR_SBE ((uint16_t)0x0008) /*!< Start Bit Error */
|
||||||
|
#define CEC_ESR_ACKE ((uint16_t)0x0010) /*!< Block Acknowledge Error */
|
||||||
|
#define CEC_ESR_LINE ((uint16_t)0x0020) /*!< Line Error */
|
||||||
|
#define CEC_ESR_TBTFE ((uint16_t)0x0040) /*!< Tx Block Transfer Finsihed Error */
|
||||||
|
|
||||||
|
/******************** Bit definition for CEC_CSR register ******************/
|
||||||
|
#define CEC_CSR_TSOM ((uint16_t)0x0001) /*!< Tx Start Of Message */
|
||||||
|
#define CEC_CSR_TEOM ((uint16_t)0x0002) /*!< Tx End Of Message */
|
||||||
|
#define CEC_CSR_TERR ((uint16_t)0x0004) /*!< Tx Error */
|
||||||
|
#define CEC_CSR_TBTRF ((uint16_t)0x0008) /*!< Tx Byte Transfer Request or Block Transfer Finished */
|
||||||
|
#define CEC_CSR_RSOM ((uint16_t)0x0010) /*!< Rx Start Of Message */
|
||||||
|
#define CEC_CSR_REOM ((uint16_t)0x0020) /*!< Rx End Of Message */
|
||||||
|
#define CEC_CSR_RERR ((uint16_t)0x0040) /*!< Rx Error */
|
||||||
|
#define CEC_CSR_RBTF ((uint16_t)0x0080) /*!< Rx Block Transfer Finished */
|
||||||
|
|
||||||
|
/******************** Bit definition for CEC_TXD register ******************/
|
||||||
|
#define CEC_TXD_TXD ((uint16_t)0x00FF) /*!< Tx Data register */
|
||||||
|
|
||||||
|
/******************** Bit definition for CEC_RXD register ******************/
|
||||||
|
#define CEC_RXD_RXD ((uint16_t)0x00FF) /*!< Rx Data register */
|
||||||
|
|
||||||
/******************************************************************************/
|
/******************************************************************************/
|
||||||
/* */
|
/* */
|
||||||
/* TIM */
|
/* TIM */
|
||||||
|
|
@ -7202,6 +7564,7 @@ typedef struct
|
||||||
#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */
|
#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */
|
||||||
#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */
|
#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */
|
||||||
#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */
|
#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */
|
||||||
|
#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversmapling 8-bits */
|
||||||
|
|
||||||
/****************** Bit definition for USART_CR2 register *******************/
|
/****************** Bit definition for USART_CR2 register *******************/
|
||||||
#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */
|
#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */
|
||||||
|
|
@ -7230,6 +7593,7 @@ typedef struct
|
||||||
#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */
|
#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */
|
||||||
#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */
|
#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */
|
||||||
#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */
|
#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */
|
||||||
|
#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<One Bit method */
|
||||||
|
|
||||||
/****************** Bit definition for USART_GTPR register ******************/
|
/****************** Bit definition for USART_GTPR register ******************/
|
||||||
#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
|
#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */
|
||||||
|
|
@ -7295,6 +7659,15 @@ typedef struct
|
||||||
#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!<TIM6 counter stopped when core is halted */
|
#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /*!<TIM6 counter stopped when core is halted */
|
||||||
#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!<TIM7 counter stopped when core is halted */
|
#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /*!<TIM7 counter stopped when core is halted */
|
||||||
#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!<Debug CAN2 stopped when Core is halted */
|
#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /*!<Debug CAN2 stopped when Core is halted */
|
||||||
|
#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /*!<Debug TIM15 stopped when Core is halted */
|
||||||
|
#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /*!<Debug TIM16 stopped when Core is halted */
|
||||||
|
#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /*!<Debug TIM17 stopped when Core is halted */
|
||||||
|
#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /*!<Debug TIM12 stopped when Core is halted */
|
||||||
|
#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /*!<Debug TIM13 stopped when Core is halted */
|
||||||
|
#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /*!<Debug TIM14 stopped when Core is halted */
|
||||||
|
#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /*!<Debug TIM9 stopped when Core is halted */
|
||||||
|
#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /*!<Debug TIM10 stopped when Core is halted */
|
||||||
|
#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /*!<Debug TIM11 stopped when Core is halted */
|
||||||
|
|
||||||
/******************************************************************************/
|
/******************************************************************************/
|
||||||
/* */
|
/* */
|
||||||
|
|
@ -7347,7 +7720,7 @@ typedef struct
|
||||||
#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!<WDG_SW */
|
#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /*!<WDG_SW */
|
||||||
#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!<nRST_STOP */
|
#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /*!<nRST_STOP */
|
||||||
#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!<nRST_STDBY */
|
#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /*!<nRST_STDBY */
|
||||||
#define FLASH_OBR_Notused ((uint16_t)0x03E0) /*!<Not used */
|
#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /*!<BFB2 */
|
||||||
|
|
||||||
/****************** Bit definition for FLASH_WRPR register ******************/
|
/****************** Bit definition for FLASH_WRPR register ******************/
|
||||||
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!<Write Protect */
|
#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!<Write Protect */
|
||||||
|
|
@ -7848,4 +8221,4 @@ typedef struct
|
||||||
* @}
|
* @}
|
||||||
*/
|
*/
|
||||||
|
|
||||||
/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
|
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
|
||||||
|
|
|
||||||
|
|
@ -72,6 +72,7 @@
|
||||||
- NEW: Added the palSetBusMode() capability to the STM8 PAL driver.
|
- NEW: Added the palSetBusMode() capability to the STM8 PAL driver.
|
||||||
- NEW: Added the palSetBusMode() capability to the LPC11xx and LPC13xx
|
- NEW: Added the palSetBusMode() capability to the LPC11xx and LPC13xx
|
||||||
PAL drivers.
|
PAL drivers.
|
||||||
|
- NEW: Updated the STM32 FW Library files to latest version 3.3.0.
|
||||||
- CHANGE: Renamed the STM32, STM8, LPC214x, AT91SAM7x, MSP430 and simulators
|
- CHANGE: Renamed the STM32, STM8, LPC214x, AT91SAM7x, MSP430 and simulators
|
||||||
PAL configuration structures to PALConfig, it is better to have the same
|
PAL configuration structures to PALConfig, it is better to have the same
|
||||||
name for this structure in all ports (like for all the other drivers).
|
name for this structure in all ports (like for all the other drivers).
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue