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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8342 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
Giovanni Di Sirio 2015-10-05 09:42:28 +00:00
parent e319439395
commit 1380d928ce
1 changed files with 171 additions and 72 deletions
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243
os/hal/ports/STM32/STM32L4xx/stm32_registry.h
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@ -126,6 +126,11 @@
#define STM32_EXTI_LINE4_HANDLER Vector68
#define STM32_EXTI_LINE5_9_HANDLER Vector9C
#define STM32_EXTI_LINE10_15_HANDLER VectorE0
#define STM32_EXTI_LINE1635_38_HANDLER Vector44
#define STM32_EXTI_LINE18_HANDLER VectorE4
#define STM32_EXTI_LINE19_HANDLER Vector48
#define STM32_EXTI_LINE20_HANDLER Vector4C
#define STM32_EXTI_LINE2122_HANDLER Vector140
#define STM32_EXTI_LINE0_NUMBER 6
#define STM32_EXTI_LINE1_NUMBER 7
@ -134,15 +139,20 @@
#define STM32_EXTI_LINE4_NUMBER 10
#define STM32_EXTI_LINE5_9_NUMBER 23
#define STM32_EXTI_LINE10_15_NUMBER 40
#define STM32_EXTI_LINE1635_38_NUMBER 1
#define STM32_EXTI_LINE18_NUMBER 41
#define STM32_EXTI_LINE19_NUMBER 2
#define STM32_EXTI_LINE20_NUMBER 3
#define STM32_EXTI_LINE2122_NUMBER 64
/* GPIO attributes.*/
#define STM32_HAS_GPIOA TRUE
#define STM32_HAS_GPIOB TRUE
#define STM32_HAS_GPIOC TRUE
#define STM32_HAS_GPIOD TRUE
#define STM32_HAS_GPIOE FALSE
#define STM32_HAS_GPIOF FALSE
#define STM32_HAS_GPIOG FALSE
#define STM32_HAS_GPIOE TRUE
#define STM32_HAS_GPIOF TRUE
#define STM32_HAS_GPIOG TRUE
#define STM32_HAS_GPIOH TRUE
#define STM32_HAS_GPIOI FALSE
#define STM32_HAS_GPIOJ FALSE
@ -151,28 +161,44 @@
RCC_IOPENR_GPIOBEN | \
RCC_IOPENR_GPIOCEN | \
RCC_IOPENR_GPIODEN | \
RCC_IOPENR_GPIOEEN | \
RCC_IOPENR_GPIOFEN | \
RCC_IOPENR_GPIOGEN | \
RCC_IOPENR_GPIOHEN)
/* I2C attributes.*/
#define STM32_HAS_I2C1 TRUE
#define STM32_I2C1_GLOBAL_HANDLER Vector9C
#define STM32_I2C1_GLOBAL_NUMBER 23
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
STM32_DMA_STREAM_ID_MSK(1, 7))
#define STM32_I2C1_RX_DMA_CHN 0x06000600
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
STM32_DMA_STREAM_ID_MSK(1, 6))
#define STM32_I2C1_TX_DMA_CHN 0x00600060
#define STM32_I2C1_EVENT_HANDLER VectorBC
#define STM32_I2C1_EVENT_NUMBER 31
#define STM32_I2C1_ERROR_HANDLER VectorC0
#define STM32_I2C1_ERROR_NUMBER 32
#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7) |\
STM32_DMA_STREAM_ID_MSK(2, 6))
#define STM32_I2C1_RX_DMA_CHN 0x03500000
#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6) |\
STM32_DMA_STREAM_ID_MSK(2, 7))
#define STM32_I2C1_TX_DMA_CHN 0x05300000
#define STM32_HAS_I2C2 TRUE
#define STM32_I2C2_GLOBAL_HANDLER VectorA0
#define STM32_I2C2_GLOBAL_NUMBER 24
#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5)
#define STM32_I2C2_RX_DMA_CHN 0x00070000
#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4)
#define STM32_I2C2_TX_DMA_CHN 0x00007000
#define STM32_I2C1_EVENT_HANDLER VectorC4
#define STM32_I2C1_EVENT_NUMBER 33
#define STM32_I2C1_ERROR_HANDLER VectorC8
#define STM32_I2C1_ERROR_NUMBER 34
#define STM32_I2C2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
#define STM32_I2C2_RX_DMA_CHN 0x00030000
#define STM32_I2C2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
#define STM32_I2C2_TX_DMA_CHN 0x00003000
#define STM32_HAS_I2C3 TRUE
#define STM32_I2C1_EVENT_HANDLER Vector160
#define STM32_I2C1_EVENT_NUMBER 72
#define STM32_I2C1_ERROR_HANDLER Vector164
#define STM32_I2C1_ERROR_NUMBER 73
#define STM32_I2C3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
#define STM32_I2C3_RX_DMA_CHN 0x00000300
#define STM32_I2C3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
#define STM32_I2C3_TX_DMA_CHN 0x00000030
#define STM32_HAS_I2C3 FALSE
#define STM32_HAS_I2C4 FALSE
/* RTC attributes.*/
@ -182,59 +208,110 @@
#define STM32_RTC_NUM_ALARMS 1
#define STM32_RTC_HAS_INTERRUPTS FALSE
/* SDIO attributes.*/
#define STM32_HAS_SDIO FALSE
/* SDMMC attributes.*/
#define STM32_HAS_SDMMC1 TRUE
#define STM32_SDMMC1_HANDLER Vector104
#define STM32_SDMMC1_NUMBER 49
#define STM32_SDC_SDMMC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 4) |\
STM32_DMA_STREAM_ID_MSK(2, 5))
#define STM32_SDC_SDMMC1_DMA_CHN 0x00077000
/* SPI attributes.*/
#define STM32_HAS_SPI1 TRUE
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
#define STM32_SPI1_RX_DMA_CHN 0x00000010
#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
#define STM32_SPI1_TX_DMA_CHN 0x00000100
#define STM32_SPI1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
STM32_DMA_STREAM_ID_MSK(2, 3))
#define STM32_SPI1_RX_DMA_CHN 0x00000410
#define STM32_SPI1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
STM32_DMA_STREAM_ID_MSK(2, 4))
#define STM32_SPI1_TX_DMA_CHN 0x00004100
#define STM32_HAS_SPI2 TRUE
#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
STM32_DMA_STREAM_ID_MSK(1, 6))
#define STM32_SPI2_RX_DMA_CHN 0x00202000
#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
STM32_DMA_STREAM_ID_MSK(1, 7))
#define STM32_SPI2_TX_DMA_CHN 0x02020000
#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4))
#define STM32_SPI2_RX_DMA_CHN 0x00001000
#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5))
#define STM32_SPI2_TX_DMA_CHN 0x00010000
#define STM32_HAS_SPI3 FALSE
#define STM32_SPI3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 1))
#define STM32_SPI3_RX_DMA_CHN 0x00000003
#define STM32_SPI3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 2))
#define STM32_SPI3_TX_DMA_CHN 0x00000030
#define STM32_HAS_SPI4 FALSE
#define STM32_HAS_SPI5 FALSE
#define STM32_HAS_SPI6 FALSE
/* TIM attributes.*/
#define STM32_HAS_TIM1 TRUE
#define STM32_TIM1_IS_32BITS FALSE
#define STM32_TIM1_CHANNELS 4
#define STM32_TIM1_UP_HANDLER VectorA4
#define STM32_TIM1_CC_HANDLER VectorAC
#define STM32_TIM1_UP_NUMBER 25
#define STM32_TIM1_CC_NUMBER 27
#define STM32_HAS_TIM2 TRUE
#define STM32_TIM2_IS_32BITS FALSE
#define STM32_TIM2_CHANNELS 4
#define STM32_TIM2_HANDLER Vector7C
#define STM32_TIM2_NUMBER 15
#define STM32_TIM2_HANDLER VectorB0
#define STM32_TIM2_NUMBER 28
#define STM32_HAS_TIM3 TRUE
#define STM32_TIM3_IS_32BITS FALSE
#define STM32_TIM3_CHANNELS 4
#define STM32_TIM3_HANDLER VectorB4
#define STM32_TIM3_NUMBER 29
#define STM32_HAS_TIM4 TRUE
#define STM32_TIM4_IS_32BITS FALSE
#define STM32_TIM4_CHANNELS 4
#define STM32_TIM4_HANDLER VectorB8
#define STM32_TIM4_NUMBER 30
#define STM32_HAS_TIM5 TRUE
#define STM32_TIM5_IS_32BITS TRUE
#define STM32_TIM5_CHANNELS 4
#define STM32_TIM5_HANDLER Vector108
#define STM32_TIM5_NUMBER 50
#define STM32_HAS_TIM6 TRUE
#define STM32_TIM6_IS_32BITS FALSE
#define STM32_TIM6_CHANNELS 0
#define STM32_TIM6_HANDLER Vector84
#define STM32_TIM6_NUMBER 17
#define STM32_TIM6_HANDLER Vector118
#define STM32_TIM6_NUMBER 54
#define STM32_HAS_TIM21 TRUE
#define STM32_TIM21_IS_32BITS FALSE
#define STM32_TIM21_CHANNELS 2
#define STM32_TIM21_HANDLER Vector90
#define STM32_TIM21_NUMBER 20
#define STM32_HAS_TIM7 TRUE
#define STM32_TIM7_IS_32BITS FALSE
#define STM32_TIM7_CHANNELS 0
#define STM32_TIM7_HANDLER Vector11C
#define STM32_TIM7_NUMBER 55
#define STM32_HAS_TIM22 TRUE
#define STM32_TIM22_IS_32BITS FALSE
#define STM32_TIM22_CHANNELS 2
#define STM32_TIM22_HANDLER Vector98
#define STM32_TIM22_NUMBER 22
#define STM32_HAS_TIM8 TRUE
#define STM32_TIM8_IS_32BITS FALSE
#define STM32_TIM8_CHANNELS 6
#define STM32_TIM8_UP_HANDLER VectorF0
#define STM32_TIM8_CC_HANDLER VectorF8
#define STM32_TIM8_UP_NUMBER 44
#define STM32_TIM8_CC_NUMBER 46
#define STM32_HAS_TIM15 TRUE
#define STM32_TIM15_IS_32BITS FALSE
#define STM32_TIM15_CHANNELS 2
#define STM32_TIM15_HANDLER VectorA0
#define STM32_TIM15_NUMBER 24
#define STM32_HAS_TIM16 TRUE
#define STM32_TIM16_IS_32BITS FALSE
#define STM32_TIM16_CHANNELS 2
#define STM32_TIM16_HANDLER VectorA4
#define STM32_TIM16_NUMBER 25
#define STM32_HAS_TIM17 TRUE
#define STM32_TIM17_IS_32BITS FALSE
#define STM32_TIM17_CHANNELS 2
#define STM32_TIM17_HANDLER VectorA8
#define STM32_TIM17_NUMBER 26
#define STM32_HAS_TIM1 FALSE
#define STM32_HAS_TIM3 FALSE
#define STM32_HAS_TIM4 FALSE
#define STM32_HAS_TIM5 FALSE
#define STM32_HAS_TIM7 FALSE
#define STM32_HAS_TIM8 FALSE
#define STM32_HAS_TIM9 FALSE
#define STM32_HAS_TIM10 FALSE
@ -242,44 +319,66 @@
#define STM32_HAS_TIM12 FALSE
#define STM32_HAS_TIM13 FALSE
#define STM32_HAS_TIM14 FALSE
#define STM32_HAS_TIM15 FALSE
#define STM32_HAS_TIM16 FALSE
#define STM32_HAS_TIM17 FALSE
#define STM32_HAS_TIM18 FALSE
#define STM32_HAS_TIM19 FALSE
#define STM32_HAS_TIM20 FALSE
#define STM32_HAS_TIM21 FALSE
#define STM32_HAS_TIM22 FALSE
/* USART attributes.*/
#define STM32_HAS_USART1 TRUE
#define STM32_USART1_HANDLER VectorAC
#define STM32_USART1_NUMBER 27
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\
STM32_DMA_STREAM_ID_MSK(1, 5))
#define STM32_USART1_RX_DMA_CHN 0x00030300
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\
STM32_DMA_STREAM_ID_MSK(1, 4))
#define STM32_USART1_TX_DMA_CHN 0x00003030
#define STM32_USART1_HANDLER VectorD4
#define STM32_USART1_NUMBER 37
#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
STM32_DMA_STREAM_ID_MSK(2, 7))
#define STM32_USART1_RX_DMA_CHN 0x02020000
#define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
STM32_DMA_STREAM_ID_MSK(2, 6))
#define STM32_USART1_TX_DMA_CHN 0x00202000
#define STM32_HAS_USART2 TRUE
#define STM32_USART2_HANDLER VectorB0
#define STM32_USART2_NUMBER 28
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\
STM32_DMA_STREAM_ID_MSK(1, 6))
#define STM32_USART2_RX_DMA_CHN 0x00440000
#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\
STM32_DMA_STREAM_ID_MSK(1, 7))
#define STM32_USART2_TX_DMA_CHN 0x04004000
#define STM32_USART2_HANDLER VectorD8
#define STM32_USART2_NUMBER 38
#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 6))
#define STM32_USART2_RX_DMA_CHN 0x00200000
#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 7))
#define STM32_USART2_TX_DMA_CHN 0x02000000
#define STM32_HAS_USART3 TRUE
#define STM32_USART3_HANDLER VectorDC
#define STM32_USART3_NUMBER 39
#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3))
#define STM32_USART3_RX_DMA_CHN 0x00000200
#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
#define STM32_USART3_TX_DMA_CHN 0x00000020
#define STM32_HAS_UART4 TRUE
#define STM32_UART4_HANDLER Vector110
#define STM32_UART4_NUMBER 52
#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 5)
#define STM32_UART4_RX_DMA_CHN 0x00020000
#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 3)
#define STM32_UART4_TX_DMA_CHN 0x00000200
#define STM32_HAS_UART5 TRUE
#define STM32_UART5_HANDLER Vector114
#define STM32_UART5_NUMBER 53
#define STM32_UART5_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 2)
#define STM32_UART5_RX_DMA_CHN 0x00000020
#define STM32_UART5_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(2, 1)
#define STM32_UART5_TX_DMA_CHN 0x00000002
#define STM32_HAS_USART3 FALSE
#define STM32_HAS_UART4 FALSE
#define STM32_HAS_UART5 FALSE
#define STM32_HAS_USART6 FALSE
#define STM32_HAS_UART7 FALSE
#define STM32_HAS_UART8 FALSE
/* USB attributes.*/
#define STM32_HAS_USB FALSE
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG1 TRUE
#define STM32_OTG1_HANDLER Vector14C
#define STM32_OTG1_NUMBER 67
#define STM32_HAS_OTG2 FALSE
/* LTDC attributes.*/