STM32 CAN driver adapted to the new ISR names.
git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4320 35acf78f-673a-0410-8e92-d51de3d6d3f4master
parent
a41017aac1
commit
11907c39a8
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@ -57,7 +57,7 @@ CANDriver CAND1;
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*
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* @isr
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*/
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CH_IRQ_HANDLER(CAN1_TX_IRQHandler) {
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CH_IRQ_HANDLER(STM32_CAN1_TX_HANDLER) {
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CH_IRQ_PROLOGUE();
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@ -77,7 +77,7 @@ CH_IRQ_HANDLER(CAN1_TX_IRQHandler) {
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*
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* @isr
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*/
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CH_IRQ_HANDLER(CAN1_RX0_IRQHandler) {
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CH_IRQ_HANDLER(STM32_CAN1_RX0_HANDLER) {
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uint32_t rf0r;
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CH_IRQ_PROLOGUE();
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@ -109,7 +109,7 @@ CH_IRQ_HANDLER(CAN1_RX0_IRQHandler) {
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*
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* @isr
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*/
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CH_IRQ_HANDLER(CAN1_RX1_IRQHandler) {
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CH_IRQ_HANDLER(STM32_CAN1_RX1_HANDLER) {
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CH_IRQ_PROLOGUE();
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@ -123,7 +123,7 @@ CH_IRQ_HANDLER(CAN1_RX1_IRQHandler) {
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*
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* @isr
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*/
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CH_IRQ_HANDLER(CAN1_SCE_IRQHandler) {
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CH_IRQ_HANDLER(STM32_CAN1_SCE_HANDLER) {
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uint32_t msr;
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CH_IRQ_PROLOGUE();
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@ -184,13 +184,13 @@ void can_lld_start(CANDriver *canp) {
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/* Clock activation.*/
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#if STM32_CAN_USE_CAN1
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if (&CAND1 == canp) {
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nvicEnableVector(CAN1_TX_IRQn,
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nvicEnableVector(STM32_CAN1_TX_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
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nvicEnableVector(CAN1_RX0_IRQn,
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nvicEnableVector(STM32_CAN1_RX0_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
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nvicEnableVector(CAN1_RX1_IRQn,
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nvicEnableVector(STM32_CAN1_RX1_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
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nvicEnableVector(CAN1_SCE_IRQn,
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nvicEnableVector(STM32_CAN1_SCE_NUMBER,
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CORTEX_PRIORITY_MASK(STM32_CAN_CAN1_IRQ_PRIORITY));
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rccEnableCAN1(FALSE);
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}
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@ -272,10 +272,10 @@ void can_lld_stop(CANDriver *canp) {
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if (&CAND1 == canp) {
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CAN1->MCR = 0x00010002; /* Register reset value. */
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CAN1->IER = 0x00000000; /* All sources disabled. */
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nvicDisableVector(CAN1_TX_IRQn);
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nvicDisableVector(CAN1_RX0_IRQn);
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nvicDisableVector(CAN1_RX1_IRQn);
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nvicDisableVector(CAN1_SCE_IRQn);
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nvicDisableVector(STM32_CAN1_TX_NUMBER);
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nvicDisableVector(STM32_CAN1_RX0_NUMBER);
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nvicDisableVector(STM32_CAN1_RX1_NUMBER);
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nvicDisableVector(STM32_CAN1_SCE_NUMBER);
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rccDisableCAN1(FALSE);
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}
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#endif
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@ -54,10 +54,6 @@
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defined(__DOXYGEN__)
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#include "stm32f10x.h"
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/* Resolving naming anomalies related to the STM32F1xx sub-family.*/
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#define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
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#define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
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#elif defined(STM32F2XX)
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#include "stm32f2xx.h"
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@ -37,6 +37,9 @@
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* @name ISR names and numbers remapping
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* @{
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*/
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/*
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* TIM units.
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*/
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#define STM32_TIM1_UP_HANDLER TIM1_BRK_UP_TRG_COM_IRQHandler
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#define STM32_TIM1_CC_HANDLER TIM1_CC_IRQHandler
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#define STM32_TIM2_HANDLER TIM2_IRQHandler
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@ -37,6 +37,30 @@
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* @name ISR names and numbers remapping
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* @{
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*/
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/*
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* CAN units.
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*/
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#define STM32_CAN1_TX_HANDLER CAN1_TX_IRQHandler
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#define STM32_CAN1_RX0_HANDLER CAN1_RX0_IRQHandler
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#define STM32_CAN1_RX1_HANDLER CAN1_RX1_IRQHandler
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#define STM32_CAN1_SCE_HANDLER CAN1_SCE_IRQHandler
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#define STM32_CAN2_TX_HANDLER CAN2_TX_IRQHandler
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#define STM32_CAN2_RX0_HANDLER CAN2_RX0_IRQHandler
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#define STM32_CAN2_RX1_HANDLER CAN2_RX1_IRQHandler
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#define STM32_CAN2_SCE_HANDLER CAN2_SCE_IRQHandler
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#define STM32_CAN1_TX_NUMBER USB_HP_CAN1_TX_IRQn
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#define STM32_CAN1_RX0_NUMBER USB_LP_CAN1_RX0_IRQn
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#define STM32_CAN1_RX1_NUMBER CAN1_RX1_IRQn
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#define STM32_CAN1_SCE_NUMBER CAN2_SCE_IRQn
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#define STM32_CAN2_TX_NUMBER CAN2_TX_IRQn
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#define STM32_CAN2_RX0_NUMBER CAN2_RX0_IRQn
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#define STM32_CAN2_RX1_NUMBER CAN2_RX1_IRQn
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#define STM32_CAN2_SCE_NUMBER CAN2_SCE_IRQn
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/*
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* TIM units.
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*/
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#if defined(STM32F10X_XL)
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#define STM32_TIM1_UP_HANDLER TIM1_UP_IRQHandler
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#elif defined(STM32F10X_LD_VL) || defined(STM32F10X_MD_VL) || \
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@ -37,6 +37,30 @@
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* @name ISR names and numbers remapping
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* @{
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*/
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/*
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* CAN units.
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*/
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#define STM32_CAN1_TX_HANDLER CAN1_TX_IRQHandler
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#define STM32_CAN1_RX0_HANDLER CAN1_RX0_IRQHandler
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#define STM32_CAN1_RX1_HANDLER CAN1_RX1_IRQHandler
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#define STM32_CAN1_SCE_HANDLER CAN1_SCE_IRQHandler
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#define STM32_CAN2_TX_HANDLER CAN2_TX_IRQHandler
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#define STM32_CAN2_RX0_HANDLER CAN2_RX0_IRQHandler
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#define STM32_CAN2_RX1_HANDLER CAN2_RX1_IRQHandler
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#define STM32_CAN2_SCE_HANDLER CAN2_SCE_IRQHandler
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#define STM32_CAN1_TX_NUMBER USB_HP_CAN1_TX_IRQn
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#define STM32_CAN1_RX0_NUMBER USB_LP_CAN1_RX0_IRQn
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#define STM32_CAN1_RX1_NUMBER CAN1_RX1_IRQn
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#define STM32_CAN1_SCE_NUMBER CAN2_SCE_IRQn
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#define STM32_CAN2_TX_NUMBER CAN2_TX_IRQn
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#define STM32_CAN2_RX0_NUMBER CAN2_RX0_IRQn
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#define STM32_CAN2_RX1_NUMBER CAN2_RX1_IRQn
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#define STM32_CAN2_SCE_NUMBER CAN2_SCE_IRQn
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/*
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* TIM units.
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*/
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#define STM32_TIM1_UP_HANDLER TIM1_UP_IRQHandler
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#define STM32_TIM1_CC_HANDLER TIM1_CC_IRQHandler
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#define STM32_TIM2_HANDLER TIM2_IRQHandler
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@ -37,6 +37,30 @@
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* @name ISR names and numbers remapping
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* @{
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*/
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/*
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* CAN units.
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*/
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#define STM32_CAN1_TX_HANDLER CAN1_TX_IRQHandler
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#define STM32_CAN1_RX0_HANDLER CAN1_RX0_IRQHandler
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#define STM32_CAN1_RX1_HANDLER CAN1_RX1_IRQHandler
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#define STM32_CAN1_SCE_HANDLER CAN1_SCE_IRQHandler
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#define STM32_CAN2_TX_HANDLER CAN2_TX_IRQHandler
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#define STM32_CAN2_RX0_HANDLER CAN2_RX0_IRQHandler
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#define STM32_CAN2_RX1_HANDLER CAN2_RX1_IRQHandler
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#define STM32_CAN2_SCE_HANDLER CAN2_SCE_IRQHandler
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#define STM32_CAN1_TX_NUMBER USB_HP_CAN1_TX_IRQn
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#define STM32_CAN1_RX0_NUMBER USB_LP_CAN1_RX0_IRQn
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#define STM32_CAN1_RX1_NUMBER CAN1_RX1_IRQn
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#define STM32_CAN1_SCE_NUMBER CAN2_SCE_IRQn
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#define STM32_CAN2_TX_NUMBER CAN2_TX_IRQn
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#define STM32_CAN2_RX0_NUMBER CAN2_RX0_IRQn
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#define STM32_CAN2_RX1_NUMBER CAN2_RX1_IRQn
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#define STM32_CAN2_SCE_NUMBER CAN2_SCE_IRQn
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/*
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* TIM units.
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*/
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#define STM32_TIM1_UP_HANDLER TIM1_UP_IRQHandler
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#define STM32_TIM1_CC_HANDLER TIM1_CC_IRQHandler
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#define STM32_TIM2_HANDLER TIM2_IRQHandler
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@ -37,6 +37,9 @@
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* @name ISR names and numbers remapping
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* @{
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*/
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/*
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* TIM units.
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*/
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#define STM32_TIM2_HANDLER TIM2_IRQHandler
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#define STM32_TIM3_HANDLER TIM3_IRQHandler
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#define STM32_TIM4_HANDLER TIM4_IRQHandler
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