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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5369 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2013-03-06 15:42:08 +00:00
parent ff29b4539f
commit 0f61b7caf5
4 changed files with 114 additions and 90 deletions
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76
os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.c
View File

@ -60,11 +60,28 @@ static const edma_channel_config_t *channels[SPC5_EDMA_NCHANNELS];
* @isr
*/
CH_IRQ_HANDLER(vector10) {
edma_channel_t channel;
uint32_t erl, esr = EDMA.ESR.R;
CH_IRQ_PROLOGUE();
/* TODO: Pass to the drivers somehow.*/
chSysHalt();
/* Scanning for errors.*/
channel = 0;
while (((erl = EDMA.ERL.R) != 0) && (channel < SPC5_EDMA_NCHANNELS)) {
if ((erl & (1U << channel)) != 0) {
/* Error flag cleared.*/
EDMA.CER.R = channel;
/* If the channel is not associated then the error is simply discarded
else the error callback is invoked.*/
if (channels[channel] != NULL)
channels[channel]->dma_error_func(channel,
channels[channel]->dma_param,
esr);
channel++;
}
}
CH_IRQ_EPILOGUE();
}
@ -82,7 +99,6 @@ CH_IRQ_HANDLER(vector11) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 0;
if (channels[0] != NULL)
channels[0]->dma_func(0, channels[0]->dma_param);
CH_IRQ_EPILOGUE();
@ -101,7 +117,6 @@ CH_IRQ_HANDLER(vector12) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 1;
if (channels[1] != NULL)
channels[1]->dma_func(1, channels[1]->dma_param);
CH_IRQ_EPILOGUE();
@ -120,7 +135,6 @@ CH_IRQ_HANDLER(vector13) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 2;
if (channels[2] != NULL)
channels[2]->dma_func(2, channels[2]->dma_param);
CH_IRQ_EPILOGUE();
@ -139,7 +153,6 @@ CH_IRQ_HANDLER(vector14) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 3;
if (channels[3] != NULL)
channels[3]->dma_func(3, channels[3]->dma_param);
CH_IRQ_EPILOGUE();
@ -158,7 +171,6 @@ CH_IRQ_HANDLER(vector15) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 4;
if (channels[4] != NULL)
channels[4]->dma_func(4, channels[4]->dma_param);
CH_IRQ_EPILOGUE();
@ -177,7 +189,6 @@ CH_IRQ_HANDLER(vector16) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 5;
if (channels[5] != NULL)
channels[5]->dma_func(5, channels[5]->dma_param);
CH_IRQ_EPILOGUE();
@ -196,7 +207,6 @@ CH_IRQ_HANDLER(vector17) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 6;
if (channels[6] != NULL)
channels[6]->dma_func(6, channels[6]->dma_param);
CH_IRQ_EPILOGUE();
@ -215,7 +225,6 @@ CH_IRQ_HANDLER(vector18) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 7;
if (channels[7] != NULL)
channels[7]->dma_func(7, channels[7]->dma_param);
CH_IRQ_EPILOGUE();
@ -234,7 +243,6 @@ CH_IRQ_HANDLER(vector19) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 8;
if (channels[8] != NULL)
channels[8]->dma_func(8, channels[8]->dma_param);
CH_IRQ_EPILOGUE();
@ -253,7 +261,6 @@ CH_IRQ_HANDLER(vector20) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 9;
if (channels[9] != NULL)
channels[9]->dma_func(9, channels[9]->dma_param);
CH_IRQ_EPILOGUE();
@ -272,7 +279,6 @@ CH_IRQ_HANDLER(vector21) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 10;
if (channels[10] != NULL)
channels[10]->dma_func(10, channels[10]->dma_param);
CH_IRQ_EPILOGUE();
@ -291,7 +297,6 @@ CH_IRQ_HANDLER(vector22) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 11;
if (channels[11] != NULL)
channels[11]->dma_func(11, channels[11]->dma_param);
CH_IRQ_EPILOGUE();
@ -310,7 +315,6 @@ CH_IRQ_HANDLER(vector23) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 12;
if (channels[12] != NULL)
channels[12]->dma_func(12, channels[12]->dma_param);
CH_IRQ_EPILOGUE();
@ -329,7 +333,6 @@ CH_IRQ_HANDLER(vector24) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 13;
if (channels[13] != NULL)
channels[13]->dma_func(13, channels[13]->dma_param);
CH_IRQ_EPILOGUE();
@ -348,7 +351,6 @@ CH_IRQ_HANDLER(vector25) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 14;
if (channels[14] != NULL)
channels[14]->dma_func(14, channels[14]->dma_param);
CH_IRQ_EPILOGUE();
@ -367,7 +369,6 @@ CH_IRQ_HANDLER(vector26) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 15;
if (channels[15] != NULL)
channels[15]->dma_func(15, channels[15]->dma_param);
CH_IRQ_EPILOGUE();
@ -387,7 +388,6 @@ CH_IRQ_HANDLER(vector27) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 16;
if (channels[16] != NULL)
channels[16]->dma_func(16, channels[16]->dma_param);
CH_IRQ_EPILOGUE();
@ -406,7 +406,6 @@ CH_IRQ_HANDLER(vector28) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 17;
if (channels[17] != NULL)
channels[17]->dma_func(17, channels[17]->dma_param);
CH_IRQ_EPILOGUE();
@ -425,7 +424,6 @@ CH_IRQ_HANDLER(vector29) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 18;
if (channels[18] != NULL)
channels[18]->dma_func(18, channels[18]->dma_param);
CH_IRQ_EPILOGUE();
@ -444,7 +442,6 @@ CH_IRQ_HANDLER(vector30) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 19;
if (channels[19] != NULL)
channels[19]->dma_func(19, channels[19]->dma_param);
CH_IRQ_EPILOGUE();
@ -463,7 +460,6 @@ CH_IRQ_HANDLER(vector31) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 20;
if (channels[20] != NULL)
channels[20]->dma_func(20, channels[20]->dma_param);
CH_IRQ_EPILOGUE();
@ -482,7 +478,6 @@ CH_IRQ_HANDLER(vector32) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 21;
if (channels[21] != NULL)
channels[21]->dma_func(21, channels[21]->dma_param);
CH_IRQ_EPILOGUE();
@ -501,7 +496,6 @@ CH_IRQ_HANDLER(vector33) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 22;
if (channels[22] != NULL)
channels[22]->dma_func(22, channels[22]->dma_param);
CH_IRQ_EPILOGUE();
@ -520,7 +514,6 @@ CH_IRQ_HANDLER(vector34) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 23;
if (channels[23] != NULL)
channels[23]->dma_func(23, channels[23]->dma_param);
CH_IRQ_EPILOGUE();
@ -539,7 +532,6 @@ CH_IRQ_HANDLER(vector35) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 24;
if (channels[24] != NULL)
channels[24]->dma_func(24, channels[24]->dma_param);
CH_IRQ_EPILOGUE();
@ -558,7 +550,6 @@ CH_IRQ_HANDLER(vector36) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 25;
if (channels[25] != NULL)
channels[25]->dma_func(25, channels[25]->dma_param);
CH_IRQ_EPILOGUE();
@ -577,7 +568,6 @@ CH_IRQ_HANDLER(vector37) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 26;
if (channels[26] != NULL)
channels[26]->dma_func(26, channels[26]->dma_param);
CH_IRQ_EPILOGUE();
@ -596,7 +586,6 @@ CH_IRQ_HANDLER(vector38) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 27;
if (channels[27] != NULL)
channels[27]->dma_func(27, channels[27]->dma_param);
CH_IRQ_EPILOGUE();
@ -615,7 +604,6 @@ CH_IRQ_HANDLER(vector39) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 28;
if (channels[28] != NULL)
channels[28]->dma_func(28, channels[28]->dma_param);
CH_IRQ_EPILOGUE();
@ -634,7 +622,6 @@ CH_IRQ_HANDLER(vector40) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 29;
if (channels[29] != NULL)
channels[29]->dma_func(29, channels[29]->dma_param);
CH_IRQ_EPILOGUE();
@ -653,7 +640,6 @@ CH_IRQ_HANDLER(vector41) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 30;
if (channels[30] != NULL)
channels[30]->dma_func(30, channels[30]->dma_param);
CH_IRQ_EPILOGUE();
@ -672,7 +658,6 @@ CH_IRQ_HANDLER(vector42) {
SPC5_EDMA_ERROR_HANDLER();
}
EDMA.CIRQR.R = 31;
if (channels[31] != NULL)
channels[31]->dma_func(31, channels[31]->dma_param);
CH_IRQ_EPILOGUE();
@ -698,6 +683,9 @@ void edmaInit(void) {
EDMA.ERL.R = 0xFFFFFFFF;
for (i = 0; i < SPC5_EDMA_NCHANNELS; i++)
EDMA.CPR[i].R = 0;
/* Error interrupt source.*/
INTC.PSR[10].R = SPC5_EDMA_ERROR_IRQ_PRIO;
}
/**
@ -720,14 +708,24 @@ edma_channel_t edmaChannelAllocate(const edma_channel_config_t *ccfg) {
#if SPC5_EDMA_HAS_MUX
/* TODO: MUX handling.*/
channel = EDMA_ERROR;
return channel;
#else /* !SPC5_EDMA_HAS_MUX */
channel = (edma_channel_t)ccfg->dma_periph;
if (channels[channel] != NULL)
return EDMA_ERROR; /* Already taken.*/
channels[channel] = ccfg;
return channel;
#endif /* !SPC5_EDMA_HAS_MUX */
/* Associating the configuration to the channel.*/
channels[channel] = ccfg;
/* If an error callback is defined then the erro interrupt source is
enabled for the channel.*/
if (ccfg->dma_error_func != NULL)
EDMA.SEEIR.R = channel;
/* Setting up IRQ priority for the selected channel.*/
INTC.PSR[11 + channel].R = ccfg->dma_irq_prio;
return channel;
}
/**
@ -745,6 +743,10 @@ void edmaChannelRelease(edma_channel_t channel) {
"edmaChannelRelease(), #1",
"not allocated");
/* Error IRQ masked for the released channel.*/
EDMA.CEEIR.R = channel;
/* The channels is flagged as available.*/
channels[channel] = NULL;
}

23
os/hal/platforms/SPC5xx/EDMA_v1/spc5_edma.h
View File

@ -68,6 +68,14 @@
#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
#endif
/**
* @brief EDMA error handler IRQ priority.
*/
#if !defined(SPC5_ADC0_FIFO2_DMA_IRQ_PRIO) || defined(__DOXYGEN__)
#define SPC5_EDMA_ERROR_IRQ_PRIO 12
#endif
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
@ -96,13 +104,24 @@ typedef struct {
} edma_tcd_t;
/**
* @brief DMA ISR function type.
* @brief DMA callback type.
*
* @param[in] channel the channel number
* @param[in] p parameter for the registered function
*/
typedef void (*edma_callback_t)(edma_channel_t channel, void *p);
/**
* @brief DMA error callback type.
*
* @param[in] channel the channel number
* @param[in] p parameter for the registered function
* @param[in] esr content of the ESR register
*/
typedef void (*edma_error_callback_t)(edma_channel_t channel,
void *p,
uint32_t esr);
/**
* @brief Type of an EDMA channel configuration structure.
*/
@ -114,7 +133,7 @@ typedef struct {
uint8_t dma_irq_prio; /**< @brief IRQ priority level for
this channel. */
edma_callback_t dma_func; /**< @brief Channel callback. */
edma_callback_t dma_error_func; /**< @brief Channel error callback. */
edma_error_callback_t dma_error_func; /**< @brief Channel error callback. */
void *dma_param; /**< @brief Channel callback param. */
} edma_channel_config_t;

28
os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.c
View File

@ -27,7 +27,9 @@
/* Some forward declarations.*/
static void adc_serve_rfifo_irq(edma_channel_t channel, void *p);
static void adc_serve_dma_error_irq(edma_channel_t channel, void *p);
static void adc_serve_dma_error_irq(edma_channel_t channel,
void *p,
uint32_t esr);
/*===========================================================================*/
/* Driver local definitions. */
@ -434,16 +436,18 @@ static void adc_serve_rfifo_irq(edma_channel_t channel, void *p) {
*
* @param[in] channel the channel number
* @param[in] p parameter for the registered function
* @param[in] esr content of the ESR register
*
* @notapi
*/
static void adc_serve_dma_error_irq(edma_channel_t channel, void *p) {
static void adc_serve_dma_error_irq(edma_channel_t channel,
void *p,
uint32_t esr) {
ADCDriver *adcp = (ADCDriver *)p;
(void)channel;
(void)esr;
/* DMA, this could help only if the DMA tries to access an unmapped
address space or violates alignment rules.*/
_adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
}
@ -620,6 +624,10 @@ void adc_lld_start(ADCDriver *adcp) {
0, /* slast, no source adjust. */
0, /* dlast, temporary. */
0); /* mode, temporary. */
/* HW triggers setup.*/
SIU.ETISR.R = adcp->config->etisr;
SIU.ISEL3.R = adcp->config->isel3;
}
/**
@ -637,16 +645,6 @@ void adc_lld_stop(ADCDriver *adcp) {
/* Releases the allocated EDMA channels.*/
edmaChannelRelease(adcp->cfifo_channel);
edmaChannelRelease(adcp->rfifo_channel);
/* Disables the peripheral.*/
#if SPC5_ADC_USE_ADC0_Q0
if (&ADCD1 == adcp) {
}
#endif /* SPC5_ADC_USE_ADC0_Q0 */
#if SPC5_ADC_USE_ADC1_Q3
if (&ADCD1 == adcp) {
}
#endif /* SPC5_ADC_USE_ADC1_Q3 */
}
}
@ -667,8 +665,6 @@ void adc_lld_start_conversion(ADCDriver *adcp) {
chDbgAssert(adcp->grpp->num_iterations >= adcp->depth,
"adc_lld_start_conversion(), #1", "too many elements");
/* TODO: ISEL0, ISEL3 setup for HW triggers.*/
/* Updating the variable TCD fields for CFIFO.*/
edmaTCDSetSourceAddress(ctcdp, adcp->grpp->commands);
edmaTCDSetOuterLoopCount(ctcdp, (uint32_t)adcp->grpp->num_channels *

11
os/hal/platforms/SPC5xx/EQADC_v1/adc_lld.h
View File

@ -374,7 +374,7 @@
/*===========================================================================*/
#if !SPC5_HAS_EQADC
#error "EQADC1 not present in the selected device"
#error "EQADC not present in the selected device"
#endif
#define SPC5_ADC_USE_ADC0 (SPC5_ADC_USE_ADC0_Q0 | \
@ -502,7 +502,14 @@ typedef struct {
* @note It could be empty on some architectures.
*/
typedef struct {
uint32_t dummy;
/**
* @brief ETISR register value for the session.
*/
uint32_t etisr;
/**
* @brief ISEL3 register value for the session.
*/
uint32_t isel3;
} ADCConfig;
/**