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git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@3175 35acf78f-673a-0410-8e92-d51de3d6d3f4

master
gdisirio 2011-07-23 16:32:03 +00:00
parent b774805ce9
commit 0bf0705e33
7 changed files with 15 additions and 12 deletions
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4
demos/ARMCM3-STM32L152-DISCOVERY/halconf.h
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@ -115,7 +115,7 @@
* @brief Enables the SERIAL over USB subsystem.
*/
#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
#define HAL_USE_SERIAL_USB FALSE
#define HAL_USE_SERIAL_USB TRUE
#endif
/**
@ -136,7 +136,7 @@
* @brief Enables the USB subsystem.
*/
#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
#define HAL_USE_USB FALSE
#define HAL_USE_USB TRUE
#endif
/*===========================================================================*/

12
os/hal/platforms/STM32/USBv1/usb_lld.c
View File

@ -171,7 +171,7 @@ static size_t read_packet(usbep_t ep, uint8_t *buf, size_t n){
*
* @isr
*/
CH_IRQ_HANDLER(USB_HP_IRQHandler) {
CH_IRQ_HANDLER(Vector8C) {
CH_IRQ_PROLOGUE();
@ -183,7 +183,7 @@ CH_IRQ_HANDLER(USB_HP_IRQHandler) {
*
* @isr
*/
CH_IRQ_HANDLER(USB_LP_IRQHandler) {
CH_IRQ_HANDLER(Vector90) {
uint32_t istr;
size_t n;
USBDriver *usbp = &USBD1;
@ -335,9 +335,9 @@ void usb_lld_start(USBDriver *usbp) {
STM32_USB->CNTR = CNTR_FRES;
/* Enabling the USB IRQ vectors, this also gives enough time to allow
the transceiver power up (1uS).*/
NVICEnableVector(USB_HP_CAN1_TX_IRQn,
NVICEnableVector(19,
CORTEX_PRIORITY_MASK(STM32_USB_USB1_HP_IRQ_PRIORITY));
NVICEnableVector(USB_LP_CAN1_RX0_IRQn,
NVICEnableVector(20,
CORTEX_PRIORITY_MASK(STM32_USB_USB1_LP_IRQ_PRIORITY));
/* Releases the USB reset.*/
STM32_USB->CNTR = 0;
@ -362,8 +362,8 @@ void usb_lld_stop(USBDriver *usbp) {
if (usbp->state == USB_STOP) {
#if STM32_ADC_USE_ADC1
if (&USBD1 == usbp) {
NVICDisableVector(USB_HP_CAN1_TX_IRQn);
NVICDisableVector(USB_LP_CAN1_RX0_IRQn);
NVICDisableVector(19);
NVICDisableVector(20);
STM32_USB->CNTR = CNTR_PDWN | CNTR_FRES;
RCC->APB1ENR &= ~RCC_APB1ENR_USBEN;
}

4
os/hal/platforms/STM32/pwm_lld.c
View File

@ -519,10 +519,12 @@ void pwm_lld_start(PWMDriver *pwmp) {
pwmp->tim->EGR = TIM_EGR_UG; /* Update event. */
pwmp->tim->DIER = pwmp->config->callback == NULL ? 0 : TIM_DIER_UIE;
pwmp->tim->SR = 0; /* Clear pending IRQs. */
#if STM32_PWM_USE_TIM1 || STM32_PWM_USE_TIM8
#if STM32_PWM_USE_ADVANCED
pwmp->tim->BDTR = pwmp->config->bdtr | TIM_BDTR_MOE;
#else
pwmp->tim->BDTR = TIM_BDTR_MOE;
#endif
#endif
/* Timer configured and started.*/
pwmp->tim->CR1 = TIM_CR1_ARPE | TIM_CR1_URS | TIM_CR1_CEN;
@ -542,7 +544,9 @@ void pwm_lld_stop(PWMDriver *pwmp) {
pwmp->tim->CR1 = 0; /* Timer disabled. */
pwmp->tim->DIER = 0; /* All IRQs disabled. */
pwmp->tim->SR = 0; /* Clear eventual pending IRQs. */
#if STM32_PWM_USE_TIM1 || STM32_PWM_USE_TIM8
pwmp->tim->BDTR = 0;
#endif
#if STM32_PWM_USE_TIM1
if (&PWMD1 == pwmp) {

0
os/hal/platforms/STM32/DMAv1/adc_lld.c → os/hal/platforms/STM32F1xx/adc_lld.c
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0
os/hal/platforms/STM32/DMAv1/adc_lld.h → os/hal/platforms/STM32F1xx/adc_lld.h
View File

6
os/hal/platforms/STM32L1xx/hal_lld.h
View File

@ -367,7 +367,7 @@
/**
* @brief Maximum HSECLK at current voltage setting.
*/
#define STM32_HSECLK_MAX 32000000
#define STM32_HSECLK_MAX 32000000#if
/**
* @brief Maximum SYSCLK at current voltage setting.
@ -430,7 +430,7 @@
#if (STM32_HSECLK < 1000000) || (STM32_HSECLK > STM32_HSECLK_MAX)
#error "STM32_HSECLK outside acceptable range (1MHz...STM32_HSECLK_MAX)"
#endif
#else /* !#if STM32_HSE_ENABLED */
#else /* !STM32_HSE_ENABLED */
#if (STM32_SW == STM32_SW_HSE) || \
((STM32_SW == STM32_SW_PLL) && \
(STM32_PLLSRC == STM32_PLLSRC_HSE)) || \
@ -440,7 +440,7 @@
(STM_RTC_SOURCE == STM32_RTCSEL_HSEDIV)
#error "required HSE clock is not enabled"
#endif
#endif /* !#if STM32_HSE_ENABLED */
#endif /* !STM32_HSE_ENABLED */
/* LSI related checks.*/
#if STM32_LSI_ENABLED

1
os/hal/platforms/STM32L1xx/platform.mk
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@ -5,7 +5,6 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32L1xx/hal_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/DMAv1/adc_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/DMAv1/spi_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/DMAv1/uart_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/DMAv1/stm32_dma.c \