From 09d8d2dfdc588422c7353314ab1f0fe61305b6b5 Mon Sep 17 00:00:00 2001 From: theShed Date: Thu, 7 Mar 2013 15:00:21 +0000 Subject: [PATCH] Initial LPC8xx port git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5376 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/EA_LPCXPRESSO_LPC812/board.c | 140 ++++ boards/EA_LPCXPRESSO_LPC812/board.h | 129 ++++ boards/EA_LPCXPRESSO_LPC812/board.mk | 5 + demos/ARMCM0P-LPC812-LPCXPRESSO/Makefile | 196 +++++ demos/ARMCM0P-LPC812-LPCXPRESSO/chconf.h | 535 ++++++++++++++ demos/ARMCM0P-LPC812-LPCXPRESSO/halconf.h | 316 ++++++++ demos/ARMCM0P-LPC812-LPCXPRESSO/lpc8xx_isp.py | 141 ++++ demos/ARMCM0P-LPC812-LPCXPRESSO/main.c | 71 ++ demos/ARMCM0P-LPC812-LPCXPRESSO/mcuconf.h | 82 +++ os/hal/platforms/LPC8xx/LPC8xx.h | 686 ++++++++++++++++++ os/hal/platforms/LPC8xx/gpt_lld.c | 282 +++++++ os/hal/platforms/LPC8xx/gpt_lld.h | 196 +++++ os/hal/platforms/LPC8xx/hal_lld.c | 145 ++++ os/hal/platforms/LPC8xx/hal_lld.h | 225 ++++++ os/hal/platforms/LPC8xx/pal_lld.c | 109 +++ os/hal/platforms/LPC8xx/pal_lld.h | 294 ++++++++ os/hal/platforms/LPC8xx/platform.dox | 108 +++ os/hal/platforms/LPC8xx/platform.mk | 8 + os/hal/platforms/LPC8xx/serial_lld.c | 354 +++++++++ os/hal/platforms/LPC8xx/serial_lld.h | 273 +++++++ os/hal/platforms/LPC8xx/system_LPC8xx.h | 62 ++ os/ports/GCC/ARMCMx/LPC8xx/cmparams.h | 60 ++ os/ports/GCC/ARMCMx/LPC8xx/ld/LPC812.ld | 150 ++++ os/ports/GCC/ARMCMx/LPC8xx/port.mk | 15 + os/ports/GCC/ARMCMx/LPC8xx/vectors.c | 199 +++++ os/ports/GCC/ARMCMx/rules.mk | 4 +- readme.txt | 1 + 27 files changed, 4784 insertions(+), 2 deletions(-) create mode 100644 boards/EA_LPCXPRESSO_LPC812/board.c create mode 100644 boards/EA_LPCXPRESSO_LPC812/board.h create mode 100644 boards/EA_LPCXPRESSO_LPC812/board.mk create mode 100644 demos/ARMCM0P-LPC812-LPCXPRESSO/Makefile create mode 100644 demos/ARMCM0P-LPC812-LPCXPRESSO/chconf.h create mode 100644 demos/ARMCM0P-LPC812-LPCXPRESSO/halconf.h create mode 100755 demos/ARMCM0P-LPC812-LPCXPRESSO/lpc8xx_isp.py create mode 100644 demos/ARMCM0P-LPC812-LPCXPRESSO/main.c create mode 100644 demos/ARMCM0P-LPC812-LPCXPRESSO/mcuconf.h create mode 100644 os/hal/platforms/LPC8xx/LPC8xx.h create mode 100644 os/hal/platforms/LPC8xx/gpt_lld.c create mode 100644 os/hal/platforms/LPC8xx/gpt_lld.h create mode 100644 os/hal/platforms/LPC8xx/hal_lld.c create mode 100644 os/hal/platforms/LPC8xx/hal_lld.h create mode 100644 os/hal/platforms/LPC8xx/pal_lld.c create mode 100644 os/hal/platforms/LPC8xx/pal_lld.h create mode 100644 os/hal/platforms/LPC8xx/platform.dox create mode 100644 os/hal/platforms/LPC8xx/platform.mk create mode 100644 os/hal/platforms/LPC8xx/serial_lld.c create mode 100644 os/hal/platforms/LPC8xx/serial_lld.h create mode 100644 os/hal/platforms/LPC8xx/system_LPC8xx.h create mode 100644 os/ports/GCC/ARMCMx/LPC8xx/cmparams.h create mode 100644 os/ports/GCC/ARMCMx/LPC8xx/ld/LPC812.ld create mode 100644 os/ports/GCC/ARMCMx/LPC8xx/port.mk create mode 100644 os/ports/GCC/ARMCMx/LPC8xx/vectors.c diff --git a/boards/EA_LPCXPRESSO_LPC812/board.c b/boards/EA_LPCXPRESSO_LPC812/board.c new file mode 100644 index 000000000..6e3f0735c --- /dev/null +++ b/boards/EA_LPCXPRESSO_LPC812/board.c @@ -0,0 +1,140 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = {VAL_GPIO0DATA, VAL_GPIO0DIR}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void){ + + lpc8xx_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void){ + + /* Enable clocks to IOCON & SWM */ + LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<18)|(1<<7)); + +#if defined VAL_PIO0_0 + LPC_IOCON->PIO0_0 = PIN_RSVD|VAL_PIO0_0; +#endif +#if defined VAL_PIO0_1 + LPC_IOCON->PIO0_1 = PIN_RSVD|VAL_PIO0_1; +#endif +#if defined VAL_PIO0_2 + LPC_IOCON->PIO0_2 = PIN_RSVD|VAL_PIO0_2; +#endif +#if defined VAL_PIO0_3 + LPC_IOCON->PIO0_3 = PIN_RSVD|VAL_PIO0_3; +#endif +#if defined VAL_PIO0_4 + LPC_IOCON->PIO0_4 = PIN_RSVD|VAL_PIO0_4; +#endif +#if defined VAL_PIO0_5 + LPC_IOCON->PIO0_5 = PIN_RSVD|VAL_PIO0_5; +#endif +#if defined VAL_PIO0_6 + LPC_IOCON->PIO0_6 = PIN_RSVD|VAL_PIO0_6; +#endif +#if defined VAL_PIO0_7 + LPC_IOCON->PIO0_7 = PIN_RSVD|VAL_PIO0_7; +#endif +#if defined VAL_PIO0_8 + LPC_IOCON->PIO0_8 = PIN_RSVD|VAL_PIO0_8; +#endif +#if defined VAL_PIO0_9 + LPC_IOCON->PIO0_9 = PIN_RSVD|VAL_PIO0_9; +#endif +#if defined VAL_PIO0_10 + LPC_IOCON->PIO0_10 = PIN_RSVD|VAL_PIO0_10; +#endif +#if defined VAL_PIO0_11 + LPC_IOCON->PIO0_11 = PIN_RSVD|VAL_PIO0_11; +#endif +#if defined VAL_PIO0_12 + LPC_IOCON->PIO0_12 = PIN_RSVD|VAL_PIO0_12; +#endif +#if defined VAL_PIO0_13 + LPC_IOCON->PIO0_13 = PIN_RSVD|VAL_PIO0_13; +#endif +#if defined VAL_PIO0_14 + LPC_IOCON->PIO0_14 = PIN_RSVD|VAL_PIO0_14; +#endif +#if defined VAL_PIO0_15 + LPC_IOCON->PIO0_15 = PIN_RSVD|VAL_PIO0_15; +#endif +#if defined VAL_PIO0_16 + LPC_IOCON->PIO0_16 = PIN_RSVD|VAL_PIO0_16; +#endif +#if defined VAL_PIO0_17 + LPC_IOCON->PIO0_17 = PIN_RSVD|VAL_PIO0_17; +#endif + + +#if defined VAL_PINASSIGN0 + LPC_SWM->PINASSIGN0 = VAL_PINASSIGN0; +#endif +#if defined VAL_PINASSIGN1 + LPC_SWM->PINASSIGN1 = VAL_PINASSIGN1; +#endif +#if defined VAL_PINASSIGN2 + LPC_SWM->PINASSIGN2 = VAL_PINASSIGN2; +#endif +#if defined VAL_PINASSIGN3 + LPC_SWM->PINASSIGN3 = VAL_PINASSIGN3; +#endif +#if defined VAL_PINASSIGN4 + LPC_SWM->PINASSIGN4 = VAL_PINASSIGN4; +#endif +#if defined VAL_PINASSIGN5 + LPC_SWM->PINASSIGN5 = VAL_PINASSIGN5; +#endif +#if defined VAL_PINASSIGN6 + LPC_SWM->PINASSIGN6 = VAL_PINASSIGN6; +#endif +#if defined VAL_PINASSIGN7 + LPC_SWM->PINASSIGN7 = VAL_PINASSIGN7; +#endif +#if defined VAL_PINASSIGN8 + LPC_SWM->PINASSIGN8 = VAL_PINASSIGN8; +#endif + + /* Disable clocks to IOCON & SWM */ + LPC_SYSCON->SYSAHBCLKCTRL &= ~((1<<18)|(1<<7)); + +} + + diff --git a/boards/EA_LPCXPRESSO_LPC812/board.h b/boards/EA_LPCXPRESSO_LPC812/board.h new file mode 100644 index 000000000..f1e05c103 --- /dev/null +++ b/boards/EA_LPCXPRESSO_LPC812/board.h @@ -0,0 +1,129 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for Embedded Artists LPCXpresso LPC812 board. + */ + +/* + * Board identifiers. + */ +#define BOARD_EA_LPC812 +#define BOARD_NAME "Embedded Artists LPCXpresso LPC812" + +/* + * Board frequencies. + */ +#define SYSOSCCLK 12000000 + + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the LPC8xx Reference Manual for details. + */ +/* Pull-up/down */ +#define PIN_MODE_NOPULL (0<<3) +#define PIN_MODE_PULLDOWN (1<<3) +#define PIN_MODE_PULLUP (2<<3) +#define PIN_MODE_REPEATER (3<<3) +/* Hysteresis */ +#define PIN_HYS_EN (1<<5) +/* Invert Input */ +#define PIN_INV_INPUT (1<<6) +/* Reserved bits */ +#define PIN_RSVD (1<<7) +/* I2C Mode */ +#define PIN_I2CMODE_STD (0<<8) +#define PIN_I2CMODE_STDIO (1<<8) +#define PIN_I2CMODE_FAST (2<<8) +/* Open Drain */ +#define PIN_OPEN_DRAIN (1<<10) +/* Input Filter Sample Clocks */ +#define PIN_SMODE_FILTER(n) ((n)<<11) +/* Input Filter clock divider */ +#define PIN_CLKDIV_FILTER(n) ((n)<<13) + +/* + * Pin definitions. + */ +#define LED_RED 7 +#define LED_BLUE 16 +#define LED_GREEN 17 + + +/* + * GPIO 0 initial setup. + */ +/*#define VAL_PIO0_0 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_1 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_2 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_3 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_4 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_5 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_6 PIN_MODE_PULLUP*/ +#define VAL_PIO0_7 PIN_MODE_NOPULL +/*#define VAL_PIO0_8 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_9 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_10 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_11 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_12 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_13 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_14 PIN_MODE_PULLUP*/ +/*#define VAL_PIO0_15 PIN_MODE_PULLUP*/ +#define VAL_PIO0_16 PIN_MODE_NOPULL +#define VAL_PIO0_17 PIN_MODE_NOPULL + + /* UART0: TXD = P0.4, RXD = P0.0)*/ +#define VAL_PINASSIGN0 ((0xFFFF<<16) | (0<<8) | (4)) +/*#define VAL_PINASSIGN1 0xFFFFFFFF*/ +/*#define VAL_PINASSIGN2 0xFFFFFFFF*/ +/*#define VAL_PINASSIGN3 0xFFFFFFFF*/ +/*#define VAL_PINASSIGN4 0xFFFFFFFF*/ +/*#define VAL_PINASSIGN5 0xFFFFFFFF*/ +/*#define VAL_PINASSIGN6 0xFFFFFFFF*/ +/*#define VAL_PINASSIGN7 0xFFFFFFFF*/ +/*#define VAL_PINASSIGN8 0xFFFFFFFF*/ + + +#define VAL_GPIO0DIR (PAL_PORT_BIT(LED_RED) | \ + PAL_PORT_BIT(LED_BLUE) | \ + PAL_PORT_BIT(LED_GREEN)) + +#define VAL_GPIO0DATA (PAL_PORT_BIT(LED_RED) | \ + PAL_PORT_BIT(LED_BLUE) | \ + PAL_PORT_BIT(LED_GREEN)) + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + + +#endif /* _BOARD_H_ */ diff --git a/boards/EA_LPCXPRESSO_LPC812/board.mk b/boards/EA_LPCXPRESSO_LPC812/board.mk new file mode 100644 index 000000000..de80424bb --- /dev/null +++ b/boards/EA_LPCXPRESSO_LPC812/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS}/boards/EA_LPCXPRESSO_LPC812/board.c + +# Required include directories +BOARDINC = ${CHIBIOS}/boards/EA_LPCXPRESSO_LPC812 diff --git a/demos/ARMCM0P-LPC812-LPCXPRESSO/Makefile b/demos/ARMCM0P-LPC812-LPCXPRESSO/Makefile new file mode 100644 index 000000000..37d897ddf --- /dev/null +++ b/demos/ARMCM0P-LPC812-LPCXPRESSO/Makefile @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -Os -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/EA_LPCXPRESSO_LPC812/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC8xx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC8xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/LPC812.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DLPC812 -D__NEWLIB__ + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM0P-LPC812-LPCXPRESSO/chconf.h b/demos/ARMCM0P-LPC812-LPCXPRESSO/chconf.h new file mode 100644 index 000000000..ae54d3edf --- /dev/null +++ b/demos/ARMCM0P-LPC812-LPCXPRESSO/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM0P-LPC812-LPCXPRESSO/halconf.h b/demos/ARMCM0P-LPC812-LPCXPRESSO/halconf.h new file mode 100644 index 000000000..c78a58996 --- /dev/null +++ b/demos/ARMCM0P-LPC812-LPCXPRESSO/halconf.h @@ -0,0 +1,316 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM0P-LPC812-LPCXPRESSO/lpc8xx_isp.py b/demos/ARMCM0P-LPC812-LPCXPRESSO/lpc8xx_isp.py new file mode 100755 index 000000000..13f976bf9 --- /dev/null +++ b/demos/ARMCM0P-LPC812-LPCXPRESSO/lpc8xx_isp.py @@ -0,0 +1,141 @@ +#!/usr/bin/env python +import serial +import array + +#========================================================= +PORT = '/dev/ttyUSB1' +FILE = 'build/ch.bin' + +RAM_ADDR = 0x10000300 +PAGE_SIZE = 0x40 +SECTOR_SIZE = 0x400 +FLASH_SIZE = 0x4000 + +#========================================================= +ser = serial.Serial( PORT, 115200, timeout=1) + +data = array.array('B') +f = file( FILE, 'rb') +try: + data.fromfile(f, FLASH_SIZE) +except: + pass +f.close() + +## pad out to next whole page +data.fromstring( chr(0xff)*(PAGE_SIZE - (data.buffer_info()[1]%PAGE_SIZE)) ) + +#========================================================= +## fix-up LPC boot checksum +csum = 0; +for i in range(7): + csum = csum + \ + (data[(i*4)] ) + \ + (data[(i*4)+1]<<8 ) + \ + (data[(i*4)+2]<<16) + \ + (data[(i*4)+3]<<24); \ + +csum = -csum +data[28] = csum & 0xff +data[29] = csum>>8 & 0xff +data[30] = csum>>16 & 0xff +data[31] = csum>>24 & 0xff + +#========================================================= +## +ser.write('?') +resp = ser.readline() +if resp.strip() <> 'Synchronized': + print 'No Response "?"' + exit(1) + +ser.write('Synchronized\r\n') +resp = ser.readline() +resp = ser.readline() +if resp.strip() <> 'OK': + print 'Not Synchronized' + exit(1) + +ser.write('12000\r\n') +resp = ser.readline() +resp = ser.readline() +if resp.strip() <> 'OK': + print 'No Response "12000"' + exit(1) + +ser.write('A 0\r\n') +resp = ser.readline() +resp = ser.readline() +if resp.strip() <> '0': + print 'Error Response "A"', resp + exit(1) + +ser.write('J\r\n') +resp = ser.readline() +if resp.strip() <> '0': + print 'Error Response "J"', resp + exit(1) +resp = ser.readline() +print 'Device ID: ', hex(int(resp)) + +ser.write('U 23130\r\n') +resp = ser.readline() +if resp.strip() <> '0': + print 'Error Response "U"', resp + exit(1) + + +## Erase whole device +ser.write('P 0 7\r\n') +resp = ser.readline() +if resp.strip() <> '0': + print 'Error Response "P"', resp + exit(1) + +ser.write('E 0 7\r\n') +resp = ser.readline() +if resp.strip() <> '0': + print 'Error Response "P"', resp + exit(1) + + +#========================================================= +address = 0 + +while data.buffer_info()[1]: + + ser.write( "W %d %d\r\n"%(RAM_ADDR, PAGE_SIZE) ) + resp = ser.readline() + if resp.strip() <> '0': + print 'Error Response "W"', resp + exit(1) + + for i in range(PAGE_SIZE): + ser.write( chr(data.pop(0)) ) + + #print('P %x %x\r\n'%( address/SECTOR_SIZE, address/SECTOR_SIZE )) + #print('C %x %x 0xff\r\n'%( address, RAM_ADDR )) + + ## Program page + ser.write('P %d %d\r\n'%( address/SECTOR_SIZE, address/SECTOR_SIZE )) + resp = ser.readline() + if resp.strip() <> '0': + print 'Error Response "P"', resp + exit(1) + + ser.write( 'C %d %d %d\r\n'%(address, RAM_ADDR, PAGE_SIZE) ) + resp = ser.readline() + if resp.strip() <> '0': + print 'Error Response "C"', resp + exit(1) + + print '.', + address = address + PAGE_SIZE + if (address%SECTOR_SIZE) == 0: + print '' + +#========================================================= +#========================================================= + + + diff --git a/demos/ARMCM0P-LPC812-LPCXPRESSO/main.c b/demos/ARMCM0P-LPC812-LPCXPRESSO/main.c new file mode 100644 index 000000000..852c47965 --- /dev/null +++ b/demos/ARMCM0P-LPC812-LPCXPRESSO/main.c @@ -0,0 +1,71 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +/* + * RGB LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); + +static msg_t Thread1(void *arg) { + (void)arg; + chRegSetThreadName("blinker"); + + palTogglePort(GPIO0, PAL_PORT_BIT(LED_GREEN)); + + while (TRUE) { + palTogglePort(GPIO0, PAL_PORT_BIT(LED_GREEN)); + palTogglePort(GPIO0, PAL_PORT_BIT(LED_RED)); + chThdSleepMilliseconds(500); + + palTogglePort(GPIO0, PAL_PORT_BIT(LED_RED)); + palTogglePort(GPIO0, PAL_PORT_BIT(LED_BLUE)); + chThdSleepMilliseconds(500); + + palTogglePort(GPIO0, PAL_PORT_BIT(LED_BLUE)); + palTogglePort(GPIO0, PAL_PORT_BIT(LED_GREEN)); + chThdSleepMilliseconds(500); + } + + return 0; +} + +int main(void){ + + halInit(); + chSysInit(); + + sdStart(&SD1, NULL); /* Default: 9600,8,N,1. */ + + chThdCreateStatic(waThread1, sizeof(waThread1), + NORMALPRIO, Thread1, NULL); + + chnWrite( &SD1, (const uint8_t *)"\nhello\n", 8 ); + + do { + chThdSleepMilliseconds(500); + } while (TRUE); + + return 0; +} + diff --git a/demos/ARMCM0P-LPC812-LPCXPRESSO/mcuconf.h b/demos/ARMCM0P-LPC812-LPCXPRESSO/mcuconf.h new file mode 100644 index 000000000..f5321ceee --- /dev/null +++ b/demos/ARMCM0P-LPC812-LPCXPRESSO/mcuconf.h @@ -0,0 +1,82 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC812 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...highest. + */ + +/* + * HAL driver system settings. + */ + +/* Default: Run PLL @24MHz from 12MHz IRC + #define LPC8xx_PLLCLK_SOURCE SYSPLLCLKSEL_IRCOSC + #define LPC8xx_SYSPLL_MUL 4 + #define LPC8xx_SYSPLL_DIV 4 + #define LPC8xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT + #define LPC8xx_SYSABHCLK_DIV 1 +*/ + +/*run directly from internal 12M osc...*/ +#define LPC8xx_MAINCLK_SOURCE SYSMAINCLKSEL_IRCOSC + +/* + * GPT driver system settings. + */ +/* Defaults: + #define LPC8xx_GPT_USE_MRT0 TRUE + #define LPC8xx_GPT_USE_MRT1 FALSE + #define LPC8xx_GPT_USE_MRT2 FALSE + #define LPC8xx_GPT_USE_MRT3 FALSE + #define LPC8xx_GPT_MRT_IRQ_PRIORITY 2 +*/ + +/* + * PWM driver system settings. + */ + +/* + * SERIAL driver system settings. + */ +/* Defaults: + #define LPC8xx_SERIAL_USE_UART0 TRUE + #define LPC8xx_SERIAL_USE_UART1 FALSE + #define LPC8xx_SERIAL_USE_UART2 FALSE + #define LPC8xx_SERIAL_UART0_IRQ_PRIORITY 3 + #define LPC8xx_SERIAL_UART1_IRQ_PRIORITY 3 + #define LPC8xx_SERIAL_UART2_IRQ_PRIORITY 3 + + #define LPC8xx_SERIAL_U_PCLK 11059200 + #define LPC8xx_SERIAL_UARTCLKDIV !!Calculated!! + #define LPC8xx_SERIAL_UARTFRGMUL !!Calculated!! + #define LPC8xx_SERIAL_UARTFRGDIV !!Calculated!! +*/ + +/* change default baudrate to 9600 */ +#define SERIAL_DEFAULT_BITRATE 9600 + + diff --git a/os/hal/platforms/LPC8xx/LPC8xx.h b/os/hal/platforms/LPC8xx/LPC8xx.h new file mode 100644 index 000000000..6cb473ee2 --- /dev/null +++ b/os/hal/platforms/LPC8xx/LPC8xx.h @@ -0,0 +1,686 @@ +/**************************************************************************** + * $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694 $ + * Project: NXP LPC8xx software example + * + * Description: + * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for + * NXP LPC800 Device Series + * + **************************************************************************** + * Software that is described herein is for illustrative purposes only + * which provides customers with programming information regarding the + * products. This software is supplied "AS IS" without any warranties. + * NXP Semiconductors assumes no responsibility or liability for the + * use of the software, conveys no license or title under any patent, + * copyright, or mask work right to the product. NXP Semiconductors + * reserves the right to make changes in the software without + * notification. NXP Semiconductors also make no representation or + * warranty that such application will be suitable for the specified + * use without further testing or modification. + + * Permission to use, copy, modify, and distribute this software and its + * documentation is hereby granted, under NXP Semiconductors' + * relevant copyright in the software, without fee, provided that it + * is used in conjunction with NXP Semiconductors microcontrollers. This + * copyright, permission, and disclaimer notice must appear in all copies of + * this code. +****************************************************************************/ +#ifndef __LPC8xx_H__ +#define __LPC8xx_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/** @addtogroup LPC8xx_Definitions LPC8xx Definitions + This file defines all structures and symbols for LPC8xx: + - Registers and bitfields + - peripheral base address + - PIO definitions + @{ +*/ + + +/******************************************************************************/ +/* Processor and Core Peripherals */ +/******************************************************************************/ +/** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions + Configuration of the Cortex-M0+ Processor and Core Peripherals + @{ +*/ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ +typedef enum IRQn +{ +/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ + Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ + +/****** LPC8xx Specific Interrupt Numbers ********************************************************/ + SPI0_IRQn = 0, /*!< SPI0 */ + SPI1_IRQn = 1, /*!< SPI1 */ + Reserved0_IRQn = 2, /*!< Reserved Interrupt */ + UART0_IRQn = 3, /*!< USART0 */ + UART1_IRQn = 4, /*!< USART1 */ + UART2_IRQn = 5, /*!< USART2 */ + Reserved1_IRQn = 6, /*!< Reserved Interrupt */ + Reserved2_IRQn = 7, /*!< Reserved Interrupt */ + I2C_IRQn = 8, /*!< I2C */ + SCT_IRQn = 9, /*!< SCT */ + MRT_IRQn = 10, /*!< MRT */ + CMP_IRQn = 11, /*!< CMP */ + WDT_IRQn = 12, /*!< WDT */ + BOD_IRQn = 13, /*!< BOD */ + Reserved3_IRQn = 14, /*!< Reserved Interrupt */ + WKT_IRQn = 15, /*!< WKT Interrupt */ + Reserved4_IRQn = 16, /*!< Reserved Interrupt */ + Reserved5_IRQn = 17, /*!< Reserved Interrupt */ + Reserved6_IRQn = 18, /*!< Reserved Interrupt */ + Reserved7_IRQn = 19, /*!< Reserved Interrupt */ + Reserved8_IRQn = 20, /*!< Reserved Interrupt */ + Reserved9_IRQn = 21, /*!< Reserved Interrupt */ + Reserved10_IRQn = 22, /*!< Reserved Interrupt */ + Reserved11_IRQn = 23, /*!< Reserved Interrupt */ + PININT0_IRQn = 24, /*!< External Interrupt 0 */ + PININT1_IRQn = 25, /*!< External Interrupt 1 */ + PININT2_IRQn = 26, /*!< External Interrupt 2 */ + PININT3_IRQn = 27, /*!< External Interrupt 3 */ + PININT4_IRQn = 28, /*!< External Interrupt 4 */ + PININT5_IRQn = 29, /*!< External Interrupt 5 */ + PININT6_IRQn = 30, /*!< External Interrupt 6 */ + PININT7_IRQn = 31, /*!< External Interrupt 7 */ +} IRQn_Type; + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M0+ Processor and Core Peripherals */ +#define __MPU_PRESENT 0 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/*@}*/ /* end of group LPC8xx_CMSIS */ + + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ +#include "system_LPC8xx.h" /* System Header */ + + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/*------------- System Control (SYSCON) --------------------------------------*/ +/** @addtogroup LPC8xx_SYSCON LPC8xx System Control Block + @{ +*/ +typedef struct +{ + __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */ + __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */ + __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */ + __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/W ) */ + uint32_t RESERVED0[4]; + + __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */ + __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */ + uint32_t RESERVED1[2]; + __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/W ) */ + uint32_t RESERVED2[3]; + __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */ + __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */ + uint32_t RESERVED3[10]; + + __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */ + __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */ + __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */ + uint32_t RESERVED4[1]; + + __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */ + uint32_t RESERVED5[4]; + __IO uint32_t UARTCLKDIV; /*!< Offset: 0x094 UART clock divider (R/W) */ + uint32_t RESERVED6[18]; + + __IO uint32_t CLKOUTSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */ + __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */ + __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */ + uint32_t RESERVED7; + __IO uint32_t UARTFRGDIV; /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */ + __IO uint32_t UARTFRGMULT; /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */ + uint32_t RESERVED8[1]; + __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */ + __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */ + uint32_t RESERVED9[12]; + __IO uint32_t IOCONCLKDIV[7]; /*!< (@0x40048134-14C) Peripheral clock x to the IOCON block for programmable glitch filter */ + __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */ + __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */ + uint32_t RESERVED10[6]; + __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IRQ delay */ + __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */ + __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */ + uint32_t RESERVED11[27]; + __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */ + uint32_t RESERVED12[3]; + __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */ + uint32_t RESERVED13[6]; + __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */ + __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */ + __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */ + uint32_t RESERVED14[110]; + __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */ +} LPC_SYSCON_TypeDef; +/*@}*/ /* end of group LPC8xx_SYSCON */ + + +/** + * @brief Product name title=UM10462 Chapter title=LPC8xx I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG) + */ + +typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */ + __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */ + __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */ + __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */ + __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */ + __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */ + __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */ + __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */ + __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */ + __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */ + __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */ + __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */ + __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */ + __IO uint32_t Reserved; /*!< (@ 0x40044030) I/O configuration for pin (Reserved) */ + __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */ + __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */ + __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */ + __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */ + __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */ + __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */ +} LPC_IOCON_TypeDef; +/*@}*/ /* end of group LPC8xx_IOCON */ + +/** + * @brief Product name title=UM10462 Chapter title=LPC8xx Flash programming firmware Major revision=0 Minor revision=3 (FLASHCTRL) + */ +typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */ + __I uint32_t RESERVED0[4]; + __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */ + __I uint32_t RESERVED1[3]; + __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */ + __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */ + __I uint32_t RESERVED2; + __I uint32_t FMSW0; +} LPC_FLASHCTRL_TypeDef; +/*@}*/ /* end of group LPC8xx_FLASHCTRL */ + + +/*------------- Power Management Unit (PMU) --------------------------*/ +/** @addtogroup LPC8xx_PMU LPC8xx Power Management Unit + @{ +*/ +typedef struct +{ + __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */ + __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */ + __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */ + __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */ + __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */ + __IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */ +} LPC_PMU_TypeDef; +/*@}*/ /* end of group LPC8xx_PMU */ + + +/*------------- Switch Matrix Port --------------------------*/ +/** @addtogroup LPC8xx_SWM LPC8xx Switch Matrix Port + @{ +*/ +typedef struct +{ + union { + __IO uint32_t PINASSIGN[9]; + struct { + __IO uint32_t PINASSIGN0; + __IO uint32_t PINASSIGN1; + __IO uint32_t PINASSIGN2; + __IO uint32_t PINASSIGN3; + __IO uint32_t PINASSIGN4; + __IO uint32_t PINASSIGN5; + __IO uint32_t PINASSIGN6; + __IO uint32_t PINASSIGN7; + __IO uint32_t PINASSIGN8; + }; + }; + __I uint32_t RESERVED0[103]; + __IO uint32_t PINENABLE0; +} LPC_SWM_TypeDef; +/*@}*/ /* end of group LPC8xx_SWM */ + + +// ------------------------------------------------------------------------------------------------ +// ----- GPIO_PORT ----- +// ------------------------------------------------------------------------------------------------ + +/** + * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT) + */ + +typedef struct { + __IO uint8_t B0[18]; /*!< (@ 0xA0000000) Byte pin registers port 0 */ + __I uint16_t RESERVED0[2039]; + __IO uint32_t W0[18]; /*!< (@ 0xA0001000) Word pin registers port 0 */ + uint32_t RESERVED1[1006]; + __IO uint32_t DIR0; /* 0x2000 */ + uint32_t RESERVED2[31]; + __IO uint32_t MASK0; /* 0x2080 */ + uint32_t RESERVED3[31]; + __IO uint32_t PIN0; /* 0x2100 */ + uint32_t RESERVED4[31]; + __IO uint32_t MPIN0; /* 0x2180 */ + uint32_t RESERVED5[31]; + __IO uint32_t SET0; /* 0x2200 */ + uint32_t RESERVED6[31]; + __O uint32_t CLR0; /* 0x2280 */ + uint32_t RESERVED7[31]; + __O uint32_t NOT0; /* 0x2300 */ + +} LPC_GPIO_PORT_TypeDef; + + +// ------------------------------------------------------------------------------------------------ +// ----- PIN_INT ----- +// ------------------------------------------------------------------------------------------------ + +/** + * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (PIN_INT) + */ + +typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */ + __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */ + __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */ + __IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */ + __IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */ + __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */ + __IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */ + __IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */ + __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */ + __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */ + __IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */ + __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */ + __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */ + __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */ +} LPC_PIN_INT_TypeDef; + + +/*------------- CRC Engine (CRC) -----------------------------------------*/ +/** @addtogroup LPC8xx_CRC + @{ +*/ +typedef struct +{ + __IO uint32_t MODE; + __IO uint32_t SEED; + union { + __I uint32_t SUM; + __O uint32_t WR_DATA_DWORD; + __O uint16_t WR_DATA_WORD; + uint16_t RESERVED_WORD; + __O uint8_t WR_DATA_BYTE; + uint8_t RESERVED_BYTE[3]; + }; +} LPC_CRC_TypeDef; +/*@}*/ /* end of group LPC8xx_CRC */ + +/*------------- Comparator (CMP) --------------------------------------------------*/ +/** @addtogroup LPC8xx_CMP LPC8xx Comparator + @{ +*/ +typedef struct { /*!< (@ 0x40024000) CMP Structure */ + __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */ + __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */ +} LPC_CMP_TypeDef; +/*@}*/ /* end of group LPC8xx_CMP */ + + +/*------------- Wakeup Timer (WKT) --------------------------------------------------*/ +/** @addtogroup LPC8xx_WKT + @{ +*/ +typedef struct { /*!< (@ 0x40028000) WKT Structure */ + __IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */ + uint32_t Reserved[2]; + __IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */ +} LPC_WKT_TypeDef; +/*@}*/ /* end of group LPC8xx_WKT */ + + +/*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/ +typedef struct { +__IO uint32_t INTVAL; +__IO uint32_t TIMER; +__IO uint32_t CTRL; +__IO uint32_t STAT; +} MRT_Channel_cfg_Type; + +typedef struct { + MRT_Channel_cfg_Type Channel[4]; + uint32_t Reserved0[1]; + __IO uint32_t IDLE_CH; + __IO uint32_t IRQ_FLAG; +} LPC_MRT_TypeDef; + + +/*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/ +/** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter + @{ +*/ +/** + * @brief Product name title=LPC8xx MCU Chapter title=USART Modification date=4/18/2012 Major revision=0 Minor revision=9 (USART) + */ +typedef struct +{ + __IO uint32_t CFG; /* 0x00 */ + __IO uint32_t CTRL; + __IO uint32_t STAT; + __IO uint32_t INTENSET; + __O uint32_t INTENCLR; /* 0x10 */ + __I uint32_t RXDATA; + __I uint32_t RXDATA_STAT; + __IO uint32_t TXDATA; + __IO uint32_t BRG; /* 0x20 */ + __IO uint32_t INTSTAT; +} LPC_USART_TypeDef; + +/*@}*/ /* end of group LPC8xx_USART */ + + +/*------------- Synchronous Serial Interface Controller (SPI) -----------------------*/ +/** @addtogroup LPC8xx_SPI LPC8xx Synchronous Serial Port + @{ +*/ +typedef struct +{ + __IO uint32_t CFG; /* 0x00 */ + __IO uint32_t DLY; + __IO uint32_t STAT; + __IO uint32_t INTENSET; + __O uint32_t INTENCLR; /* 0x10 */ + __I uint32_t RXDAT; + __IO uint32_t TXDATCTL; + __IO uint32_t TXDAT; + __IO uint32_t TXCTRL; /* 0x20 */ + __IO uint32_t DIV; + __I uint32_t INTSTAT; +} LPC_SPI_TypeDef; +/*@}*/ /* end of group LPC8xx_SPI */ + + +/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ +/** @addtogroup LPC8xx_I2C I2C-Bus Interface + @{ +*/ +typedef struct +{ + __IO uint32_t CFG; /* 0x00 */ + __IO uint32_t STAT; + __IO uint32_t INTENSET; + __O uint32_t INTENCLR; + __IO uint32_t TIMEOUT; /* 0x10 */ + __IO uint32_t DIV; + __IO uint32_t INTSTAT; + uint32_t Reserved0[1]; + __IO uint32_t MSTCTL; /* 0x20 */ + __IO uint32_t MSTTIME; + __IO uint32_t MSTDAT; + uint32_t Reserved1[5]; + __IO uint32_t SLVCTL; /* 0x40 */ + __IO uint32_t SLVDAT; + __IO uint32_t SLVADR0; + __IO uint32_t SLVADR1; + __IO uint32_t SLVADR2; /* 0x50 */ + __IO uint32_t SLVADR3; + __IO uint32_t SLVQUAL0; + uint32_t Reserved2[9]; + __I uint32_t MONRXDAT; /* 0x80 */ +} LPC_I2C_TypeDef; + +/*@}*/ /* end of group LPC8xx_I2C */ + +/** + * @brief State Configurable Timer (SCT) (SCT) + */ + +/** + * @brief Product name title=UM10430 Chapter title=LPC8xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT) + */ + +#define CONFIG_SCT_nEV (6) /* Number of events */ +#define CONFIG_SCT_nRG (5) /* Number of match/compare registers */ +#define CONFIG_SCT_nOU (4) /* Number of outputs */ + +typedef struct +{ + __IO uint32_t CONFIG; /* 0x000 Configuration Register */ + union { + __IO uint32_t CTRL_U; /* 0x004 Control Register */ + struct { + __IO uint16_t CTRL_L; /* 0x004 low control register */ + __IO uint16_t CTRL_H; /* 0x006 high control register */ + }; + }; + __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */ + __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */ + __IO uint16_t HALT_L; /* 0x00C halt register for counter L */ + __IO uint16_t HALT_H; /* 0x00E halt register for counter H */ + __IO uint16_t STOP_L; /* 0x010 stop register for counter L */ + __IO uint16_t STOP_H; /* 0x012 stop register for counter H */ + __IO uint16_t START_L; /* 0x014 start register for counter L */ + __IO uint16_t START_H; /* 0x016 start register for counter H */ + uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */ + union { + __IO uint32_t COUNT_U; /* 0x040 counter register */ + struct { + __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */ + __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */ + }; + }; + __IO uint16_t STATE_L; /* 0x044 state register for counter L */ + __IO uint16_t STATE_H; /* 0x046 state register for counter H */ + __I uint32_t INPUT; /* 0x048 input register */ + __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */ + __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */ + __IO uint32_t OUTPUT; /* 0x050 output register */ + __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */ + __IO uint32_t RES; /* 0x058 conflict resolution register */ + uint32_t RESERVED2[37]; /* 0x05C-0x0EC reserved */ + __IO uint32_t EVEN; /* 0x0F0 event enable register */ + __IO uint32_t EVFLAG; /* 0x0F4 event flag register */ + __IO uint32_t CONEN; /* 0x0F8 conflict enable register */ + __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */ + + union { + __IO union { /* 0x100-... Match / Capture value */ + uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */ + struct { + uint16_t L; /* SCTMATCH[i].L Access to L value */ + uint16_t H; /* SCTMATCH[i].H Access to H value */ + }; + } MATCH[CONFIG_SCT_nRG]; + __I union { + uint32_t U; /* SCTCAP[i].U Unified 32-bit register */ + struct { + uint16_t L; /* SCTCAP[i].L Access to H value */ + uint16_t H; /* SCTCAP[i].H Access to H value */ + }; + } CAP[CONFIG_SCT_nRG]; + }; + + + uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */ + + union { + __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */ + __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */ + }; + uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */ + union { + __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */ + __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */ + }; + + uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */ + + + union { + __IO union { /* 0x200-... Match Reload / Capture Control value */ + uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */ + struct { + uint16_t L; /* SCTMATCHREL[i].L Access to L value */ + uint16_t H; /* SCTMATCHREL[i].H Access to H value */ + }; + } MATCHREL[CONFIG_SCT_nRG]; + __IO union { + uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */ + struct { + uint16_t L; /* SCTCAPCTRL[i].L Access to H value */ + uint16_t H; /* SCTCAPCTRL[i].H Access to H value */ + }; + } CAPCTRL[CONFIG_SCT_nRG]; + }; + + uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */ + + union { + __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */ + __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */ + }; + uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */ + union { + __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */ + __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */ + }; + uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */ + + __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/ + uint32_t STATE; /* Event State Register */ + uint32_t CTRL; /* Event Control Register */ + } EVENT[CONFIG_SCT_nEV]; + + uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */ + + __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */ + uint32_t SET; /* Output n Set Register */ + uint32_t CLR; /* Output n Clear Register */ + } OUT[CONFIG_SCT_nOU]; + + uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */ + + __I uint32_t MODULECONTENT; /* 0x7FC Module Content */ + +} LPC_SCT_TypeDef; +/*@}*/ /* end of group LPC8xx_SCT */ + + +/*------------- Watchdog Timer (WWDT) -----------------------------------------*/ +/** @addtogroup LPC8xx_WDT LPC8xx WatchDog Timer + @{ +*/ +typedef struct +{ + __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */ + __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */ + __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */ + __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */ + uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */ + __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */ + __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */ +} LPC_WWDT_TypeDef; +/*@}*/ /* end of group LPC8xx_WDT */ + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/* Base addresses */ +#define LPC_FLASH_BASE (0x00000000UL) +#define LPC_RAM_BASE (0x10000000UL) +#define LPC_ROM_BASE (0x1FFF0000UL) +#define LPC_APB0_BASE (0x40000000UL) +#define LPC_AHB_BASE (0x50000000UL) + +/* APB0 peripherals */ +#define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000) +#define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000) +#define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000) +#define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000) +#define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000) +#define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000) + +#define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000) +#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000) +#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000) +#define LPC_I2C_BASE (LPC_APB0_BASE + 0x50000) +#define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000) +#define LPC_SPI1_BASE (LPC_APB0_BASE + 0x5C000) +#define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000) +#define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000) +#define LPC_USART2_BASE (LPC_APB0_BASE + 0x6C000) + +/* AHB peripherals */ +#define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000) +#define LPC_SCT_BASE (LPC_AHB_BASE + 0x04000) + +#define LPC_GPIO_PORT_BASE (0xA0000000) +#define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000) + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +#define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE ) +#define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE ) + + +#define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE ) +#define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE ) +#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE ) +#define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE ) + +#define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE ) +#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) +#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE) +#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE ) +#define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE ) +#define LPC_SPI1 ((LPC_SPI_TypeDef *) LPC_SPI1_BASE ) +#define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE ) +#define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE ) +#define LPC_USART2 ((LPC_USART_TypeDef *) LPC_USART2_BASE ) + +#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE ) +#define LPC_SCT ((LPC_SCT_TypeDef *) LPC_SCT_BASE ) + +#define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE ) +#define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE ) + +#ifdef __cplusplus +} +#endif + +#endif /* __LPC8xx_H__ */ diff --git a/os/hal/platforms/LPC8xx/gpt_lld.c b/os/hal/platforms/LPC8xx/gpt_lld.c new file mode 100644 index 000000000..3504aeefe --- /dev/null +++ b/os/hal/platforms/LPC8xx/gpt_lld.c @@ -0,0 +1,282 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file LPC8xx/gpt_lld.c + * @brief LPC8xx GPT subsystem low level driver source. + * + * @addtogroup GPT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief GPT1 driver identifier. + * @note The driver GPT1 allocates MRT channel0 when enabled. + */ +#if LPC8xx_GPT_USE_MRT0 || defined(__DOXYGEN__) +GPTDriver GPTD1; +#endif + +/** + * @brief GPT2 driver identifier. + * @note The driver GPT1 allocates MRT channel1 when enabled. + */ +#if LPC8xx_GPT_USE_MRT1 || defined(__DOXYGEN__) +GPTDriver GPTD2; +#endif + +/** + * @brief GPT3 driver identifier. + * @note The driver GPT1 allocates MRT channel2 when enabled. + */ +#if LPC8xx_GPT_USE_MRT2 || defined(__DOXYGEN__) +GPTDriver GPTD3; +#endif + +/** + * @brief GPT4 driver identifier. + * @note The driver GPT1 allocates MRT channel3 when enabled. + */ +#if LPC8xx_GPT_USE_MRT3 || defined(__DOXYGEN__) +GPTDriver GPTD4; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ +static uint32_t clk_enabled; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ +/** + * @brief Shared IRQ handler. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @param[in] irq_flag irq flag bit + */ + +static void gpt_lld_serve_interrupt( GPTDriver *gptp ) { + + if (gptp->tmr->STAT & 0x01) { + gptp->tmr->STAT |= 0x01; + + if (gptp->state == GPT_ONESHOT) { + gptp->state = GPT_READY; /* Back in GPT_READY state. */ + } + gptp->config->callback(gptp); + } + return; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + + * @brief MRT IRQ handler. + * + */ +CH_IRQ_HANDLER(Vector68) { + CH_IRQ_PROLOGUE(); + +#if LPC8xx_GPT_USE_MRT0 + gpt_lld_serve_interrupt( &GPTD1 ); +#endif + +#if LPC8xx_GPT_USE_MRT1 + gpt_lld_serve_interrupt( &GPTD2 ); +#endif + +#if LPC8xx_GPT_USE_MRT2 + gpt_lld_serve_interrupt( &GPTD3 ); +#endif + +#if LPC8xx_GPT_USE_MRT3 + gpt_lld_serve_interrupt( &GPTD4 ); +#endif + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level GPT driver initialization. + * + * @notapi + */ +void gpt_lld_init(void) { + +#if LPC8xx_GPT_USE_MRT0 + GPTD1.tmr = &(LPC_MRT->Channel[0]); + gptObjectInit(&GPTD1); + GPTD1.mask = (1<<0); +#endif + +#if LPC8xx_GPT_USE_MRT1 + GPTD2.tmr = &(LPC_MRT->Channel[1]); + gptObjectInit(&GPTD2); + GPTD1.mask = (1<<1); +#endif + +#if LPC8xx_GPT_USE_MRT2 + GPTD3.tmr = &(LPC_MRT->Channel[2]); + gptObjectInit(&GPTD3); + GPTD1.mask = (1<<2); +#endif + +#if LPC8xx_GPT_USE_MRT3 + GPTD4.tmr = &(LPC_MRT->Channel[3]); + gptObjectInit(&GPTD4); + GPTD1.mask = (1<<3); +#endif + + clk_enabled = FALSE; + return; +} + +/** + * @brief Configures and activates a GPT channel. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_start(GPTDriver *gptp) { + + if( !clk_enabled ) { + + /* Enable clock & reset MRT */ + LPC_SYSCON->SYSAHBCLKCTRL |= (1<<10); + LPC_SYSCON->PRESETCTRL &= ~(1<<7); + LPC_SYSCON->PRESETCTRL |= (1<<7); + + nvicEnableVector(MRT_IRQn, + CORTEX_PRIORITY_MASK(LPC8xx_GPT_MRT_IRQ_PRIORITY)); + + clk_enabled |= gptp->mask; + } + + /* Prescaler value calculation.*/ + gptp->pr = (LPC8xx_SYSCLK / gptp->config->frequency); + chDbgAssert((gptp->pr * gptp->config->frequency) == LPC8xx_SYSCLK, + "gpt_lld_start(), #1", "invalid frequency"); + + /* MRT Channel configuration.*/ + gptp->tmr->CTRL = 0; + gptp->tmr->STAT |= 1; + +} + +/** + * @brief Deactivates a GPT channel. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop(GPTDriver *gptp) { + + /* Shared peripheral - + mark this channel as disabled */ + clk_enabled &= ~gptp->mask; + + /* All channels disabled? */ + if( !clk_enabled ) + { + /* Disable periheral */ + nvicDisableVector(MRT_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<10); + } + + return; +} + +/** + * @brief Starts the timer in continuous/One shot mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @notapi + */ +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->INTVAL = (1<<31)|((interval*gptp->pr) - 1); + + if (gptp->state == GPT_ONESHOT) + gptp->tmr->CTRL = (1<<1)|1; + else + gptp->tmr->CTRL = 1; +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop_timer(GPTDriver *gptp) { + + gptp->tmr->INTVAL = (1<<31); + gptp->tmr->CTRL = 0; + gptp->tmr->STAT |= 1; +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @notapi + */ +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->INTVAL = (1<<31)|((interval*gptp->pr) - 1); + gptp->tmr->CTRL = (1<<1); + + while (gptp->tmr->STAT & (1<<1)) + ; + + gptp->tmr->CTRL = 0; + gptp->tmr->STAT |= 1; +} + +#endif /* HAL_USE_GPT */ + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/gpt_lld.h b/os/hal/platforms/LPC8xx/gpt_lld.h new file mode 100644 index 000000000..208672096 --- /dev/null +++ b/os/hal/platforms/LPC8xx/gpt_lld.h @@ -0,0 +1,196 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file LPC8xx/gpt_lld.h + * @brief LPC8xx GPT subsystem low level driver header. + * + * @addtogroup GPT + * @{ + */ + +#ifndef _GPT_LLD_H_ +#define _GPT_LLD_H_ + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief GPT1 driver enable switch. + * @details If set to @p TRUE the support for GPT1 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC8xx_GPT_USE_MRT0) || defined(__DOXYGEN__) +#define LPC8xx_GPT_USE_MRT0 TRUE +#endif + +/** + * @brief GPT2 driver enable switch. + * @details If set to @p TRUE the support for GPT2 is included. + * @note The default is @p FALSE. + */ +#if !defined(LPC8xx_GPT_USE_MRT1) || defined(__DOXYGEN__) +#define LPC8xx_GPT_USE_MRT1 FALSE +#endif + +/** + * @brief GPT3 driver enable switch. + * @details If set to @p TRUE the support for GPT3 is included. + * @note The default is @p FALSE. + */ +#if !defined(LPC8xx_GPT_USE_MRT2) || defined(__DOXYGEN__) +#define LPC8xx_GPT_USE_MRT2 FALSE +#endif + +/** + * @brief GPT4 driver enable switch. + * @details If set to @p TRUE the support for GPT4 is included. + * @note The default is @p FALSE. + */ +#if !defined(LPC8xx_GPT_USE_MRT3) || defined(__DOXYGEN__) +#define LPC8xx_GPT_USE_MRT3 FALSE +#endif + +/** + * @brief GPT interrupt priority level setting. + */ +#if !defined(LPC8xx_GPT_MRT_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC8xx_GPT_MRT_IRQ_PRIORITY 2 +#endif + + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !LPC8xx_GPT_USE_MRT0 && !LPC8xx_GPT_USE_MRT1 && \ + !LPC8xx_GPT_USE_MRT2 && !LPC8xx_GPT_USE_MRT3 +#error "GPT driver activated but no CT peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief GPT frequency type. + */ +typedef uint32_t gptfreq_t; + +/** + * @brief GPT counter type. + */ +typedef uint32_t gptcnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + gptfreq_t frequency; + /** + * @brief Timer callback pointer. + * @note This callback is invoked on GPT counter events. + */ + gptcallback_t callback; + /* End of the mandatory fields.*/ +} GPTConfig; + +/** + * @brief Structure representing a GPT driver. + */ +struct GPTDriver { + /** + * @brief Driver state. + */ + gptstate_t state; + /** + * @brief Current configuration data. + */ + const GPTConfig *config; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the MRT Channelx registers block. + */ + MRT_Channel_cfg_Type *tmr; + /** + * @brief Prescaler. + */ + uint32_t pr; + /** + * @brief channel bitmask. + */ + uint32_t mask; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC8xx_GPT_USE_MRT0 && !defined(__DOXYGEN__) +extern GPTDriver GPTD1; +#endif + +#if LPC8xx_GPT_USE_MRT1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD2; +#endif + +#if LPC8xx_GPT_USE_MRT2 && !defined(__DOXYGEN__) +extern GPTDriver GPTD3; +#endif + +#if LPC8xx_GPT_USE_MRT3 && !defined(__DOXYGEN__) +extern GPTDriver GPTD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void gpt_lld_init(void); + void gpt_lld_start(GPTDriver *gptp); + void gpt_lld_stop(GPTDriver *gptp); + void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); + void gpt_lld_stop_timer(GPTDriver *gptp); + void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT */ + +#endif /* _GPT_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/hal_lld.c b/os/hal/platforms/LPC8xx/hal_lld.c new file mode 100644 index 000000000..52c12aca0 --- /dev/null +++ b/os/hal/platforms/LPC8xx/hal_lld.c @@ -0,0 +1,145 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file LPC8xx/hal_lld.c + * @brief LPC8xx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* SysTick initialization using the system clock.*/ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, CORTEX_PRIORITY_SYSTICK); + SysTick->LOAD = LPC8xx_SYSCLK / CH_FREQUENCY - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief LPC8xx clocks and PLL initialization. + * @note This function must be invoked only after the system reset. + * + * @special + */ +void lpc8xx_clock_init(void) { + int i; + + /* Enable clocks to IOCON & SWM. */ + LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<18)|(1<<7)); + + /* System oscillator initialization.*/ +#if (LPC8xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) + // switch off pull-ups + LPC_IOCON->PIO0_8 &= ~(3<<3); + LPC_IOCON->PIO0_9 &= ~(3<<3); + + // enable xtalin/xtalout + LPC_SWM->PINENABLE0 &= ~(3<<4); + + LPC_SYSCON->SYSOSCCTRL = LPC8xx_SYSOSCCTRL; + LPC_SYSCON->PDRUNCFG &= ~(1<<5); /* System oscillator ON. */ + for (i = 0; i<200; i++) + __NOP(); /* Stabilization delay. */ +#endif + + /* CLKIN initialization.*/ +#if (LPC8xx_PLLCLK_SOURCE == SYSPLLCLKSEL_CLKIN) + // switch off pull-up + LPC_IOCON->PIO0_1 &= ~(3<<3); + + // enable clkin + LPC_SWM->PINENABLE0 &= ~(1<<7); +#endif + + /* Always set PLL clock source - + PLL IN can be a main clock source */ + LPC_SYSCON->SYSPLLCLKSEL = LPC8xx_PLLCLK_SOURCE; + LPC_SYSCON->SYSPLLCLKUEN = 1; + while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */ + + /* PLL initialization.*/ +#if LPC8xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT + LPC_SYSCON->SYSPLLCTRL = LPC8xx_SYSPLLCTRL_MSEL | LPC8xx_SYSPLLCTRL_PSEL; + LPC_SYSCON->PDRUNCFG &= ~(1<<7); /* System PLL ON. */ + while (!(LPC_SYSCON->SYSPLLSTAT & 1)) /* Wait PLL lock. */ + ; +#endif + +#if LPC8xx_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC +#error "WatchDog Oscillator not configured! Dont use as main clock source" + LPC_SYSCON->WDTOSCCTRL = ??; + LPC_SYSCON->PDRUNCFG &= ~(1<<6); /* WDT OSC On */ + for (i = 0; i<200; i++) + __NOP(); /* Stabilization delay. */ +#endif + + /* Flash wait states setting, the code takes care to not touch TBD bits.*/ + LPC_FLASHCTRL->FLASHCFG = (LPC_FLASHCTRL->FLASHCFG & ~1) | + LPC8xx_FLASHCFG_FLASHTIM; + + /* ABH divider initialization. Set this **before** switching Main clock + source to ensure AHB clock stays in spec */ + LPC_SYSCON->SYSAHBCLKDIV = LPC8xx_SYSABHCLK_DIV; + + + /* Main clock source selection.*/ + LPC_SYSCON->MAINCLKSEL = LPC8xx_MAINCLK_SOURCE; + LPC_SYSCON->MAINCLKUEN = 1; + while (!(LPC_SYSCON->MAINCLKUEN & 1)); /* Wait switch completion. */ + + /* Disable clocks to IOCON, SWM, FLASHREG & ROM. */ + LPC_SYSCON->SYSAHBCLKCTRL &= ~((1<<18)|(1<<7)|(1<<3)|(1<<1)); + +} + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/hal_lld.h b/os/hal/platforms/LPC8xx/hal_lld.h new file mode 100644 index 000000000..ca7cccd5a --- /dev/null +++ b/os/hal/platforms/LPC8xx/hal_lld.h @@ -0,0 +1,225 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file LPC8xx/hal_lld.h + * @brief HAL subsystem low level driver header template. + * + * @addtogroup HAL + * @{ + */ + +#ifndef _HAL_LLD_H_ +#define _HAL_LLD_H_ + +#include "LPC8xx.h" +#include "nvic.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @brief Platform name. + */ +#define PLATFORM_NAME "LPC8xx" + +#define IRCOSCCLK 12000000 /**< High speed internal clock. */ +#define WDGOSCCLK ??????? /**< Watchdog internal clock. */ + +#define SYSPLLCLKSEL_IRCOSC 0 /**< Internal RC oscillator + clock source. */ +#define SYSPLLCLKSEL_SYSOSC 1 /**< System oscillator clock + source. */ +#define SYSPLLCLKSEL_CLKIN 3 /**< External CLKIN clock + source. */ + +#define SYSMAINCLKSEL_IRCOSC 0 /**< Clock source is IRC. */ +#define SYSMAINCLKSEL_PLLIN 1 /**< Clock source is PLLIN. */ +#define SYSMAINCLKSEL_WDGOSC 2 /**< Clock source is WDGOSC. */ +#define SYSMAINCLKSEL_PLLOUT 3 /**< Clock source is PLLOUT. */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief System PLL clock source. + */ +#if !defined(LPC8xx_PLLCLK_SOURCE) || defined(__DOXYGEN__) +#define LPC8xx_PLLCLK_SOURCE SYSPLLCLKSEL_IRCOSC +#endif + +/** + * @brief System PLL multiplier. + * @note The value must be in the 1..32 range and the final frequency + * must not exceed the CCO ratings. + */ +#if !defined(LPC8xx_SYSPLL_MUL) || defined(__DOXYGEN__) +#define LPC8xx_SYSPLL_MUL 4 +#endif + +/** + * @brief System PLL divider. + * @note The value must be chosen between (2, 4, 8, 16). + */ +#if !defined(LPC8xx_SYSPLL_DIV) || defined(__DOXYGEN__) +#define LPC8xx_SYSPLL_DIV 4 +#endif + +/** + * @brief System main clock source. + */ +#if !defined(LPC8xx_MAINCLK_SOURCE) || defined(__DOXYGEN__) +#define LPC8xx_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#endif + +/** + * @brief AHB clock divider. + * @note The value must be chosen between (1...255). + */ +#if !defined(LPC8xx_SYSABHCLK_DIV) || defined(__DOXYGEN__) +#define LPC8xx_SYSABHCLK_DIV 1 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** + * @brief Calculated SYSOSCCTRL setting. + */ +#if (SYSOSCCLK < 18000000) || defined(__DOXYGEN__) +#define LPC8xx_SYSOSCCTRL 0 +#else +#define LPC8xx_SYSOSCCTRL 2 +#endif + +/** + * @brief PLL input clock frequency. + */ +#if (LPC8xx_PLLCLK_SOURCE == SYSPLLCLKSEL_SYSOSC) || defined(__DOXYGEN__) +#define LPC8xx_SYSPLLCLKIN SYSOSCCLK +#elif LPC8xx_PLLCLK_SOURCE == SYSPLLCLKSEL_IRCOSC +#define LPC8xx_SYSPLLCLKIN IRCOSCCLK +#elif LPC8xx_PLLCLK_SOURCE == SYSPLLCLKSEL_CLKIN +#define LPC8xx_SYSPLLCLKIN CLKINCLK +#else +#error "invalid LPC8xx_PLLCLK_SOURCE clock source specified" +#endif + +/** + * @brief MSEL mask in SYSPLLCTRL register. + */ +#if (LPC8xx_SYSPLL_MUL >= 1) && (LPC8xx_SYSPLL_MUL <= 32) || \ + defined(__DOXYGEN__) +#define LPC8xx_SYSPLLCTRL_MSEL (LPC8xx_SYSPLL_MUL - 1) +#else +#error "LPC8xx_SYSPLL_MUL out of range (1...32)" +#endif + +/** + * @brief PSEL mask in SYSPLLCTRL register. + */ +#if (LPC8xx_SYSPLL_DIV == 2) || defined(__DOXYGEN__) +#define LPC8xx_SYSPLLCTRL_PSEL (0 << 5) +#elif LPC8xx_SYSPLL_DIV == 4 +#define LPC8xx_SYSPLLCTRL_PSEL (1 << 5) +#elif LPC8xx_SYSPLL_DIV == 8 +#define LPC8xx_SYSPLLCTRL_PSEL (2 << 5) +#elif LPC8xx_SYSPLL_DIV == 16 +#define LPC8xx_SYSPLLCTRL_PSEL (3 << 5) +#else +#error "invalid LPC8xx_SYSPLL_DIV value (2,4,8,16)" +#endif + +/** + * @brief CCO frequency. + */ +#define LPC8xx_SYSPLLCCO (LPC8xx_SYSPLLCLKIN * LPC8xx_SYSPLL_MUL * \ + LPC8xx_SYSPLL_DIV) + +#if (LPC8xx_SYSPLLCCO < 156000000) || (LPC8xx_SYSPLLCCO > 320000000) +#error "CCO frequency out of the acceptable range (156...320MHz)" +#endif + +/** + * @brief PLL output clock frequency. + */ +#define LPC8xx_SYSPLLCLKOUT (LPC8xx_SYSPLLCCO / LPC8xx_SYSPLL_DIV) + +#if (LPC8xx_MAINCLK_SOURCE == SYSMAINCLKSEL_IRCOSC) || defined(__DOXYGEN__) +#define LPC8xx_MAINCLK IRCOSCCLK +#elif LPC8xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLIN +#define LPC8xx_MAINCLK LPC8xx_SYSPLLCLKIN +#elif LPC8xx_MAINCLK_SOURCE == SYSMAINCLKSEL_WDGOSC +#define LPC8xx_MAINCLK WDGOSCCLK +#elif LPC8xx_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT +#define LPC8xx_MAINCLK LPC8xx_SYSPLLCLKOUT +#else +#error "invalid LPC8xx_MAINCLK_SOURCE clock source specified" +#endif + +/** + * @brief AHB clock. + */ +#define LPC8xx_SYSCLK (LPC8xx_MAINCLK / LPC8xx_SYSABHCLK_DIV) +#if LPC8xx_SYSCLK > 30000000 +#error "AHB clock frequency out of the acceptable range (30MHz max)" +#endif + +/** + * @brief Flash wait states. + */ +#if (LPC8xx_SYSCLK <= 20000000) || defined(__DOXYGEN__) +#define LPC8xx_FLASHCFG_FLASHTIM 0 +#else +#define LPC8xx_FLASHCFG_FLASHTIM 1 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void lpc8xx_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/pal_lld.c b/os/hal/platforms/LPC8xx/pal_lld.c new file mode 100644 index 000000000..50bf20870 --- /dev/null +++ b/os/hal/platforms/LPC8xx/pal_lld.c @@ -0,0 +1,109 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file LPC8xx/pal_lld.c + * @brief LPC8xx GPIO low level driver code. + * + * @addtogroup PAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ +/** + * @brief LPC8xx I/O ports configuration. + * @details GPIO unit registers initialization. + * + * @param[in] config the LPC11xx ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) { + + /* Enable clocks to GPIO */ + LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6); + + LPC_GPIO_PORT->DIR0 = config->dir; + LPC_GPIO_PORT->PIN0 = config->data; +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note @p PAL_MODE_UNCONNECTED is implemented as push pull output with + * high state. + * @note This function does not alter the @p PINSELx registers. Alternate + * functions setup must be handled by device-specific code. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + switch (mode) + { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + port->DIR0 &= ~mask; + break; + + case PAL_MODE_UNCONNECTED: + palSetPort(port, PAL_WHOLE_PORT); + //no break + case PAL_MODE_OUTPUT_PUSHPULL: + port->DIR0 |= mask; + break; + } + + return; +} + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/pal_lld.h b/os/hal/platforms/LPC8xx/pal_lld.h new file mode 100644 index 000000000..fd3cc6a04 --- /dev/null +++ b/os/hal/platforms/LPC8xx/pal_lld.h @@ -0,0 +1,294 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file LPC8xx/pal_lld.h + * @brief LPC8xx GPIO low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef _PAL_LLD_H_ +#define _PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +/** + * @brief GPIO port setup info. + */ + +/** + * @brief GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + * @note The @p IOCON block is not configured, initially all pins have + * enabled pullups and are programmed as GPIO. It is responsibility + * of the various drivers to reprogram the pins in the proper mode. + * Pins that are not handled by any driver may be programmed in + * @p board.c. + */ +typedef struct { + /** Initial value for FIO_PIN register.*/ + uint32_t data; + /** Initial value for FIO_DIR register.*/ + uint32_t dir; +} PALConfig; + +/** + * @brief Width, in bits, of the I/O port. + */ +#define PAL_IOPORTS_WIDTH 32 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0x3FFFF) + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + */ +typedef LPC_GPIO_PORT_TypeDef *ioportid_t; + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief GPIO0 port identifier. + */ +#define IOPORT1 LPC_GPIO_PORT +#define GPIO0 LPC_GPIO_PORT + + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->PIN0) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->SET0) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->PIN0 = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) ((port)->SET0 = (bits)) + +/** + * @brief Clears a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) ((port)->CLR0 = (bits)) + + +/** + * @brief Toggles a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + + * + * @param[in] port port identifier + * @param[in] bits bits to be XORed on the specified port + * + * @api + */ +#define pal_lld_toggleport(port, bits) ((port)->NOT0 = (bits)) + + +/** + * @brief Writes a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group width + * are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + (port)->MASK0 = (~(mask) << (offset)); \ + (port)->MPIN0 = ((bits) << (offset)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Writes a logical state on an output pad. + * @note This function is not meant to be invoked directly by the + * application code. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) \ + ((port)->W0[(pad)] = (bit)) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) \ + ((port)->W0[(pad)] = 1) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) \ + ((port)->W0[(pad)] = 0) + +#if !defined(__DOXYGEN__) +extern const PALConfig pal_default_config; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* _PAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/platform.dox b/os/hal/platforms/LPC8xx/platform.dox new file mode 100644 index 000000000..3b479ba91 --- /dev/null +++ b/os/hal/platforms/LPC8xx/platform.dox @@ -0,0 +1,108 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @defgroup LPC8xx LPC8xx Drivers + * @details This section describes all the supported drivers on the LPC8xx + * platform and the implementation details of the single drivers. + * + * @ingroup platforms + */ + +/** + * @defgroup LPC8xx_HAL LPC8xx Initialization Support + * @details The LPC8xx HAL support is responsible for system initialization. + * + * @section lpc8xx_hal_1 Supported HW resources + * - SYSCON. + * - Flash. + * . + * @section lpc8xx_hal_2 LPC8xx HAL driver implementation features + * - Clock tree initialization. + * - Clock source selection. + * - Flash controller initialization. + * - SYSTICK initialization based on current clock and kernel required rate. + * . + * @ingroup LPC8xx + */ + +/** + * @defgroup LPC8xx_GPT LPC8xx GPT Support + * @details The LPC8xx GPT driver uses the MRT peripheral. + * + * @section lpc8xx_gpt_1 Supported HW resources + * - MRT. + * . + * @section lpc8xx_gpt_2 LPC8xx GPT driver implementation features + * - Each timer can be independently enabled and programmed. + * - Programmable MRT interrupt priority level. + * . + * @ingroup LPC8xx + */ + +/** + * @defgroup LPC8xx_PAL LPC8xx PAL Support + * @details The LPC8xx PAL driver uses the GPIO peripheral. + * + * @section lpc8xx_pal_1 Supported HW resources + * - GPIO_PORT. + * . + * @section lpc8xx_pal_2 LPC8xx PAL driver implementation features + * - 18 bits wide ports. + * - Atomic set/reset functions. + * - Atomic Toggle functions. + * - Atomic set+reset function (atomic bus operations). + * - Output latched regardless of the pad setting. + * - Direct read of input pads regardless of the pad setting. + * . + * @section lpc8xx_pal_3 Supported PAL setup modes + * - @p PAL_MODE_RESET. + * - @p PAL_MODE_UNCONNECTED. + * - @p PAL_MODE_INPUT. + * - @p PAL_MODE_OUTPUT_PUSHPULL. + * . + * Any attempt to setup an invalid mode is ignored. + * + * @section lpc8xx_pal_4 Suboptimal behavior + * Some GPIO features are less than optimal: + * - Group operations are not atomic. + * - Pull-up and Pull-down resistors cannot be programmed through the PAL + * driver and must be programmed separately using the IOCON peripheral. + * . + * @ingroup LPC8xx + */ + +/** + * @defgroup LPC8xx_SERIAL LPC8xx Serial Support + * @details The LPC8xx Serial driver uses the UART peripheral in a + * buffered, interrupt driven, implementation. + * + * @section lpc8xx_serial_1 Supported HW resources + * The serial driver can support any of the following hardware resources: + * - UART. + * . + * @section lpc8xx_serial_2 LPC8xx Serial driver implementation features + * - Clock stop for reduced power usage when the driver is in stop state. + * - Fully interrupt driven. + * - Programmable priority level. + * . + * @ingroup LPC8xx + */ + diff --git a/os/hal/platforms/LPC8xx/platform.mk b/os/hal/platforms/LPC8xx/platform.mk new file mode 100644 index 000000000..3818f1021 --- /dev/null +++ b/os/hal/platforms/LPC8xx/platform.mk @@ -0,0 +1,8 @@ +# List of all the LPC8xx platform files. +PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC8xx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC8xx/gpt_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC8xx/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC8xx/serial_lld.c + +# Required include directories +PLATFORMINC = ${CHIBIOS}/os/hal/platforms/LPC8xx diff --git a/os/hal/platforms/LPC8xx/serial_lld.c b/os/hal/platforms/LPC8xx/serial_lld.c new file mode 100644 index 000000000..e5937bae8 --- /dev/null +++ b/os/hal/platforms/LPC8xx/serial_lld.c @@ -0,0 +1,354 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file LPC8xx/serial_lld.c + * @brief LPC8xx low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if LPC8xx_SERIAL_USE_UART0 || defined(__DOXYGEN__) +/** @brief UART0 serial driver identifier.*/ +SerialDriver SD1; +#endif + +#if LPC8xx_SERIAL_USE_UART1 || defined(__DOXYGEN__) +/** @brief UART1 serial driver identifier.*/ +SerialDriver SD2; +#endif + +#if LPC8xx_SERIAL_USE_UART2 || defined(__DOXYGEN__) +/** @brief UART2 serial driver identifier.*/ +SerialDriver SD3; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** @brief Driver default configuration.*/ +static const SerialConfig default_config = { + SERIAL_DEFAULT_BITRATE, + (CFG_DL8 | CFG_NOPARITY | CFG_STOP1) +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Error handling routine. + * + * @param[in] sdp communication channel associated to the UART + * @param[in] err UART STAT register value + */ +static void set_error(SerialDriver *sdp, IOREG32 err) { + flagsmask_t sts = 0; + + if (err & STAT_OVERRUN) + sts |= SD_OVERRUN_ERROR; + if (err & STAT_PARITYERR) + sts |= SD_PARITY_ERROR; + if (err & STAT_FRAMERR) + sts |= SD_FRAMING_ERROR; + if (err & STAT_RXBRK) + sts |= SD_BREAK_DETECTED; + + chSysLockFromIsr(); + chnAddFlagsI(sdp, sts); + chSysUnlockFromIsr(); +} + +/** + * @brief Common IRQ handler. + * @note Tries hard to clear all the pending interrupt sources, we don't + * want to go through the whole ISR and have another interrupt soon + * after. + * + * @param[in] u pointer to an UART I/O block + * @param[in] sdp communication channel associated to the UART + */ +static void serve_interrupt(SerialDriver *sdp) { + LPC_USART_TypeDef *u = sdp->uart; + + while (u->INTSTAT) { + + if (u->INTSTAT & STAT_RXRDY) { + chSysLockFromIsr(); + if (chIQIsEmptyI(&sdp->iqueue)) + chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE); + if (chIQPutI(&sdp->iqueue, u->RXDATA) < Q_OK) + chnAddFlagsI(sdp, SD_OVERRUN_ERROR); + chSysUnlockFromIsr(); + } + + if (u->INTSTAT & STAT_TXRDY) { + msg_t b; + + chSysLockFromIsr(); + b = chOQGetI(&sdp->oqueue); + chSysUnlockFromIsr(); + + if (b < Q_OK) { + u->INTENCLR = STAT_TXRDY; + chSysLockFromIsr(); + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + chSysUnlockFromIsr(); + break; + } + else { + u->TXDATA = b; + } + } + + if (u->INTSTAT & (STAT_OVERRUN | STAT_DELTARXBRK | + STAT_FRAMERR | STAT_PARITYERR) ) { + set_error(sdp, u->STAT); + } + + } +} + +/** + * @brief Attempts a TX preload. + */ +static void preload(SerialDriver *sdp) { + LPC_USART_TypeDef *u = sdp->uart; + + if (u->STAT & STAT_TXIDLE) { + msg_t b = chOQGetI(&sdp->oqueue); + if (b < Q_OK) { + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + return; + } + u->TXDATA = b; + } + u->INTENSET = STAT_TXRDY; +} + +/** + * @brief Driver output notification. + */ +#if LPC8xx_SERIAL_USE_UART0 || defined(__DOXYGEN__) +static void notify1(GenericQueue *qp) { + + (void)qp; + preload(&SD1); +} +#endif + +#if LPC8xx_SERIAL_USE_UART1 || defined(__DOXYGEN__) +static void notify2(GenericQueue *qp) { + + (void)qp; + preload(&SD2); +} +#endif + +#if LPC8xx_SERIAL_USE_UART2 || defined(__DOXYGEN__) +static void notify3(GenericQueue *qp) { + + (void)qp; + preload(&SD3); +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief UARTn IRQ handlers. + * + * @isr + */ +#if LPC8xx_SERIAL_USE_UART0 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(Vector4C) { + + CH_IRQ_PROLOGUE(); + serve_interrupt( &SD1 ); + CH_IRQ_EPILOGUE(); +} +#endif +#if LPC8xx_SERIAL_USE_UART1 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(Vector50) { + + CH_IRQ_PROLOGUE(); + serve_interrupt( &SD2 ); + CH_IRQ_EPILOGUE(); +} +#endif +#if LPC8xx_SERIAL_USE_UART2 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(Vector54) { + + CH_IRQ_PROLOGUE(); + serve_interrupt( &SD3 ); + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + * + * @notapi + */ +void sd_lld_init(void) { + +#if LPC8xx_SERIAL_USE_UART0 + sdObjectInit(&SD1, NULL, notify1); + SD1.uart = LPC_USART0; +#endif + +#if LPC8xx_SERIAL_USE_UART1 + sdObjectInit(&SD2, NULL, notify2); + SD2.uart = LPC_USART1; +#endif + +#if LPC8xx_SERIAL_USE_UART2 + sdObjectInit(&SD3, NULL, notify3); + SD3.uart = LPC_USART2; +#endif + + /* Reset fractional baudrate generator */ + LPC_SYSCON->PRESETCTRL &= ~(1<<2); + LPC_SYSCON->PRESETCTRL |= (1<<2); + + LPC_SYSCON->UARTCLKDIV = LPC8xx_SERIAL_UARTCLKDIV; + LPC_SYSCON->UARTFRGDIV = LPC8xx_SERIAL_UARTFRGDIV; + LPC_SYSCON->UARTFRGMULT = LPC8xx_SERIAL_UARTFRGMULT; + +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + * + * @notapi + */ +void sd_lld_start( SerialDriver *sdp, const SerialConfig *config ) { + + if (config == NULL) + config = &default_config; + + if (sdp->state == SD_STOP) { + +#if LPC8xx_SERIAL_USE_UART0 + if (&SD1 == sdp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1<<14); // Enable Clk + LPC_SYSCON->PRESETCTRL &= ~(1<<3); // Reset peripheral + LPC_SYSCON->PRESETCTRL |= (1<<3); + nvicEnableVector(UART0_IRQn, + CORTEX_PRIORITY_MASK(LPC8xx_SERIAL_UART0_IRQ_PRIORITY)); + } +#endif + +#if LPC8xx_SERIAL_USE_UART1 + if (&SD2 == sdp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1<<15); // Enable Clk + LPC_SYSCON->PRESETCTRL &= ~(1<<4); // Reset peripheral + LPC_SYSCON->PRESETCTRL |= (1<<4); + nvicEnableVector(UART1_IRQn, + CORTEX_PRIORITY_MASK(LPC8xx_SERIAL_UART1_IRQ_PRIORITY)); + } +#endif + +#if LPC8xx_SERIAL_USE_UART2 + if (&SD3 == sdp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1<<16); // Enable Clk + LPC_SYSCON->PRESETCTRL &= ~(1<<5); // Reset peripheral + LPC_SYSCON->PRESETCTRL |= (1<<5); + nvicEnableVector(UART2_IRQn, + CORTEX_PRIORITY_MASK(LPC8xx_SERIAL_UART2_IRQ_PRIORITY)); + } +#endif + + } + + sdp->uart->BRG = (LPC8xx_SERIAL_U_PCLK / (config->sc_speed << 4)) -1; + sdp->uart->INTENSET = STAT_FRAMERR | STAT_OVERRUN | + STAT_PARITYERR | STAT_DELTARXBRK | + STAT_RXRDY; + sdp->uart->CFG = config->sc_cfg | CFG_ENA; +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the UART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + * + * @notapi + */ +void sd_lld_stop( SerialDriver *sdp ) { + + if (sdp->state == SD_READY) { + sdp->uart->INTENCLR = STAT_TXRDY | STAT_RXRDY; + sdp->uart->CFG = 0; + +#if LPC8xx_SERIAL_USE_UART0 + if (&SD1 == sdp) { + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<12); + nvicDisableVector(UART0_IRQn); + return; + } +#endif + +#if LPC8xx_SERIAL_USE_UART1 + if (&SD2 == sdp) { + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<13); + nvicDisableVector(UART1_IRQn); + return; + } +#endif + +#if LPC8xx_SERIAL_USE_UART2 + if (&SD3 == sdp) { + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1<<14); + nvicDisableVector(UART2_IRQn); + return; + } +#endif + + } +} + +#endif /* HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/serial_lld.h b/os/hal/platforms/LPC8xx/serial_lld.h new file mode 100644 index 000000000..f43c6af6d --- /dev/null +++ b/os/hal/platforms/LPC8xx/serial_lld.h @@ -0,0 +1,273 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file LPC8xx/serial_lld.h + * @brief LPC8xx low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef _SERIAL_LLD_H_ +#define _SERIAL_LLD_H_ + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define CFG_ENA 0x0001 +#define CFG_DL7 0x0000 +#define CFG_DL8 0x0004 +#define CFG_DL9 0x0008 +#define CFG_NOPARITY 0x0000 +#define CFG_PARITYEVEN 0x0020 +#define CFG_PARITYODD 0x0030 +#define CFG_STOP1 0x0000 +#define CFG_STOP2 0x0040 +#define CFG_CTSEN 0x0200 +#define CFG_SYNCEN 0x0800 +#define CFG_CLKPOL_FALL 0x0000 +#define CFG_CLKPOL_RISE 0x1000 +#define CFG_SYNC_SLV 0x0000 +#define CFG_SYNC_MAST 0x4000 +#define CFG_LOOP_EN 0x8000 + +#define CTRL_TXBRKEN 0x0002 +#define CTRL_ADDRDET 0x0004 +#define CTRL_TXDIS 0x0040 +#define CTRL_CC 0x0100 +#define CTRL_CLRCC 0x0200 + +#define STAT_RXRDY 0x0001 +#define STAT_RXIDLE 0x0002 +#define STAT_TXRDY 0x0004 +#define STAT_TXIDLE 0x0008 +#define STAT_CTS 0x0010 +#define STAT_DELTACTS 0x0020 +#define STAT_TXDIS 0x0040 +#define STAT_OVERRUN 0x0100 +#define STAT_RXBRK 0x0400 +#define STAT_DELTARXBRK 0x0800 +#define STAT_START 0x1000 +#define STAT_FRAMERR 0x2000 +#define STAT_PARITYERR 0x4000 +#define STAT_RXNOISE 0x8000 + + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief UART0 driver enable switch. + * @details If set to @p TRUE the support for UART0 is included. + * @note The default is @p TRUE . + */ +#if !defined(LPC8xx_SERIAL_USE_UART0) || defined(__DOXYGEN__) +#define LPC8xx_SERIAL_USE_UART0 TRUE +#endif + +/** + * @brief UART1 driver enable switch. + * @details If set to @p TRUE the support for UART1 is included. + * @note The default is @p FALSE . + */ +#if !defined(LPC8xx_SERIAL_USE_UART1) || defined(__DOXYGEN__) +#define LPC8xx_SERIAL_USE_UART1 FALSE +#endif + +/** + * @brief UART2 driver enable switch. + * @details If set to @p TRUE the support for UART2 is included. + * @note The default is @p FALSE . + */ +#if !defined(LPC8xx_SERIAL_USE_UART2) || defined(__DOXYGEN__) +#define LPC8xx_SERIAL_USE_UART2 FALSE +#endif + +/** + * @brief UART0 interrupt priority level setting. + */ +#if !defined(LPC8xx_SERIAL_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC8xx_SERIAL_UART0_IRQ_PRIORITY 3 +#endif + +/** + * @brief UART1 interrupt priority level setting. + */ +#if !defined(LPC8xx_SERIAL_UART1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC8xx_SERIAL_UART1_IRQ_PRIORITY 3 +#endif + +/** + * @brief UART2 interrupt priority level setting. + */ +#if !defined(LPC8xx_SERIAL_UART2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC8xx_SERIAL_UART2_IRQ_PRIORITY 3 +#endif + + +/** + * @brief Uart Baud Clock (U_PCLK). + * @details The Baud clock rate we would like to achieve. + * @note The default is @p 11.0592MHz. + * A multiple of 1.8432MHz will give accurate + * results at all standard baud rates . + */ +#if !defined(LPC8xx_SERIAL_U_PCLK) || defined(__DOXYGEN__) +#define LPC8xx_SERIAL_U_PCLK 11059200 +#endif + +/** + * @brief UARTCLKDIV divider. + */ +#if !defined(LPC8xx_SERIAL_UARTCLKDIV) || defined(__DOXYGEN__) +#define LPC8xx_SERIAL_UARTCLKDIV (LPC8xx_MAINCLK/LPC8xx_SERIAL_U_PCLK) +#endif + +// Output from uart clock divider +#define LPC8xx_UARTDIVCLK (LPC8xx_MAINCLK/LPC8xx_SERIAL_UARTCLKDIV) + +/** + * @brief UARTFRGDIV + * @details Fractional Baud rate generator denominator. + * @note If used, *must* be set to 256, otherwise set to 0 + */ +#if !defined(LPC8xx_SERIAL_UARTFRGDIV) || defined(__DOXYGEN__) + #if (LPC8xx_SERIAL_UARTCLKDIV != LPC8xx_SERIAL_U_PCLK) + #define LPC8xx_SERIAL_UARTFRGDIV 0xFF + #else + #define LPC8xx_SERIAL_UARTFRGDIV 0x00 + #endif +#endif + +/** + * @brief UARTFRGMUL + * @details Fractional Baud rate generator numerator. + * Refer to LPC8xx User Manual 4.6.19 for calculation + * @note the *2, +1 and /2 are included to round to the nearest integer. + */ +#if !defined(LPC8xx_SERIAL_UARTFRGMUL) || defined(__DOXYGEN__) + #if (LPC8xx_SERIAL_UARTCLKDIV != LPC8xx_SERIAL_U_PCLK) + #define LPC8xx_SERIAL_UARTFRGMULT ( ( ( ( (LPC8xx_UARTDIVCLK- \ + LPC8xx_SERIAL_U_PCLK) \ + *256*2 ) \ + /LPC8xx_SERIAL_U_PCLK ) \ + +1 ) \ + /2 ) + + #else + #define LPC8xx_SERIAL_UARTFRGMULT 0x00 + #endif +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (LPC8xx_SERIAL_UARTCLKDIV < 1) || (LPC8xx_SERIAL_UARTCLKDIV > 255) +#error "invalid LPC8xx_SERIAL_UARTCLKDIV setting" +#endif + +#if (LPC8xx_SERIAL_UARTFRGDIV != 0) && (LPC8xx_SERIAL_UARTFRGDIV != 255) +#error "invalid LPC8xx_SERIAL_UARTFRGDIV setting" +#endif + +#if (LPC8xx_SERIAL_UARTFRGMUL != 0) && (LPC8xx_SERIAL_UARTFRGMUL > 255) +#error "invalid LPC8xx_SERIAL_UARTFRGMUL setting" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief LPC8xx Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t sc_speed; + /** + * @brief Initialization value for the CFG register. + */ + uint32_t sc_cfg; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + InputQueue iqueue; \ + /* Output queue.*/ \ + OutputQueue oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the USART registers block.*/ \ + LPC_USART_TypeDef *uart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC8xx_SERIAL_USE_UART0 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif + +#if LPC8xx_SERIAL_USE_UART1 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif + +#if LPC8xx_SERIAL_USE_UART2 && !defined(__DOXYGEN__) +extern SerialDriver SD3; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* _SERIAL_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC8xx/system_LPC8xx.h b/os/hal/platforms/LPC8xx/system_LPC8xx.h new file mode 100644 index 000000000..108baa842 --- /dev/null +++ b/os/hal/platforms/LPC8xx/system_LPC8xx.h @@ -0,0 +1,62 @@ +/****************************************************************************** + * @file: system_LPC8xx.h + * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Header File + * for the NXP LPC8xx Device Series + * @version: V1.0 + * @date: 16. Aug. 2012 + *---------------------------------------------------------------------------- + * + * Copyright (C) 2012 ARM Limited. All rights reserved. + * + * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __SYSTEM_LPC8xx_H +#define __SYSTEM_LPC8xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_LPC8xx_H */ diff --git a/os/ports/GCC/ARMCMx/LPC8xx/cmparams.h b/os/ports/GCC/ARMCMx/LPC8xx/cmparams.h new file mode 100644 index 000000000..da25ac6a2 --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC8xx/cmparams.h @@ -0,0 +1,60 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/LPC8xx/cmparams.h + * @brief ARM Cortex-M0+ parameters for the LPC8xx. + * + * @defgroup ARMCMx_LPC8xx LPC8xx Specific Parameters + * @ingroup ARMCMx_SPECIFIC + * @details This file contains the Cortex-M0+ specific parameters for the + * LPC8xx platform. + * (Taken from the device header file where possible) + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +#include "LPC8xx.h" + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL __CORTEX_M + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Memory Protection unit presence. + */ +#define CORTEX_HAS_MPU __MPU_PRESENT + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS __NVIC_PRIO_BITS + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/LPC8xx/ld/LPC812.ld b/os/ports/GCC/ARMCMx/LPC8xx/ld/LPC812.ld new file mode 100644 index 000000000..9121f89a2 --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC8xx/ld/LPC812.ld @@ -0,0 +1,150 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC812 memory setup. + */ +__main_stack_size__ = 0x0200; +__process_stack_size__ = 0x0200; + +MEMORY +{ + flash : org = 0x00000000, len = 16k + ram : org = 0x10000000, len = 4k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/LPC8xx/port.mk b/os/ports/GCC/ARMCMx/LPC8xx/port.mk new file mode 100644 index 000000000..9353ee68b --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC8xx/port.mk @@ -0,0 +1,15 @@ +# List of the ChibiOS/RT Cortex-M0 LPC8xx port files. +PORTSRC = $(CHIBIOS)/os/ports/GCC/ARMCMx/crt0.c \ + $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC8xx/vectors.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore.c \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/chcore_v6m.c \ + ${CHIBIOS}/os/ports/common/ARMCMx/nvic.c + +PORTASM = + +PORTINC = ${CHIBIOS}/os/ports/common/ARMCMx/CMSIS/include \ + ${CHIBIOS}/os/ports/common/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx \ + ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC8xx + +PORTLD = ${CHIBIOS}/os/ports/GCC/ARMCMx/LPC8xx/ld diff --git a/os/ports/GCC/ARMCMx/LPC8xx/vectors.c b/os/ports/GCC/ARMCMx/LPC8xx/vectors.c new file mode 100644 index 000000000..f4685dae8 --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC8xx/vectors.c @@ -0,0 +1,199 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012,2013 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file GCC/ARMCMx/LPC8xx/vectors.c + * @brief Interrupt vectors for the LPC8xx family. + * + * @defgroup ARMCMx_LPC8xx_VECTORS LPC8xx Interrupt Vectors + * @ingroup ARMCMx_SPECIFIC + * @details Interrupt vectors for the LPC8xx family. + * @{ + */ + +#include "ch.h" + +/** + * @brief Type of an IRQ vector. + */ +typedef void (*irq_vector_t)(void); + +/** + * @brief Type of a structure representing the whole vectors table. + */ +typedef struct { + uint32_t *init_stack; + irq_vector_t reset_vector; + irq_vector_t nmi_vector; + irq_vector_t hardfault_vector; + irq_vector_t memmanage_vector; + irq_vector_t busfault_vector; + irq_vector_t usagefault_vector; + irq_vector_t vector1c; + irq_vector_t vector20; + irq_vector_t vector24; + irq_vector_t vector28; + irq_vector_t svcall_vector; + irq_vector_t debugmonitor_vector; + irq_vector_t vector34; + irq_vector_t pendsv_vector; + irq_vector_t systick_vector; + irq_vector_t vectors[32]; +} vectors_t; + +#if !defined(__DOXYGEN__) +extern uint32_t __main_stack_end__; +extern void ResetHandler(void); +extern void NMIVector(void); +extern void HardFaultVector(void); +extern void Vector10(void); +extern void Vector14(void); +extern void Vector18(void); +extern void Vector1C(void); +extern void Vector20(void); +extern void Vector24(void); +extern void Vector28(void); +extern void SVCallVector(void); +extern void Vector30(void); +extern void Vector34(void); +extern void PendSVVector(void); +extern void SysTickVector(void); + +extern void Vector40(void); +extern void Vector44(void); +extern void Vector48(void); +extern void Vector4C(void); +extern void Vector50(void); +extern void Vector54(void); +extern void Vector58(void); +extern void Vector5C(void); +extern void Vector60(void); +extern void Vector64(void); +extern void Vector68(void); +extern void Vector6C(void); +extern void Vector70(void); +extern void Vector74(void); +extern void Vector78(void); +extern void Vector7C(void); +extern void Vector80(void); +extern void Vector84(void); +extern void Vector88(void); +extern void Vector8C(void); +extern void Vector90(void); +extern void Vector94(void); +extern void Vector98(void); +extern void Vector9C(void); +extern void VectorA0(void); +extern void VectorA4(void); +extern void VectorA8(void); +extern void VectorAC(void); +extern void VectorB0(void); +extern void VectorB4(void); +extern void VectorB8(void); +extern void VectorBC(void); +#endif + +/** + * @brief LPC8xx vectors table. + */ +#if !defined(__DOXYGEN__) +__attribute__ ((section("vectors"))) +#endif +vectors_t _vectors = { + &__main_stack_end__,ResetHandler, NMIVector, HardFaultVector, + Vector10, Vector14, Vector18, Vector1C, + Vector20, Vector24, Vector28, SVCallVector, + Vector30, Vector34, PendSVVector, SysTickVector, + { + Vector40, Vector44, Vector48, Vector4C, + Vector50, Vector54, Vector58, Vector5C, + Vector60, Vector64, Vector68, Vector6C, + Vector70, Vector74, Vector78, Vector7C, + Vector80, Vector84, Vector88, Vector8C, + Vector90, Vector94, Vector98, Vector9C, + VectorA0, VectorA4, VectorA8, VectorAC, + VectorB0, VectorB4, VectorB8, VectorBC + } +}; + +/** + * @brief Unhandled exceptions handler. + * @details Any undefined exception vector points to this function by default. + * This function simply stops the system into an infinite loop. + * + * @notapi + */ +#if !defined(__DOXYGEN__) +__attribute__ ((naked)) +#endif +void _unhandled_exception(void) { + + while (TRUE) + ; +} + +void NMIVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void HardFaultVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector10(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector14(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector18(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector1C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector20(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector24(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector28(void) __attribute__((weak, alias("_unhandled_exception"))); +void SVCallVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector30(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector34(void) __attribute__((weak, alias("_unhandled_exception"))); +void PendSVVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void SysTickVector(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector40(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector44(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector48(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector4C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector50(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector54(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector58(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector5C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector60(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector64(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector68(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector6C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector70(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector74(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector78(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector7C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector80(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector84(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector88(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector8C(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector90(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector94(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector98(void) __attribute__((weak, alias("_unhandled_exception"))); +void Vector9C(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorA8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorAC(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB0(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB4(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorB8(void) __attribute__((weak, alias("_unhandled_exception"))); +void VectorBC(void) __attribute__((weak, alias("_unhandled_exception"))); + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/rules.mk b/os/ports/GCC/ARMCMx/rules.mk index 33531d201..f3cf0e264 100644 --- a/os/ports/GCC/ARMCMx/rules.mk +++ b/os/ports/GCC/ARMCMx/rules.mk @@ -62,9 +62,9 @@ ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS) CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS) CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS) ifeq ($(USE_LINK_GC),yes) - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR) + LDFLAGS = --specs=nano.specs $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--gc-sections $(LLIBDIR) else - LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch $(LLIBDIR) + LDFLAGS = --specs=nano.specs $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch $(LLIBDIR) endif # Thumb interwork enabled only if needed because it kills performance. diff --git a/readme.txt b/readme.txt index 6a6c33c3b..9f2e434fd 100644 --- a/readme.txt +++ b/readme.txt @@ -29,6 +29,7 @@ | | | +--LPC11xx/ - Drivers for LPC11xx platform. | | | +--LPC13xx/ - Drivers for LPC13xx platform. | | | +--LPC214x/ - Drivers for LPC214x platform. + | | | +--LPC8xx/ - Drivers for LPC8xx platform. | | | +--MSP430/ - Drivers for MSP430 platform. | | | +--SPC5xx/ - Drivers for all SPC5xx platform (common). | | | +--SPC5ELxx/ - Drivers for SPC56ELxx platform.