459 lines
15 KiB
C
459 lines
15 KiB
C
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32/USARTv2/uart_lld.h
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* @brief STM32 low level UART driver header.
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*
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* @addtogroup UART
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* @{
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*/
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#ifndef _UART_LLD_H_
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#define _UART_LLD_H_
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#if HAL_USE_UART || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief UART driver on USART1 enable switch.
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* @details If set to @p TRUE the support for USART1 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_UART_USE_USART1) || defined(__DOXYGEN__)
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#define STM32_UART_USE_USART1 FALSE
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#endif
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/**
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* @brief UART driver on USART2 enable switch.
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* @details If set to @p TRUE the support for USART2 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_UART_USE_USART2) || defined(__DOXYGEN__)
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#define STM32_UART_USE_USART2 FALSE
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#endif
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/**
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* @brief UART driver on USART3 enable switch.
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* @details If set to @p TRUE the support for USART3 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_UART_USE_USART3) || defined(__DOXYGEN__)
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#define STM32_UART_USE_USART3 FALSE
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#endif
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/**
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* @brief USART1 interrupt priority level setting.
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*/
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#if !defined(STM32_UART_USART1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_UART_USART1_IRQ_PRIORITY 12
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#endif
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/**
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* @brief USART2 interrupt priority level setting.
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*/
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#if !defined(STM32_UART_USART2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_UART_USART2_IRQ_PRIORITY 12
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#endif
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/**
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* @brief USART3 interrupt priority level setting.
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*/
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#if !defined(STM32_UART_USART3_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_UART_USART3_IRQ_PRIORITY 12
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#endif
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/**
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* @brief USART1 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA channels but
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* because of the channels ordering the RX channel has always priority
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* over the TX channel.
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*/
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#if !defined(STM32_UART_USART1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_UART_USART1_DMA_PRIORITY 0
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#endif
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/**
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* @brief USART2 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA channels but
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* because of the channels ordering the RX channel has always priority
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* over the TX channel.
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*/
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#if !defined(STM32_UART_USART2_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_UART_USART2_DMA_PRIORITY 0
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#endif
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/**
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* @brief USART3 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA channels but
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* because of the channels ordering the RX channel has always priority
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* over the TX channel.
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*/
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#if !defined(STM32_UART_USART3_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_UART_USART3_DMA_PRIORITY 0
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#endif
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/**
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* @brief USART1 DMA error hook.
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* @note The default action for DMA errors is a system halt because DMA
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* error can only happen because programming errors.
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*/
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#if !defined(STM32_UART_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
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#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
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#endif
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#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)
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/**
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* @brief DMA stream used for USART1 RX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_UART_USART1_RX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
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#endif
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/**
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* @brief DMA stream used for USART1 TX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_UART_USART1_TX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
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#endif
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/**
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* @brief DMA stream used for USART2 RX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_UART_USART2_RX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#endif
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/**
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* @brief DMA stream used for USART2 TX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_UART_USART2_TX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#endif
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/**
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* @brief DMA stream used for USART3 RX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_UART_USART3_RX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
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#endif
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/**
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* @brief DMA stream used for USART3 TX operations.
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* @note This option is only available on platforms with enhanced DMA.
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*/
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#if !defined(STM32_UART_USART3_TX_DMA_STREAM) || defined(__DOXYGEN__)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#endif
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#else /* !STM32_ADVANCED_DMA*/
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#if defined(STM32F0XX)
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/* Fixed values for STM32F0xx devices.*/
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#endif /* defined(STM32F0XX) */
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#if defined(STM32F30X)|| defined(STM32F37X)
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/* Fixed values for STM32F3xx devices.*/
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#endif /* defined(STM32F30X) */
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#endif /* !STM32_ADVANCED_DMA*/
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if STM32_UART_USE_USART1 && !STM32_HAS_USART1
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#error "USART1 not present in the selected device"
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#endif
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#if STM32_UART_USE_USART2 && !STM32_HAS_USART2
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#error "USART2 not present in the selected device"
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#endif
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#if STM32_UART_USE_USART3 && !STM32_HAS_USART3
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#error "USART3 not present in the selected device"
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#endif
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#if !STM32_UART_USE_USART1 && !STM32_UART_USE_USART2 && \
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!STM32_UART_USE_USART3
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#error "UART driver activated but no USART/UART peripheral assigned"
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#endif
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#if STM32_UART_USE_USART1 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART1_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to USART1"
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#endif
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#if STM32_UART_USE_USART2 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART2_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to USART2"
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#endif
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#if STM32_UART_USE_USART3 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_UART_USART3_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to USART3"
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#endif
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#if STM32_UART_USE_USART1 && \
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!STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART1_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to USART1"
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#endif
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#if STM32_UART_USE_USART2 && \
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!STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART2_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to USART2"
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#endif
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#if STM32_UART_USE_USART3 && \
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!STM32_DMA_IS_VALID_PRIORITY(STM32_UART_USART3_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to USART3"
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#endif
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#if STM32_UART_USE_USART1 && \
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!STM32_DMA_IS_VALID_ID(STM32_UART_USART1_RX_DMA_STREAM, \
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STM32_USART1_RX_DMA_MSK)
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#error "invalid DMA stream associated to USART1 RX"
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#endif
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#if STM32_UART_USE_USART1 && \
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!STM32_DMA_IS_VALID_ID(STM32_UART_USART1_TX_DMA_STREAM, \
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STM32_USART1_TX_DMA_MSK)
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#error "invalid DMA stream associated to USART1 TX"
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#endif
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#if STM32_UART_USE_USART2 && \
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!STM32_DMA_IS_VALID_ID(STM32_UART_USART2_RX_DMA_STREAM, \
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STM32_USART2_RX_DMA_MSK)
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#error "invalid DMA stream associated to USART2 RX"
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#endif
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#if STM32_UART_USE_USART2 && \
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!STM32_DMA_IS_VALID_ID(STM32_UART_USART2_TX_DMA_STREAM, \
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STM32_USART2_TX_DMA_MSK)
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#error "invalid DMA stream associated to USART2 TX"
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#endif
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#if STM32_UART_USE_USART3 && \
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!STM32_DMA_IS_VALID_ID(STM32_UART_USART3_RX_DMA_STREAM, \
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STM32_USART3_RX_DMA_MSK)
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#error "invalid DMA stream associated to USART3 RX"
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#endif
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#if STM32_UART_USE_USART3 && \
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!STM32_DMA_IS_VALID_ID(STM32_UART_USART3_TX_DMA_STREAM, \
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STM32_USART3_TX_DMA_MSK)
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#error "invalid DMA stream associated to USART3 TX"
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#endif
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#if !defined(STM32_DMA_REQUIRED)
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#define STM32_DMA_REQUIRED
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief UART driver condition flags type.
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*/
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typedef uint32_t uartflags_t;
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/**
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* @brief Structure representing an UART driver.
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*/
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typedef struct UARTDriver UARTDriver;
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/**
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* @brief Generic UART notification callback type.
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*
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* @param[in] uartp pointer to the @p UARTDriver object
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*/
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typedef void (*uartcb_t)(UARTDriver *uartp);
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/**
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* @brief Character received UART notification callback type.
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*
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* @param[in] uartp pointer to the @p UARTDriver object
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* @param[in] c received character
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*/
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typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c);
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/**
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* @brief Receive error UART notification callback type.
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*
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* @param[in] uartp pointer to the @p UARTDriver object
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* @param[in] e receive error mask
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*/
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typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e);
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/**
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* @brief Driver configuration structure.
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* @note It could be empty on some architectures.
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*/
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typedef struct {
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/**
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* @brief End of transmission buffer callback.
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*/
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uartcb_t txend1_cb;
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/**
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* @brief Physical end of transmission callback.
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*/
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uartcb_t txend2_cb;
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/**
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* @brief Receive buffer filled callback.
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*/
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uartcb_t rxend_cb;
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/**
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* @brief Character received while out if the @p UART_RECEIVE state.
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*/
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uartccb_t rxchar_cb;
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/**
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* @brief Receive error callback.
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*/
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|
uartecb_t rxerr_cb;
|
||
|
|
/* End of the mandatory fields.*/
|
||
|
|
/**
|
||
|
|
* @brief Bit rate.
|
||
|
|
*/
|
||
|
|
uint32_t speed;
|
||
|
|
/**
|
||
|
|
* @brief Initialization value for the CR1 register.
|
||
|
|
*/
|
||
|
|
uint32_t cr1;
|
||
|
|
/**
|
||
|
|
* @brief Initialization value for the CR2 register.
|
||
|
|
*/
|
||
|
|
uint32_t cr2;
|
||
|
|
/**
|
||
|
|
* @brief Initialization value for the CR3 register.
|
||
|
|
*/
|
||
|
|
uint32_t cr3;
|
||
|
|
} UARTConfig;
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Structure representing an UART driver.
|
||
|
|
*/
|
||
|
|
struct UARTDriver {
|
||
|
|
/**
|
||
|
|
* @brief Driver state.
|
||
|
|
*/
|
||
|
|
uartstate_t state;
|
||
|
|
/**
|
||
|
|
* @brief Transmitter state.
|
||
|
|
*/
|
||
|
|
uarttxstate_t txstate;
|
||
|
|
/**
|
||
|
|
* @brief Receiver state.
|
||
|
|
*/
|
||
|
|
uartrxstate_t rxstate;
|
||
|
|
/**
|
||
|
|
* @brief Current configuration data.
|
||
|
|
*/
|
||
|
|
const UARTConfig *config;
|
||
|
|
#if defined(UART_DRIVER_EXT_FIELDS)
|
||
|
|
UART_DRIVER_EXT_FIELDS
|
||
|
|
#endif
|
||
|
|
/* End of the mandatory fields.*/
|
||
|
|
/**
|
||
|
|
* @brief Pointer to the USART registers block.
|
||
|
|
*/
|
||
|
|
USART_TypeDef *usart;
|
||
|
|
/**
|
||
|
|
* @brief DMA mode bit mask.
|
||
|
|
*/
|
||
|
|
uint32_t dmamode;
|
||
|
|
/**
|
||
|
|
* @brief Receive DMA channel.
|
||
|
|
*/
|
||
|
|
const stm32_dma_stream_t *dmarx;
|
||
|
|
/**
|
||
|
|
* @brief Transmit DMA channel.
|
||
|
|
*/
|
||
|
|
const stm32_dma_stream_t *dmatx;
|
||
|
|
/**
|
||
|
|
* @brief Default receive buffer while into @p UART_RX_IDLE state.
|
||
|
|
*/
|
||
|
|
volatile uint16_t rxbuf;
|
||
|
|
};
|
||
|
|
|
||
|
|
/*===========================================================================*/
|
||
|
|
/* Driver macros. */
|
||
|
|
/*===========================================================================*/
|
||
|
|
|
||
|
|
/*===========================================================================*/
|
||
|
|
/* External declarations. */
|
||
|
|
/*===========================================================================*/
|
||
|
|
|
||
|
|
#if STM32_UART_USE_USART1 && !defined(__DOXYGEN__)
|
||
|
|
extern UARTDriver UARTD1;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if STM32_UART_USE_USART2 && !defined(__DOXYGEN__)
|
||
|
|
extern UARTDriver UARTD2;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if STM32_UART_USE_USART3 && !defined(__DOXYGEN__)
|
||
|
|
extern UARTDriver UARTD3;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
extern "C" {
|
||
|
|
#endif
|
||
|
|
void uart_lld_init(void);
|
||
|
|
void uart_lld_start(UARTDriver *uartp);
|
||
|
|
void uart_lld_stop(UARTDriver *uartp);
|
||
|
|
void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf);
|
||
|
|
size_t uart_lld_stop_send(UARTDriver *uartp);
|
||
|
|
void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf);
|
||
|
|
size_t uart_lld_stop_receive(UARTDriver *uartp);
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* HAL_USE_UART */
|
||
|
|
|
||
|
|
#endif /* _UART_LLD_H_ */
|
||
|
|
|
||
|
|
/** @} */
|