366 lines
12 KiB
C
366 lines
12 KiB
C
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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Concepts and parts of this file have been contributed by Uladzimir Pylinsky
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aka barthess.
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*/
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/**
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* @file STM32/I2Cv2/i2c_lld.h
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* @brief STM32 I2C subsystem low level driver header.
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*
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* @addtogroup I2C
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* @{
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*/
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#ifndef _I2C_LLD_H_
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#define _I2C_LLD_H_
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#if HAL_USE_I2C || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name TIMINGR register definitions
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* @{
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*/
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#define STM32_TIMINGR_PRESC_MASK (15U << 28)
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#define STM32_TIMINGR_PRESC(n) ((n) << 28)
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#define STM32_TIMINGR_SCLDEL_MASK (15U << 20)
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#define STM32_TIMINGR_SCLDEL(n) ((n) << 20)
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#define STM32_TIMINGR_SDADEL_MASK (15U << 16)
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#define STM32_TIMINGR_SDADEL(n) ((n) << 16)
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#define STM32_TIMINGR_SCLH_MASK (255U << 8)
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#define STM32_TIMINGR_SCLH(n) ((n) << 8)
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#define STM32_TIMINGR_SCLL_MASK (255U << 0)
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#define STM32_TIMINGR_SCLL(n) ((n) << 0)
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief I2C1 driver enable switch.
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* @details If set to @p TRUE the support for I2C1 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_I2C_USE_I2C1) || defined(__DOXYGEN__)
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#define STM32_I2C_USE_I2C1 FALSE
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#endif
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/**
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* @brief I2C2 driver enable switch.
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* @details If set to @p TRUE the support for I2C2 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_I2C_USE_I2C2) || defined(__DOXYGEN__)
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#define STM32_I2C_USE_I2C2 FALSE
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#endif
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/**
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* @brief I2C timeout on busy condition in milliseconds.
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*/
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#if !defined(STM32_I2C_BUSY_TIMEOUT) || defined(__DOXYGEN__)
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#define STM32_I2C_BUSY_TIMEOUT 50
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#endif
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/**
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* @brief I2C1 interrupt priority level setting.
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*/
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#if !defined(STM32_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C1_IRQ_PRIORITY 10
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#endif
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/**
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* @brief I2C2 interrupt priority level setting.
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*/
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#if !defined(STM32_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C2_IRQ_PRIORITY 10
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#endif
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/**
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* @brief I2C1 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA streams but
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* because of the streams ordering the RX stream has always priority
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* over the TX stream.
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*/
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#if !defined(STM32_I2C_I2C1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C1_DMA_PRIORITY 1
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#endif
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/**
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* @brief I2C2 DMA priority (0..3|lowest..highest).
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* @note The priority level is used for both the TX and RX DMA streams but
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* because of the streams ordering the RX stream has always priority
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* over the TX stream.
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*/
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#if !defined(STM32_I2C_I2C2_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_I2C_I2C2_DMA_PRIORITY 1
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#endif
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/**
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* @brief I2C DMA error hook.
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* @note The default action for DMA errors is a system halt because DMA
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* error can only happen because programming errors.
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*/
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#if !defined(STM32_I2C_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
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#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/* TODO: Move the following DMA settings in the STM32F37X registry.*/
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#if defined(STM32F37X)
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#endif
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/** @brief error checks */
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#if STM32_I2C_USE_I2C1 && !STM32_HAS_I2C1
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#error "I2C1 not present in the selected device"
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#endif
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#if STM32_I2C_USE_I2C2 && !STM32_HAS_I2C2
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#error "I2C2 not present in the selected device"
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#endif
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#if !STM32_I2C_USE_I2C1 && !STM32_I2C_USE_I2C2
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#error "I2C driver activated but no I2C peripheral assigned"
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#endif
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#if STM32_I2C_USE_I2C1 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_I2C_I2C1_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to I2C1"
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#endif
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#if STM32_I2C_USE_I2C2 && \
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!CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_I2C_I2C2_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to I2C2"
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#endif
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#if STM32_I2C_USE_I2C1 && \
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!STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C1_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to I2C1"
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#endif
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#if STM32_I2C_USE_I2C2 && \
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!STM32_DMA_IS_VALID_PRIORITY(STM32_I2C_I2C2_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to I2C2"
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#endif
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/* The following checks are only required when there is a DMA able to
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reassign streams to different channels.*/
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#if STM32_ADVANCED_DMA
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/* Check on the presence of the DMA streams settings in mcuconf.h.*/
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#if STM32_I2C_USE_I2C1 && (!defined(STM32_I2C_I2C1_RX_DMA_STREAM) || \
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!defined(STM32_I2C_I2C1_TX_DMA_STREAM))
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#error "I2C1 DMA streams not defined"
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#endif
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#if STM32_I2C_USE_I2C2 && (!defined(STM32_I2C_I2C2_RX_DMA_STREAM) || \
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!defined(STM32_I2C_I2C2_TX_DMA_STREAM))
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#error "I2C2 DMA streams not defined"
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#endif
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/* Check on the validity of the assigned DMA channels.*/
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#if STM32_I2C_USE_I2C1 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_RX_DMA_STREAM, \
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STM32_I2C1_RX_DMA_MSK)
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#error "invalid DMA stream associated to I2C1 RX"
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#endif
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#if STM32_I2C_USE_I2C1 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C1_TX_DMA_STREAM, \
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STM32_I2C1_TX_DMA_MSK)
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#error "invalid DMA stream associated to I2C1 TX"
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#endif
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#if STM32_I2C_USE_I2C2 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_RX_DMA_STREAM, \
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STM32_I2C2_RX_DMA_MSK)
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#error "invalid DMA stream associated to I2C2 RX"
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#endif
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#if STM32_I2C_USE_I2C2 && \
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!STM32_DMA_IS_VALID_ID(STM32_I2C_I2C2_TX_DMA_STREAM, \
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STM32_I2C2_TX_DMA_MSK)
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#error "invalid DMA stream associated to I2C2 TX"
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#endif
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#endif /* STM32_ADVANCED_DMA */
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#if !defined(STM32_DMA_REQUIRED)
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#define STM32_DMA_REQUIRED
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#endif
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/* Check clock range. */
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief Type representing I2C address.
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*/
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typedef uint16_t i2caddr_t;
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/**
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* @brief I2C Driver condition flags type.
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*/
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typedef uint32_t i2cflags_t;
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/**
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* @brief Driver configuration structure.
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*/
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typedef struct {
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/**
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* @brief TIMINGR register initialization.
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* @note Refer to the STM32 reference manual, the values are affected
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* by the system clock settings in mcuconf.h.
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*/
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uint32_t timingr;
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/**
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* @brief CR1 register initialization.
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* @note Leave to zero unless you know what you are doing.
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*/
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uint32_t cr1;
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/**
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* @brief CR2 register initialization.
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* @note Only the ADD10 bit can eventually be specified here.
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*/
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uint32_t cr2;
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} I2CConfig;
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/**
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* @brief Type of a structure representing an I2C driver.
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*/
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typedef struct I2CDriver I2CDriver;
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/**
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* @brief Structure representing an I2C driver.
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*/
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struct I2CDriver{
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/**
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* @brief Driver state.
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*/
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i2cstate_t state;
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/**
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* @brief Current configuration data.
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*/
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const I2CConfig *config;
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/**
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* @brief Error flags.
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*/
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i2cflags_t errors;
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#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
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mutex_t mutex;
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#endif /* I2C_USE_MUTUAL_EXCLUSION */
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#if defined(I2C_DRIVER_EXT_FIELDS)
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I2C_DRIVER_EXT_FIELDS
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#endif
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/* End of the mandatory fields.*/
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/**
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* @brief Thread waiting for I/O completion.
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*/
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thread_reference_t thread;
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/**
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* @brief Current slave address without R/W bit.
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*/
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i2caddr_t addr;
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/**
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* @brief RX DMA mode bit mask.
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*/
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uint32_t rxdmamode;
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/**
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* @brief TX DMA mode bit mask.
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*/
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uint32_t txdmamode;
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/**
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* @brief Receive DMA channel.
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*/
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const stm32_dma_stream_t *dmarx;
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/**
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* @brief Transmit DMA channel.
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*/
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const stm32_dma_stream_t *dmatx;
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/**
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* @brief Pointer to the I2Cx registers block.
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*/
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I2C_TypeDef *i2c;
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};
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @brief Get errors from I2C driver.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*
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* @notapi
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*/
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#define i2c_lld_get_errors(i2cp) ((i2cp)->errors)
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if !defined(__DOXYGEN__)
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#if STM32_I2C_USE_I2C1
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extern I2CDriver I2CD1;
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#endif
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#if STM32_I2C_USE_I2C2
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extern I2CDriver I2CD2;
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#endif
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#endif /* !defined(__DOXYGEN__) */
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#ifdef __cplusplus
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extern "C" {
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#endif
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void i2c_lld_init(void);
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void i2c_lld_start(I2CDriver *i2cp);
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void i2c_lld_stop(I2CDriver *i2cp);
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msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
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const uint8_t *txbuf, size_t txbytes,
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uint8_t *rxbuf, size_t rxbytes,
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systime_t timeout);
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msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
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uint8_t *rxbuf, size_t rxbytes,
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systime_t timeout);
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#ifdef __cplusplus
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}
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#endif
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#endif /* HAL_USE_I2C */
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||
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||
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#endif /* _I2C_LLD_H_ */
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||
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/** @} */
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