157 lines
6.1 KiB
C
157 lines
6.1 KiB
C
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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* LPC43xx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the driver
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* is enabled in halconf.h.
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*
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* IRQ priorities:
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* 7...0 Lowest...highest.
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*
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* LPC base clock sources:
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* 0x00 32 kHz oscillator
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* 0x01 IRC (default)
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* 0x02 ENET_RX_CLK
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* 0x03 ENET_TX_CLK
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* 0x04 GP_CLKIN
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* 0x06 Crystal oscillator
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* 0x07 PLL0USB
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* 0x08 PLL0AUDIO
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* 0x09 PLL1
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* 0x0C IDIVA
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* 0x0D IDIVB
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* 0x0E IDIVC
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* 0x0F IDIVD
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* 0x10 IDIVE
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*/
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/*
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* HAL driver system settings.
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*/
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#define LPC_XTAL_ENABLE TRUE
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#define LPC_PLL1_ENABLE TRUE
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#define LPC_PLL1_MUL 17
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#define LPC_PLL1_PREDIV 1
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#define LPC_PLL1_POSTDIV_ENABLE FALSE
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#define LPC_PLL1_POSTDIV 2
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#define LPC_PLL0USB_ENABLE FALSE
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#define LPC_PLL0AUDIO_ENABLE FALSE
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#define LPC_FLASHLESS TRUE
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/* Clock dividers */
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#define LPC_IDIVA_ENABLE FALSE
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#define LPC_IDIVA_DIV 1
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#define LPC_IDIVA_SRC 0x09
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#define LPC_IDIVB_ENABLE FALSE
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#define LPC_IDIVB_DIV 2
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#define LPC_IDIVB_SRC 0x09
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#define LPC_IDIVC_ENABLE FALSE
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#define LPC_IDIVC_DIV 3
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#define LPC_IDIVC_SRC 0x09
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#define LPC_IDIVD_ENABLE FALSE
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#define LPC_IDIVD_DIV 1
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#define LPC_IDIVD_SRC 0x09
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#define LPC_IDIVE_ENABLE FALSE
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#define LPC_IDIVE_DIV 1
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#define LPC_IDIVE_SRC 0x09
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/* Base clocks */
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#define LPC_BASE_USB0_CLK_ENABLE FALSE /* Base clock for USB0. */
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#define LPC_BASE_PERIPH_CLK_ENABLE TRUE /* Base clock for Cortex-M0SUB subsystem, SGPIO. */
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#define LPC_BASE_PERIPH_CLK_SRC 0x09
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#define LPC_BASE_USB1_CLK_ENABLE TRUE /* Base clock for USB1. */
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#define LPC_BASE_USB1_CLK_SRC 0x01
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#define LPC_BASE_SPIFI_CLK_ENABLE FALSE /* Base clock for SPIFI. */
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#define LPC_BASE_SPIFI_CLK_SRC 0x0D
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#define LPC_BASE_SPI_CLK_ENABLE TRUE /* Base clock for SPI. */
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#define LPC_BASE_SPI_CLK_SRC 0x01
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#define LPC_BASE_PHY_RX_CLK_ENABLE FALSE /* Base clock for Ethernet PHY Receive clock. */
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#define LPC_BASE_PHY_RX_CLK_SRC 0x0E
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#define LPC_BASE_PHY_TX_CLK_ENABLE FALSE /* Base clock for Ethernet PHY Transmit clock. */
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#define LPC_BASE_PHY_TX_CLK_SRC 0x0E
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#define LPC_BASE_APB1_CLK_ENABLE TRUE /* Base clock for APB1: I2C0, I2S, CAN1. */
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#define LPC_BASE_APB1_CLK_SRC 0x01
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#define LPC_BASE_APB3_CLK_ENABLE TRUE /* Base clock for APB3: I2C1, DAC, ADC0, ADC1, CAN0. */
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#define LPC_BASE_APB3_CLK_SRC 0x01
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#define LPC_BASE_LCD_CLK_ENABLE FALSE /* Base clock for LCD. */
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#define LPC_BASE_LCD_CLK_SRC 0x01
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#define LPC_BASE_SDIO_CLK_ENABLE FALSE /* Base clock for SD/MMC. */
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#define LPC_BASE_SDIO_CLK_SRC 0x01
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#define LPC_BASE_SSP0_CLK_ENABLE TRUE /* Base clock for SSP0. */
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#define LPC_BASE_SSP0_CLK_SRC 0x01
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#define LPC_BASE_SSP1_CLK_ENABLE TRUE /* Base clock for SSP1. */
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#define LPC_BASE_SSP1_CLK_SRC 0x01
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#define LPC_BASE_UART0_CLK_ENABLE TRUE /* Base clock for UART0. */
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#define LPC_BASE_UART0_CLK_SRC 0x01
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#define LPC_BASE_UART1_CLK_ENABLE TRUE /* Base clock for UART1. */
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#define LPC_BASE_UART1_CLK_SRC 0x01
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#define LPC_BASE_UART2_CLK_ENABLE TRUE /* Base clock for UART2. */
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#define LPC_BASE_UART2_CLK_SRC 0x01
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#define LPC_BASE_UART3_CLK_ENABLE TRUE /* Base clock for UART3. */
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#define LPC_BASE_UART3_CLK_SRC 0x01
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#define LPC_BASE_OUT_CLK_ENABLE FALSE /* Base clock for UART0. */
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#define LPC_BASE_OUT_CLK_SRC 0x01
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#define LPC_BASE_APLL_CLK_ENABLE FALSE /* Base clock for audio system. */
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#define LPC_BASE_APLL_CLK_SRC 0x01
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#define LPC_BASE_CGU_OUT0_CLK_ENABLE FALSE /* Base clock for CGU_OUT0 clock output. */
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#define LPC_BASE_CGU_OUT0_CLK_SRC 0x01
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#define LPC_BASE_CGU_OUT1_CLK_ENABLE FALSE /* Base clock for CGU_OUT1 clock output. */
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#define LPC_BASE_CGU_OUT1_CLK_SRC 0x01
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/*
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* GPT driver system settings.
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*/
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#define LPC_GPT_USE_TIM0 FALSE
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#define LPC_GPT_USE_TIM1 FALSE
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#define LPC_GPT_USE_TIM2 FALSE
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#define LPC_GPT_USE_TIM3 FALSE
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#define LPC_GPT_TIM0_IRQ_PRIORITY 2
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#define LPC_GPT_TIM1_IRQ_PRIORITY 2
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#define LPC_GPT_TIM2_IRQ_PRIORITY 2
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#define LPC_GPT_TIM3_IRQ_PRIORITY 2
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/*
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* SERIAL driver system settings.
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*/
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#define LPC_SERIAL_USE_UART0 FALSE
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#define LPC_SERIAL_USE_UART1 FALSE
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#define LPC_SERIAL_USE_UART2 FALSE
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#define LPC_SERIAL_USE_UART3 TRUE
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#define LPC_SERIAL_FIFO_PRELOAD 16
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#define LPC_SERIAL_UART0_IRQ_PRIORITY 3
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#define LPC_SERIAL_UART1_IRQ_PRIORITY 3
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#define LPC_SERIAL_UART2_IRQ_PRIORITY 3
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#define LPC_SERIAL_UART3_IRQ_PRIORITY 3
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/*
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* I2C driver system settings.
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*/
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#define LPC_I2C_USE_I2C0 FALSE
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#define LPC_I2C_USE_I2C1 FALSE
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#define LPC_I2C_I2C0_IRQ_PRIORITY 3
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#define LPC_I2C_I2C1_IRQ_PRIORITY 3
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/*
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* SPI driver system settings.
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*/
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#define LPC_SPI_USE_SSP0 FALSE
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#define LPC_SPI_USE_SSP1 FALSE
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#define LPC_SPI_SSP0_IRQ_PRIORITY 5
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#define LPC_SPI_SSP1_IRQ_PRIORITY 5
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