2012-10-05 09:59:50 +00:00
|
|
|
/*
|
2013-04-11 12:23:05 +00:00
|
|
|
SPC5 HAL - Copyright (C) 2013 STMicroelectronics
|
|
|
|
|
|
|
|
|
|
Licensed under the Apache License, Version 2.0 (the "License");
|
|
|
|
|
you may not use this file except in compliance with the License.
|
|
|
|
|
You may obtain a copy of the License at
|
|
|
|
|
|
|
|
|
|
http://www.apache.org/licenses/LICENSE-2.0
|
|
|
|
|
|
|
|
|
|
Unless required by applicable law or agreed to in writing, software
|
|
|
|
|
distributed under the License is distributed on an "AS IS" BASIS,
|
|
|
|
|
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
|
|
|
|
See the License for the specific language governing permissions and
|
|
|
|
|
limitations under the License.
|
|
|
|
|
*/
|
2012-10-05 09:59:50 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* SPC560Pxx drivers configuration.
|
|
|
|
|
* The following settings override the default settings present in
|
|
|
|
|
* the various device driver implementation headers.
|
|
|
|
|
* Note that the settings for each driver only have effect if the whole
|
|
|
|
|
* driver is enabled in halconf.h.
|
|
|
|
|
*
|
|
|
|
|
* IRQ priorities:
|
|
|
|
|
* 1...15 Lowest...Highest.
|
2013-06-14 14:25:39 +00:00
|
|
|
* DMA priorities:
|
|
|
|
|
* 0...15 Highest...Lowest.
|
2012-10-05 09:59:50 +00:00
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define SPC560Pxx_MCUCONF
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* HAL driver system settings.
|
|
|
|
|
*/
|
|
|
|
|
#define SPC5_NO_INIT FALSE
|
|
|
|
|
#define SPC5_ALLOW_OVERCLOCK FALSE
|
2013-02-19 14:25:56 +00:00
|
|
|
#define SPC5_DISABLE_WATCHDOG TRUE
|
2013-02-19 15:06:03 +00:00
|
|
|
#define SPC5_FMPLL0_IDF_VALUE 5
|
|
|
|
|
#define SPC5_FMPLL0_NDIV_VALUE 32
|
|
|
|
|
#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
|
|
|
|
|
#define SPC5_FMPLL1_IDF_VALUE 5
|
|
|
|
|
#define SPC5_FMPLL1_NDIV_VALUE 60
|
|
|
|
|
#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
|
2013-02-19 14:25:56 +00:00
|
|
|
#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL1
|
|
|
|
|
#define SPC5_MCONTROL_DIVIDER_VALUE 2
|
|
|
|
|
#define SPC5_FMPLL1_CLK_DIVIDER_VALUE 2
|
|
|
|
|
#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1
|
|
|
|
|
#define SPC5_SP_CLK_DIVIDER_VALUE 2
|
|
|
|
|
#define SPC5_AUX3CLK_SRC SPC5_CGM_SS_FMPLL1
|
|
|
|
|
#define SPC5_FR_CLK_DIVIDER_VALUE 2
|
2012-10-05 09:59:50 +00:00
|
|
|
#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \
|
|
|
|
|
SPC5_ME_ME_RUN2 | \
|
|
|
|
|
SPC5_ME_ME_RUN3 | \
|
|
|
|
|
SPC5_ME_ME_HALT0 | \
|
|
|
|
|
SPC5_ME_ME_STOP0)
|
|
|
|
|
#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \
|
|
|
|
|
SPC5_ME_MC_IRCON | \
|
|
|
|
|
SPC5_ME_MC_XOSC0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL1ON | \
|
|
|
|
|
SPC5_ME_MC_CFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_DFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_MVRON)
|
|
|
|
|
#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO)
|
|
|
|
|
#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
|
|
|
|
|
SPC5_ME_MC_IRCON | \
|
|
|
|
|
SPC5_ME_MC_XOSC0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL1ON | \
|
|
|
|
|
SPC5_ME_MC_CFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_DFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_MVRON)
|
|
|
|
|
#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
|
|
|
|
|
SPC5_ME_MC_IRCON | \
|
|
|
|
|
SPC5_ME_MC_XOSC0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL1ON | \
|
|
|
|
|
SPC5_ME_MC_CFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_DFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_MVRON)
|
|
|
|
|
#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
|
|
|
|
|
SPC5_ME_MC_IRCON | \
|
|
|
|
|
SPC5_ME_MC_XOSC0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL1ON | \
|
|
|
|
|
SPC5_ME_MC_CFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_DFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_MVRON)
|
|
|
|
|
#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
|
|
|
|
|
SPC5_ME_MC_IRCON | \
|
|
|
|
|
SPC5_ME_MC_XOSC0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL1ON | \
|
|
|
|
|
SPC5_ME_MC_CFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_DFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_MVRON)
|
|
|
|
|
#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
|
|
|
|
|
SPC5_ME_MC_IRCON | \
|
|
|
|
|
SPC5_ME_MC_XOSC0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL1ON | \
|
|
|
|
|
SPC5_ME_MC_CFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_DFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_MVRON)
|
|
|
|
|
#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
|
|
|
|
|
SPC5_ME_MC_IRCON | \
|
|
|
|
|
SPC5_ME_MC_XOSC0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL1ON | \
|
|
|
|
|
SPC5_ME_MC_CFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_DFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_MVRON)
|
|
|
|
|
#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
|
|
|
|
|
SPC5_ME_MC_IRCON | \
|
|
|
|
|
SPC5_ME_MC_XOSC0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL1ON | \
|
|
|
|
|
SPC5_ME_MC_CFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_DFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_MVRON)
|
|
|
|
|
#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN1 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN2 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN3)
|
|
|
|
|
#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN1 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN2 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN3)
|
|
|
|
|
#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN1 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN2 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN3)
|
|
|
|
|
#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN1 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN2 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN3)
|
|
|
|
|
#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN1 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN2 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN3)
|
|
|
|
|
#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
|
|
|
|
|
SPC5_ME_LP_PC_STOP0)
|
|
|
|
|
#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
|
|
|
|
|
SPC5_ME_LP_PC_STOP0)
|
|
|
|
|
#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \
|
|
|
|
|
SPC5_ME_LP_PC_STOP0)
|
|
|
|
|
#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
|
|
|
|
|
SPC5_ME_LP_PC_STOP0)
|
2012-11-19 12:47:33 +00:00
|
|
|
#define SPC5_PIT0_IRQ_PRIORITY 4
|
2013-02-19 14:25:56 +00:00
|
|
|
#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
|
2012-10-05 09:59:50 +00:00
|
|
|
|
2013-06-14 14:25:39 +00:00
|
|
|
/*
|
|
|
|
|
* EDMA driver settings.
|
|
|
|
|
*/
|
|
|
|
|
#define SPC5_EDMA_CR_SETTING 0
|
|
|
|
|
#define SPC5_EDMA_GROUP0_PRIORITIES \
|
|
|
|
|
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
|
|
|
|
|
#define SPC5_EDMA_ERROR_IRQ_PRIO 2
|
|
|
|
|
#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
|
|
|
|
|
|
2012-10-05 09:59:50 +00:00
|
|
|
/*
|
|
|
|
|
* SERIAL driver system settings.
|
|
|
|
|
*/
|
|
|
|
|
#define SPC5_SERIAL_USE_LINFLEX0 TRUE
|
|
|
|
|
#define SPC5_SERIAL_USE_LINFLEX1 TRUE
|
|
|
|
|
#define SPC5_SERIAL_LINFLEX0_PRIORITY 8
|
|
|
|
|
#define SPC5_SERIAL_LINFLEX1_PRIORITY 8
|
|
|
|
|
#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
|
|
|
|
SPC5_ME_PCTL_LP(2))
|
|
|
|
|
#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
|
|
|
|
SPC5_ME_PCTL_LP(0))
|
|
|
|
|
#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
|
|
|
|
SPC5_ME_PCTL_LP(2))
|
|
|
|
|
#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
|
|
|
|
SPC5_ME_PCTL_LP(0))
|
2013-06-14 14:25:39 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* SPI driver system settings.
|
|
|
|
|
*/
|
|
|
|
|
#define SPC5_SPI_USE_DSPI0 TRUE
|
|
|
|
|
#define SPC5_SPI_USE_DSPI1 TRUE
|
|
|
|
|
#define SPC5_SPI_USE_DSPI2 TRUE
|
|
|
|
|
#define SPC5_SPI_USE_DSPI3 TRUE
|
|
|
|
|
#define SPC5_SPI_USE_DSPI4 FALSE
|
|
|
|
|
#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \
|
|
|
|
|
SPC5_MCR_PCSIS1 | \
|
|
|
|
|
SPC5_MCR_PCSIS2 | \
|
|
|
|
|
SPC5_MCR_PCSIS3 | \
|
|
|
|
|
SPC5_MCR_PCSIS4 | \
|
|
|
|
|
SPC5_MCR_PCSIS5 | \
|
|
|
|
|
SPC5_MCR_PCSIS6 | \
|
|
|
|
|
SPC5_MCR_PCSIS7)
|
|
|
|
|
#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
|
|
|
|
|
SPC5_MCR_PCSIS1 | \
|
|
|
|
|
SPC5_MCR_PCSIS2 | \
|
|
|
|
|
SPC5_MCR_PCSIS3 | \
|
|
|
|
|
SPC5_MCR_PCSIS4 | \
|
|
|
|
|
SPC5_MCR_PCSIS5 | \
|
|
|
|
|
SPC5_MCR_PCSIS6 | \
|
|
|
|
|
SPC5_MCR_PCSIS7)
|
|
|
|
|
#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \
|
|
|
|
|
SPC5_MCR_PCSIS1 | \
|
|
|
|
|
SPC5_MCR_PCSIS2 | \
|
|
|
|
|
SPC5_MCR_PCSIS3 | \
|
|
|
|
|
SPC5_MCR_PCSIS4 | \
|
|
|
|
|
SPC5_MCR_PCSIS5 | \
|
|
|
|
|
SPC5_MCR_PCSIS6 | \
|
|
|
|
|
SPC5_MCR_PCSIS7)
|
|
|
|
|
#define SPC5_SPI_DSPI3_MCR (SPC5_MCR_PCSIS0 | \
|
|
|
|
|
SPC5_MCR_PCSIS1 | \
|
|
|
|
|
SPC5_MCR_PCSIS2 | \
|
|
|
|
|
SPC5_MCR_PCSIS3 | \
|
|
|
|
|
SPC5_MCR_PCSIS4 | \
|
|
|
|
|
SPC5_MCR_PCSIS5 | \
|
|
|
|
|
SPC5_MCR_PCSIS6 | \
|
|
|
|
|
SPC5_MCR_PCSIS7)
|
|
|
|
|
#define SPC5_SPI_DSPI4_MCR (SPC5_MCR_PCSIS0 | \
|
|
|
|
|
SPC5_MCR_PCSIS1 | \
|
|
|
|
|
SPC5_MCR_PCSIS2 | \
|
|
|
|
|
SPC5_MCR_PCSIS3 | \
|
|
|
|
|
SPC5_MCR_PCSIS4 | \
|
|
|
|
|
SPC5_MCR_PCSIS5 | \
|
|
|
|
|
SPC5_MCR_PCSIS6 | \
|
|
|
|
|
SPC5_MCR_PCSIS7)
|
|
|
|
|
#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
|
|
|
|
|
#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
|
|
|
|
|
#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
|
|
|
|
|
#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10
|
|
|
|
|
#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO 10
|
|
|
|
|
#define SPC5_SPI_DSPI0_IRQ_PRIO 10
|
|
|
|
|
#define SPC5_SPI_DSPI1_IRQ_PRIO 10
|
|
|
|
|
#define SPC5_SPI_DSPI2_IRQ_PRIO 10
|
|
|
|
|
#define SPC5_SPI_DSPI3_IRQ_PRIO 10
|
|
|
|
|
#define SPC5_SPI_DSPI4_IRQ_PRIO 10
|
|
|
|
|
#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
|
|
|
|
|
#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
|
|
|
|
SPC5_ME_PCTL_LP(2))
|
|
|
|
|
#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
|
|
|
|
SPC5_ME_PCTL_LP(0))
|
|
|
|
|
#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
|
|
|
|
SPC5_ME_PCTL_LP(2))
|
|
|
|
|
#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
|
|
|
|
SPC5_ME_PCTL_LP(0))
|
|
|
|
|
#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
|
|
|
|
SPC5_ME_PCTL_LP(2))
|
|
|
|
|
#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
|
|
|
|
SPC5_ME_PCTL_LP(0))
|
|
|
|
|
#define SPC5_SPI_DSPI3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
|
|
|
|
SPC5_ME_PCTL_LP(2))
|
|
|
|
|
#define SPC5_SPI_DSPI3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
|
|
|
|
SPC5_ME_PCTL_LP(0))
|
|
|
|
|
#define SPC5_SPI_DSPI4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
|
|
|
|
|
SPC5_ME_PCTL_LP(2))
|
|
|
|
|
#define SPC5_SPI_DSPI4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
|
|
|
|
|
SPC5_ME_PCTL_LP(0))
|
