2015-09-28 10:38:41 +00:00
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/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32L1xx/hal_lld.h
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* @brief STM32L1xx HAL subsystem low level driver header.
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* @pre This module requires the following macros to be defined in the
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* @p board.h file:
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* - STM32_LSECLK.
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2015-10-05 15:18:23 +00:00
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* - STM32_LSEDRV.
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* - STM32_LSE_BYPASS (optionally).
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2015-09-28 10:38:41 +00:00
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* - STM32_HSECLK.
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* - STM32_HSE_BYPASS (optionally).
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* .
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* One of the following macros must also be defined:
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2015-10-05 15:18:23 +00:00
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* - STM32L471xx, STM32L475xx, STM32L476xx.
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* - STM32L485xx, STM32L486xx.
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2015-09-28 10:38:41 +00:00
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* .
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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#include "stm32_registry.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name Platform identification
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* @{
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*/
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2015-10-05 15:18:23 +00:00
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#if defined(STM32L471xx) || defined(STM32L475xx) || \
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defined(STM32L476xx) || defined(__DOXYGEN__)
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#define PLATFORM_NAME "STM32L4xx Ultra Low Power"
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2015-09-28 10:38:41 +00:00
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2015-10-05 15:18:23 +00:00
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#elif defined(STM32L485xx) || defined(STM32L486xx)
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#define PLATFORM_NAME "STM32L4xx Ultra Low Power with Crypto"
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2015-09-28 10:38:41 +00:00
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#else
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2015-10-05 15:18:23 +00:00
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#error "STM32L4xx device not specified"
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2015-09-28 10:38:41 +00:00
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#endif
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/**
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* @brief Sub-family identifier.
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*/
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2015-10-05 15:18:23 +00:00
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#if !defined(STM32L4XX) || defined(__DOXYGEN__)
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#define STM32L4XX
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2015-09-28 10:38:41 +00:00
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#endif
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/** @} */
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/**
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* @name Internal clock sources
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* @{
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*/
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#define STM32_HSICLK 16000000 /**< High speed internal clock. */
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#define STM32_LSICLK 38000 /**< Low speed internal clock. */
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/** @} */
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/**
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2015-10-05 15:18:23 +00:00
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* @name PWR_CR1 register bits definitions
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* @{
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*/
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#define STM32_VOS_MASK (3 << 9) /**< Core voltage mask. */
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#define STM32_VOS_RANGE1 (1 << 9) /**< Core voltage 1.8 Volts. */
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#define STM32_VOS_RANGE2 (2 << 9) /**< Core voltage 1.5 Volts. */
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/** @} */
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/**
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* @name PWR_CR2 register bits definitions
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2015-09-28 10:38:41 +00:00
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* @{
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*/
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2015-10-05 15:18:23 +00:00
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#define STM32_PLS_MASK (7 << 1) /**< PLS bits mask. */
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#define STM32_PLS_LEV0 (0 << 1) /**< PVD level 0. */
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#define STM32_PLS_LEV1 (1 << 1) /**< PVD level 1. */
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#define STM32_PLS_LEV2 (2 << 1) /**< PVD level 2. */
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#define STM32_PLS_LEV3 (3 << 1) /**< PVD level 3. */
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#define STM32_PLS_LEV4 (4 << 1) /**< PVD level 4. */
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#define STM32_PLS_LEV5 (5 << 1) /**< PVD level 5. */
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#define STM32_PLS_LEV6 (6 << 1) /**< PVD level 6. */
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#define STM32_PLS_EXT (7 << 1) /**< PVD level 7. */
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2015-09-28 10:38:41 +00:00
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/** @} */
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/**
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* @name RCC_CR register bits definitions
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* @{
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*/
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2015-10-05 15:18:23 +00:00
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#define STM32_MSIRANGE_MASK (15 << 4) /**< MSIRANGE field mask. */
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#define STM32_MSIRANGE_100K (0 << 4) /**< 100kHz nominal. */
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#define STM32_MSIRANGE_200K (1 << 4) /**< 200kHz nominal. */
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#define STM32_MSIRANGE_400K (2 << 4) /**< 400kHz nominal. */
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#define STM32_MSIRANGE_800K (3 << 4) /**< 800kHz nominal. */
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#define STM32_MSIRANGE_1M (4 << 4) /**< 1MHz nominal. */
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#define STM32_MSIRANGE_2M (5 << 4) /**< 2MHz nominal. */
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#define STM32_MSIRANGE_4M (6 << 4) /**< 4MHz nominal. */
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#define STM32_MSIRANGE_8M (7 << 4) /**< 8MHz nominal. */
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#define STM32_MSIRANGE_16M (8 << 4) /**< 16MHz nominal. */
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#define STM32_MSIRANGE_24M (9 << 4) /**< 24MHz nominal. */
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#define STM32_MSIRANGE_32M (10 << 4) /**< 32MHz nominal. */
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#define STM32_MSIRANGE_48M (11 << 4) /**< 48MHz nominal. */
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2015-09-28 10:38:41 +00:00
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/** @} */
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/**
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* @name RCC_CFGR register bits definitions
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* @{
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*/
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#define STM32_SW_MSI (0 << 0) /**< SYSCLK source is MSI. */
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2015-10-05 15:18:23 +00:00
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#define STM32_SW_HSI16 (1 << 0) /**< SYSCLK source is HSI. */
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2015-09-28 10:38:41 +00:00
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#define STM32_SW_HSE (2 << 0) /**< SYSCLK source is HSE. */
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#define STM32_SW_PLL (3 << 0) /**< SYSCLK source is PLL. */
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#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
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#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
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#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
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#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
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#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
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#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
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#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
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#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
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#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
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#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
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#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
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#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
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#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
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#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
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#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
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#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
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#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
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#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
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#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
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#define STM32_MCOSEL_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
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#define STM32_MCOSEL_SYSCLK (1 << 24) /**< SYSCLK on MCO pin. */
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2015-10-05 15:18:23 +00:00
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#define STM32_MCOSEL_MSI (2 << 24) /**< MSI clock on MCO pin. */
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#define STM32_MCOSEL_HSI16 (3 << 24) /**< HSI16 clock on MCO pin. */
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2015-09-28 10:38:41 +00:00
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#define STM32_MCOSEL_HSE (4 << 24) /**< HSE clock on MCO pin. */
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#define STM32_MCOSEL_PLL (5 << 24) /**< PLL clock on MCO pin. */
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#define STM32_MCOSEL_LSI (6 << 24) /**< LSI clock on MCO pin. */
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#define STM32_MCOSEL_LSE (7 << 24) /**< LSE clock on MCO pin. */
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#define STM32_MCOPRE_DIV1 (0 << 28) /**< MCO divided by 1. */
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#define STM32_MCOPRE_DIV2 (1 << 28) /**< MCO divided by 1. */
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#define STM32_MCOPRE_DIV4 (2 << 28) /**< MCO divided by 1. */
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#define STM32_MCOPRE_DIV8 (3 << 28) /**< MCO divided by 1. */
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#define STM32_MCOPRE_DIV16 (4 << 28) /**< MCO divided by 1. */
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/** @} */
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/**
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2015-10-05 15:18:23 +00:00
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* @name RCC_PLLCFGR register bits definitions
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2015-09-28 10:38:41 +00:00
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* @{
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*/
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2015-10-05 15:18:23 +00:00
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#define STM32_PLLSRC_MASK (3 << 16) /**< PLL clock source mask. */
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#define STM32_PLLSRC_NOCLOCK (0 << 16) /**< PLL clock source disabled. */
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#define STM32_PLLSRC_MSI (1 << 16) /**< PLL clock source is MSI. */
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#define STM32_PLLSRC_HSI16 (2 << 16) /**< PLL clock source is HSI16. */
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#define STM32_PLLSRC_HSE (3 << 16) /**< PLL clock source is HSE. */
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/** @} */
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/**
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* @name RCC_BDCR register bits definitions
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* @{
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*/
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#define STM32_RTCSEL_MASK (3 << 8) /**< RTC source mask. */
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#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No RTC source. */
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#define STM32_RTCSEL_LSE (1 << 8) /**< RTC source is LSE. */
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#define STM32_RTCSEL_LSI (2 << 8) /**< RTC source is LSI. */
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#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */
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2015-09-28 10:38:41 +00:00
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/** @} */
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/**
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* @name RCC_CSR register bits definitions
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* @{
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*/
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2015-10-05 15:18:23 +00:00
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#define STM32_MSISRANGE_MASK (15 << 8) /**< MSISRANGE field mask. */
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#define STM32_MSISRANGE_1M (4 << 8) /**< 1MHz nominal. */
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#define STM32_MSISRANGE_2M (5 << 8) /**< 2MHz nominal. */
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#define STM32_MSISRANGE_4M (6 << 8) /**< 4MHz nominal. */
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#define STM32_MSISRANGE_8M (7 << 8) /**< 8MHz nominal. */
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2015-09-28 10:38:41 +00:00
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief Disables the PWR/RCC initialization in the HAL.
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*/
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#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
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#define STM32_NO_INIT FALSE
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#endif
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/**
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* @brief Core voltage selection.
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* @note This setting affects all the performance and clock related
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* settings, the maximum performance is only obtainable selecting
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* the maximum voltage.
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*/
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#if !defined(STM32_VOS) || defined(__DOXYGEN__)
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#define STM32_VOS STM32_VOS_1P8
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#endif
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/**
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* @brief Enables or disables the programmable voltage detector.
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*/
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#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
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#define STM32_PVD_ENABLE FALSE
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#endif
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/**
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* @brief Sets voltage level for programmable voltage detector.
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*/
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#if !defined(STM32_PLS) || defined(__DOXYGEN__)
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#define STM32_PLS STM32_PLS_LEV0
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#endif
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/**
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* @brief Enables or disables the HSI clock source.
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*/
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#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
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#define STM32_HSI_ENABLED TRUE
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#endif
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/**
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* @brief Enables or disables the LSI clock source.
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*/
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#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
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#define STM32_LSI_ENABLED TRUE
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#endif
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/**
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* @brief Enables or disables the HSE clock source.
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*/
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#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
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#define STM32_HSE_ENABLED FALSE
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#endif
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/**
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* @brief Enables or disables the LSE clock source.
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*/
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#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
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#define STM32_LSE_ENABLED FALSE
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#endif
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/**
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* @brief ADC clock setting.
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*/
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#if !defined(STM32_ADC_CLOCK_ENABLED) || defined(__DOXYGEN__)
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#define STM32_ADC_CLOCK_ENABLED TRUE
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#endif
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/**
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* @brief USB clock setting.
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*/
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#if !defined(STM32_USB_CLOCK_ENABLED) || defined(__DOXYGEN__)
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#define STM32_USB_CLOCK_ENABLED TRUE
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#endif
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/**
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* @brief MSI frequency setting.
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*/
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#if !defined(STM32_MSIRANGE) || defined(__DOXYGEN__)
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#define STM32_MSIRANGE STM32_MSIRANGE_2M
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Main clock source selection.
|
|
|
|
|
* @note If the selected clock source is not the PLL then the PLL is not
|
|
|
|
|
* initialized and started.
|
|
|
|
|
* @note The default value is calculated for a 32MHz system clock from
|
|
|
|
|
* the internal 16MHz HSI clock.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(STM32_SW) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_SW STM32_SW_PLL
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Clock source for the PLL.
|
|
|
|
|
* @note This setting has only effect if the PLL is selected as the
|
|
|
|
|
* system clock source.
|
|
|
|
|
* @note The default value is calculated for a 32MHz system clock from
|
|
|
|
|
* the internal 16MHz HSI clock.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
|
2015-10-05 15:18:23 +00:00
|
|
|
#define STM32_PLLSRC STM32_PLLSRC_HSI16
|
2015-09-28 10:38:41 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief PLL multiplier value.
|
|
|
|
|
* @note The allowed values are 3, 4, 6, 8, 12, 16, 32, 48.
|
|
|
|
|
* @note The default value is calculated for a 32MHz system clock from
|
|
|
|
|
* the internal 16MHz HSI clock.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_PLLMUL_VALUE 6
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief PLL divider value.
|
|
|
|
|
* @note The allowed values are 2, 3, 4.
|
|
|
|
|
* @note The default value is calculated for a 32MHz system clock from
|
|
|
|
|
* the internal 16MHz HSI clock.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(STM32_PLLDIV_VALUE) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_PLLDIV_VALUE 3
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief AHB prescaler value.
|
|
|
|
|
* @note The default value is calculated for a 32MHz system clock from
|
|
|
|
|
* the internal 16MHz HSI clock.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_HPRE STM32_HPRE_DIV1
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief APB1 prescaler value.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_PPRE1 STM32_PPRE1_DIV1
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief APB2 prescaler value.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_PPRE2 STM32_PPRE2_DIV1
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief MCO clock source.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief MCO divider setting.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(STM32_MCOPRE) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_MCOPRE STM32_MCOPRE_DIV1
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief RTC/LCD clock source.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_RTCSEL STM32_RTCSEL_LSE
|
|
|
|
|
#endif
|
|
|
|
|
/** @} */
|
|
|
|
|
|
|
|
|
|
/*===========================================================================*/
|
|
|
|
|
/* Derived constants and error checks. */
|
|
|
|
|
/*===========================================================================*/
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Configuration-related checks.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(STM32L1xx_MCUCONF)
|
|
|
|
|
#error "Using a wrong mcuconf.h file, STM32L1xx_MCUCONF not defined"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* Voltage related limits.*/
|
|
|
|
|
#if (STM32_VOS == STM32_VOS_1P8) || defined(__DOXYGEN__)
|
|
|
|
|
/**
|
|
|
|
|
* @brief Maximum HSE clock frequency at current voltage setting.
|
|
|
|
|
*/
|
|
|
|
|
#define STM32_HSECLK_MAX 32000000
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Maximum SYSCLK clock frequency at current voltage setting.
|
|
|
|
|
*/
|
|
|
|
|
#define STM32_SYSCLK_MAX 32000000
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Maximum VCO clock frequency at current voltage setting.
|
|
|
|
|
*/
|
|
|
|
|
#define STM32_PLLVCO_MAX 96000000
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Minimum VCO clock frequency at current voltage setting.
|
|
|
|
|
*/
|
|
|
|
|
#define STM32_PLLVCO_MIN 6000000
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Maximum APB1 clock frequency.
|
|
|
|
|
*/
|
|
|
|
|
#define STM32_PCLK1_MAX 32000000
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Maximum APB2 clock frequency.
|
|
|
|
|
*/
|
|
|
|
|
#define STM32_PCLK2_MAX 32000000
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Maximum frequency not requiring a wait state for flash accesses.
|
|
|
|
|
*/
|
|
|
|
|
#define STM32_0WS_THRESHOLD 16000000
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief HSI availability at current voltage settings.
|
|
|
|
|
*/
|
|
|
|
|
#define STM32_HSI_AVAILABLE TRUE
|
|
|
|
|
|
|
|
|
|
#elif STM32_VOS == STM32_VOS_1P5
|
|
|
|
|
#define STM32_HSECLK_MAX 16000000
|
|
|
|
|
#define STM32_SYSCLK_MAX 16000000
|
|
|
|
|
#define STM32_PLLVCO_MAX 48000000
|
|
|
|
|
#define STM32_PLLVCO_MIN 6000000
|
|
|
|
|
#define STM32_PCLK1_MAX 16000000
|
|
|
|
|
#define STM32_PCLK2_MAX 16000000
|
|
|
|
|
#define STM32_0WS_THRESHOLD 8000000
|
|
|
|
|
#define STM32_HSI_AVAILABLE TRUE
|
|
|
|
|
#elif STM32_VOS == STM32_VOS_1P2
|
|
|
|
|
#define STM32_HSECLK_MAX 4000000
|
|
|
|
|
#define STM32_SYSCLK_MAX 4000000
|
|
|
|
|
#define STM32_PLLVCO_MAX 24000000
|
|
|
|
|
#define STM32_PLLVCO_MIN 6000000
|
|
|
|
|
#define STM32_PCLK1_MAX 4000000
|
|
|
|
|
#define STM32_PCLK2_MAX 4000000
|
|
|
|
|
#define STM32_0WS_THRESHOLD 2000000
|
|
|
|
|
#define STM32_HSI_AVAILABLE FALSE
|
|
|
|
|
#else
|
|
|
|
|
#error "invalid STM32_VOS value specified"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* HSI related checks.*/
|
|
|
|
|
#if STM32_HSI_ENABLED
|
|
|
|
|
#if !STM32_HSI_AVAILABLE
|
|
|
|
|
#error "impossible to activate HSI under the current voltage settings"
|
|
|
|
|
#endif
|
|
|
|
|
#else /* !STM32_HSI_ENABLED */
|
|
|
|
|
#if STM32_ADC_CLOCK_ENABLED || \
|
2015-10-05 15:18:23 +00:00
|
|
|
(STM32_SW == STM32_SW_HSI16) || \
|
2015-09-28 10:38:41 +00:00
|
|
|
((STM32_SW == STM32_SW_PLL) && \
|
2015-10-05 15:18:23 +00:00
|
|
|
(STM32_PLLSRC == STM32_PLLSRC_HSI16)) || \
|
|
|
|
|
(STM32_MCOSEL == STM32_MCOSEL_HSI16) || \
|
2015-09-28 10:38:41 +00:00
|
|
|
((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
|
2015-10-05 15:18:23 +00:00
|
|
|
(STM32_PLLSRC == STM32_PLLSRC_HSI16))
|
2015-09-28 10:38:41 +00:00
|
|
|
#error "required HSI clock is not enabled"
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* !STM32_HSI_ENABLED */
|
|
|
|
|
|
|
|
|
|
/* HSE related checks.*/
|
|
|
|
|
#if STM32_HSE_ENABLED
|
|
|
|
|
#if STM32_HSECLK == 0
|
|
|
|
|
#error "impossible to activate HSE"
|
|
|
|
|
#endif
|
|
|
|
|
#if (STM32_HSECLK < 1000000) || (STM32_HSECLK > STM32_HSECLK_MAX)
|
|
|
|
|
#error "STM32_HSECLK outside acceptable range (1MHz...STM32_HSECLK_MAX)"
|
|
|
|
|
#endif
|
|
|
|
|
#else /* !STM32_HSE_ENABLED */
|
|
|
|
|
#if (STM32_SW == STM32_SW_HSE) || \
|
|
|
|
|
((STM32_SW == STM32_SW_PLL) && \
|
|
|
|
|
(STM32_PLLSRC == STM32_PLLSRC_HSE)) || \
|
|
|
|
|
(STM32_MCOSEL == STM32_MCOSEL_HSE) || \
|
|
|
|
|
((STM32_MCOSEL == STM32_MCOSEL_PLL) && \
|
|
|
|
|
(STM32_PLLSRC == STM32_PLLSRC_HSE)) || \
|
|
|
|
|
(STM32_RTCSEL == STM32_RTCSEL_HSEDIV)
|
|
|
|
|
#error "required HSE clock is not enabled"
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* !STM32_HSE_ENABLED */
|
|
|
|
|
|
|
|
|
|
/* LSI related checks.*/
|
|
|
|
|
#if STM32_LSI_ENABLED
|
|
|
|
|
#else /* !STM32_LSI_ENABLED */
|
|
|
|
|
|
|
|
|
|
#if STM32_MCOSEL == STM32_MCOSEL_LSI
|
|
|
|
|
#error "LSI not enabled, required by STM32_MCOSEL"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#if STM32_RTCSEL == STM32_RTCSEL_LSI
|
|
|
|
|
#error "LSI not enabled, required by STM32_RTCSEL"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#endif /* !STM32_LSI_ENABLED */
|
|
|
|
|
|
|
|
|
|
/* LSE related checks.*/
|
|
|
|
|
#if STM32_LSE_ENABLED
|
|
|
|
|
#if (STM32_LSECLK == 0)
|
|
|
|
|
#error "impossible to activate LSE"
|
|
|
|
|
#endif
|
|
|
|
|
#if (STM32_LSECLK < 1000) || (STM32_LSECLK > 1000000)
|
|
|
|
|
#error "STM32_LSECLK outside acceptable range (1...1000kHz)"
|
|
|
|
|
#endif
|
|
|
|
|
#else /* !STM32_LSE_ENABLED */
|
|
|
|
|
|
|
|
|
|
#if STM32_MCOSEL == STM32_MCOSEL_LSE
|
|
|
|
|
#error "LSE not enabled, required by STM32_MCOSEL"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#if STM32_RTCSEL == STM32_RTCSEL_LSE
|
|
|
|
|
#error "LSE not enabled, required by STM32_RTCSEL"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#endif /* !STM32_LSE_ENABLED */
|
|
|
|
|
|
|
|
|
|
/* PLL related checks.*/
|
|
|
|
|
#if STM32_USB_CLOCK_ENABLED || \
|
|
|
|
|
(STM32_SW == STM32_SW_PLL) || \
|
|
|
|
|
(STM32_MCOSEL == STM32_MCOSEL_PLL) || \
|
|
|
|
|
defined(__DOXYGEN__)
|
|
|
|
|
/**
|
|
|
|
|
* @brief PLL activation flag.
|
|
|
|
|
*/
|
|
|
|
|
#define STM32_ACTIVATE_PLL TRUE
|
|
|
|
|
#else
|
|
|
|
|
#define STM32_ACTIVATE_PLL FALSE
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief PLLMUL field.
|
|
|
|
|
*/
|
|
|
|
|
#if (STM32_PLLMUL_VALUE == 3) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_PLLMUL (0 << 18)
|
|
|
|
|
#elif STM32_PLLMUL_VALUE == 4
|
|
|
|
|
#define STM32_PLLMUL (1 << 18)
|
|
|
|
|
#elif STM32_PLLMUL_VALUE == 6
|
|
|
|
|
#define STM32_PLLMUL (2 << 18)
|
|
|
|
|
#elif STM32_PLLMUL_VALUE == 8
|
|
|
|
|
#define STM32_PLLMUL (3 << 18)
|
|
|
|
|
#elif STM32_PLLMUL_VALUE == 12
|
|
|
|
|
#define STM32_PLLMUL (4 << 18)
|
|
|
|
|
#elif STM32_PLLMUL_VALUE == 16
|
|
|
|
|
#define STM32_PLLMUL (5 << 18)
|
|
|
|
|
#elif STM32_PLLMUL_VALUE == 24
|
|
|
|
|
#define STM32_PLLMUL (6 << 18)
|
|
|
|
|
#elif STM32_PLLMUL_VALUE == 32
|
|
|
|
|
#define STM32_PLLMUL (7 << 18)
|
|
|
|
|
#elif STM32_PLLMUL_VALUE == 48
|
|
|
|
|
#define STM32_PLLMUL (8 << 18)
|
|
|
|
|
#else
|
|
|
|
|
#error "invalid STM32_PLLMUL_VALUE value specified"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief PLLDIV field.
|
|
|
|
|
*/
|
|
|
|
|
#if (STM32_PLLDIV_VALUE == 2) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_PLLDIV (1 << 22)
|
|
|
|
|
#elif STM32_PLLDIV_VALUE == 3
|
|
|
|
|
#define STM32_PLLDIV (2 << 22)
|
|
|
|
|
#elif STM32_PLLDIV_VALUE == 4
|
|
|
|
|
#define STM32_PLLDIV (3 << 22)
|
|
|
|
|
#else
|
|
|
|
|
#error "invalid STM32_PLLDIV_VALUE value specified"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief PLL input clock frequency.
|
|
|
|
|
*/
|
|
|
|
|
#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_PLLCLKIN STM32_HSECLK
|
2015-10-05 15:18:23 +00:00
|
|
|
#elif STM32_PLLSRC == STM32_PLLSRC_HSI16
|
2015-09-28 10:38:41 +00:00
|
|
|
#define STM32_PLLCLKIN STM32_HSICLK
|
|
|
|
|
#else
|
|
|
|
|
#error "invalid STM32_PLLSRC value specified"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* PLL input frequency range check.*/
|
|
|
|
|
#if (STM32_PLLCLKIN < 2000000) || (STM32_PLLCLKIN > 24000000)
|
|
|
|
|
#error "STM32_PLLCLKIN outside acceptable range (2...24MHz)"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief PLL VCO frequency.
|
|
|
|
|
*/
|
|
|
|
|
#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
|
|
|
|
|
|
|
|
|
|
/* PLL output frequency range check.*/
|
|
|
|
|
#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX)
|
|
|
|
|
#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief PLL output clock frequency.
|
|
|
|
|
*/
|
|
|
|
|
#define STM32_PLLCLKOUT (STM32_PLLVCO / STM32_PLLDIV_VALUE)
|
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|
/* PLL output frequency range check.*/
|
|
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|
#if (STM32_PLLCLKOUT < 2000000) || (STM32_PLLCLKOUT > 32000000)
|
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|
|
#error "STM32_PLLCLKOUT outside acceptable range (2...32MHz)"
|
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|
|
#endif
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|
/**
|
|
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|
* @brief MSI frequency.
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|
* @note Values are taken from the STM8Lxx datasheet.
|
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|
*/
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|
#if STM32_MSIRANGE == STM32_MSIRANGE_64K
|
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|
#define STM32_MSICLK 65500
|
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|
#elif STM32_MSIRANGE == STM32_MSIRANGE_128K
|
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|
#define STM32_MSICLK 131000
|
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|
#elif STM32_MSIRANGE == STM32_MSIRANGE_256K
|
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#define STM32_MSICLK 262000
|
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#elif STM32_MSIRANGE == STM32_MSIRANGE_512K
|
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|
#define STM32_MSICLK 524000
|
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|
#elif STM32_MSIRANGE == STM32_MSIRANGE_1M
|
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|
#define STM32_MSICLK 1050000
|
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|
#elif STM32_MSIRANGE == STM32_MSIRANGE_2M
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#define STM32_MSICLK 2100000
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#elif STM32_MSIRANGE == STM32_MSIRANGE_4M
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|
#define STM32_MSICLK 4200000
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#else
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|
#error "invalid STM32_MSIRANGE value specified"
|
|
|
|
|
#endif
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|
/**
|
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|
* @brief System clock source.
|
|
|
|
|
*/
|
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|
|
#if STM32_NO_INIT || defined(__DOXYGEN__)
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|
|
#define STM32_SYSCLK 2100000
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|
|
#elif (STM32_SW == STM32_SW_MSI)
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|
|
#define STM32_SYSCLK STM32_MSICLK
|
2015-10-05 15:18:23 +00:00
|
|
|
#elif (STM32_SW == STM32_SW_HSI16)
|
2015-09-28 10:38:41 +00:00
|
|
|
#define STM32_SYSCLK STM32_HSICLK
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|
|
#elif (STM32_SW == STM32_SW_HSE)
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|
|
#define STM32_SYSCLK STM32_HSECLK
|
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|
|
#elif (STM32_SW == STM32_SW_PLL)
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|
|
|
#define STM32_SYSCLK STM32_PLLCLKOUT
|
|
|
|
|
#else
|
|
|
|
|
#error "invalid STM32_SW value specified"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* Check on the system clock.*/
|
|
|
|
|
#if STM32_SYSCLK > STM32_SYSCLK_MAX
|
|
|
|
|
#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief AHB frequency.
|
|
|
|
|
*/
|
|
|
|
|
#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_HCLK (STM32_SYSCLK / 1)
|
|
|
|
|
#elif STM32_HPRE == STM32_HPRE_DIV2
|
|
|
|
|
#define STM32_HCLK (STM32_SYSCLK / 2)
|
|
|
|
|
#elif STM32_HPRE == STM32_HPRE_DIV4
|
|
|
|
|
#define STM32_HCLK (STM32_SYSCLK / 4)
|
|
|
|
|
#elif STM32_HPRE == STM32_HPRE_DIV8
|
|
|
|
|
#define STM32_HCLK (STM32_SYSCLK / 8)
|
|
|
|
|
#elif STM32_HPRE == STM32_HPRE_DIV16
|
|
|
|
|
#define STM32_HCLK (STM32_SYSCLK / 16)
|
|
|
|
|
#elif STM32_HPRE == STM32_HPRE_DIV64
|
|
|
|
|
#define STM32_HCLK (STM32_SYSCLK / 64)
|
|
|
|
|
#elif STM32_HPRE == STM32_HPRE_DIV128
|
|
|
|
|
#define STM32_HCLK (STM32_SYSCLK / 128)
|
|
|
|
|
#elif STM32_HPRE == STM32_HPRE_DIV256
|
|
|
|
|
#define STM32_HCLK (STM32_SYSCLK / 256)
|
|
|
|
|
#elif STM32_HPRE == STM32_HPRE_DIV512
|
|
|
|
|
#define STM32_HCLK (STM32_SYSCLK / 512)
|
|
|
|
|
#else
|
|
|
|
|
#error "invalid STM32_HPRE value specified"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* AHB frequency check.*/
|
|
|
|
|
#if STM32_HCLK > STM32_SYSCLK_MAX
|
|
|
|
|
#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief APB1 frequency.
|
|
|
|
|
*/
|
|
|
|
|
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_PCLK1 (STM32_HCLK / 1)
|
|
|
|
|
#elif STM32_PPRE1 == STM32_PPRE1_DIV2
|
|
|
|
|
#define STM32_PCLK1 (STM32_HCLK / 2)
|
|
|
|
|
#elif STM32_PPRE1 == STM32_PPRE1_DIV4
|
|
|
|
|
#define STM32_PCLK1 (STM32_HCLK / 4)
|
|
|
|
|
#elif STM32_PPRE1 == STM32_PPRE1_DIV8
|
|
|
|
|
#define STM32_PCLK1 (STM32_HCLK / 8)
|
|
|
|
|
#elif STM32_PPRE1 == STM32_PPRE1_DIV16
|
|
|
|
|
#define STM32_PCLK1 (STM32_HCLK / 16)
|
|
|
|
|
#else
|
|
|
|
|
#error "invalid STM32_PPRE1 value specified"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* APB1 frequency check.*/
|
|
|
|
|
#if STM32_PCLK1 > STM32_PCLK1_MAX
|
|
|
|
|
#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief APB2 frequency.
|
|
|
|
|
*/
|
|
|
|
|
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_PCLK2 (STM32_HCLK / 1)
|
|
|
|
|
#elif STM32_PPRE2 == STM32_PPRE2_DIV2
|
|
|
|
|
#define STM32_PCLK2 (STM32_HCLK / 2)
|
|
|
|
|
#elif STM32_PPRE2 == STM32_PPRE2_DIV4
|
|
|
|
|
#define STM32_PCLK2 (STM32_HCLK / 4)
|
|
|
|
|
#elif STM32_PPRE2 == STM32_PPRE2_DIV8
|
|
|
|
|
#define STM32_PCLK2 (STM32_HCLK / 8)
|
|
|
|
|
#elif STM32_PPRE2 == STM32_PPRE2_DIV16
|
|
|
|
|
#define STM32_PCLK2 (STM32_HCLK / 16)
|
|
|
|
|
#else
|
|
|
|
|
#error "invalid STM32_PPRE2 value specified"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* APB2 frequency check.*/
|
|
|
|
|
#if STM32_PCLK2 > STM32_PCLK2_MAX
|
|
|
|
|
#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief MCO divider clock.
|
|
|
|
|
*/
|
|
|
|
|
#if (STM32_MCOSEL == STM32_MCOSEL_NOCLOCK) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_MCODIVCLK 0
|
2015-10-05 15:18:23 +00:00
|
|
|
#elif STM32_MCOSEL == STM32_MCOSEL_HSI16
|
2015-09-28 10:38:41 +00:00
|
|
|
#define STM32_MCODIVCLK STM32_HSICLK
|
|
|
|
|
#elif STM32_MCOSEL == STM32_MCOSEL_MSI
|
|
|
|
|
#define STM32_MCODIVCLK STM32_MSICLK
|
|
|
|
|
#elif STM32_MCOSEL == STM32_MCOSEL_HSE
|
|
|
|
|
#define STM32_MCODIVCLK STM32_HSECLK
|
|
|
|
|
#elif STM32_MCOSEL == STM32_MCOSEL_PLL
|
|
|
|
|
#define STM32_MCODIVCLK STM32_PLLCLKOUT
|
|
|
|
|
#elif STM32_MCOSEL == STM32_MCOSEL_LSI
|
|
|
|
|
#define STM32_MCODIVCLK STM32_LSICLK
|
|
|
|
|
#elif STM32_MCOSEL == STM32_MCOSEL_LSE
|
|
|
|
|
#define STM32_MCODIVCLK STM32_LSECLK
|
|
|
|
|
#else
|
|
|
|
|
#error "invalid STM32_MCOSEL value specified"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief MCO output pin clock.
|
|
|
|
|
*/
|
|
|
|
|
#if (STM32_MCOPRE == STM32_MCOPRE_DIV1) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_MCOCLK STM32_MCODIVCLK
|
|
|
|
|
#elif STM32_MCOPRE == STM32_MCOPRE_DIV2
|
|
|
|
|
#define STM32_MCOCLK (STM32_MCODIVCLK / 2)
|
|
|
|
|
#elif STM32_MCOPRE == STM32_MCOPRE_DIV4
|
|
|
|
|
#define STM32_MCOCLK (STM32_MCODIVCLK / 4)
|
|
|
|
|
#elif STM32_MCOPRE == STM32_MCOPRE_DIV8
|
|
|
|
|
#define STM32_MCOCLK (STM32_MCODIVCLK / 8)
|
|
|
|
|
#elif STM32_MCOPRE == STM32_MCOPRE_DIV16
|
|
|
|
|
#define STM32_MCOCLK (STM32_MCODIVCLK / 16)
|
|
|
|
|
#else
|
|
|
|
|
#error "invalid STM32_MCOPRE value specified"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief RTC/LCD clock.
|
|
|
|
|
*/
|
|
|
|
|
#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_RTCCLK 0
|
|
|
|
|
#elif STM32_RTCSEL == STM32_RTCSEL_LSE
|
|
|
|
|
#define STM32_RTCCLK STM32_LSECLK
|
|
|
|
|
#elif STM32_RTCSEL == STM32_RTCSEL_LSI
|
|
|
|
|
#define STM32_RTCCLK STM32_LSICLK
|
|
|
|
|
#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
|
2015-10-05 15:18:23 +00:00
|
|
|
#define STM32_RTCCLK (STM32_HSECLK / 32)
|
2015-09-28 10:38:41 +00:00
|
|
|
#else
|
|
|
|
|
#error "invalid STM32_RTCSEL value specified"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief USB frequency.
|
|
|
|
|
*/
|
|
|
|
|
#define STM32_USBCLK (STM32_PLLVCO / 2)
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Timers 2, 3, 4, 6, 7 clock.
|
|
|
|
|
*/
|
|
|
|
|
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
|
|
|
|
|
#else
|
|
|
|
|
#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Timers 9, 10, 11 clock.
|
|
|
|
|
*/
|
|
|
|
|
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
|
|
|
|
|
#else
|
|
|
|
|
#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Flash settings.
|
|
|
|
|
*/
|
|
|
|
|
#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_FLASHBITS1 0x00000000
|
|
|
|
|
#else
|
|
|
|
|
#define STM32_FLASHBITS1 0x00000004
|
|
|
|
|
#define STM32_FLASHBITS2 0x00000007
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/*===========================================================================*/
|
|
|
|
|
/* Driver data structures and types. */
|
|
|
|
|
/*===========================================================================*/
|
|
|
|
|
|
|
|
|
|
/*===========================================================================*/
|
|
|
|
|
/* Driver macros. */
|
|
|
|
|
/*===========================================================================*/
|
|
|
|
|
|
|
|
|
|
/*===========================================================================*/
|
|
|
|
|
/* External declarations. */
|
|
|
|
|
/*===========================================================================*/
|
|
|
|
|
|
|
|
|
|
/* Various helpers.*/
|
|
|
|
|
#include "nvic.h"
|
|
|
|
|
#include "stm32_isr.h"
|
|
|
|
|
#include "stm32_dma.h"
|
|
|
|
|
#include "stm32_rcc.h"
|
|
|
|
|
|
|
|
|
|
#ifdef __cplusplus
|
|
|
|
|
extern "C" {
|
|
|
|
|
#endif
|
|
|
|
|
void hal_lld_init(void);
|
|
|
|
|
void stm32_clock_init(void);
|
|
|
|
|
#ifdef __cplusplus
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#endif /* _HAL_LLD_H_ */
|
|
|
|
|
|
|
|
|
|
/** @} */
|
