405 lines
12 KiB
C
405 lines
12 KiB
C
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012,2013 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file PPC/chcore.h
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* @brief PowerPC architecture port macros and structures.
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*
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* @addtogroup PPC_CORE
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* @{
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*/
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#ifndef _CHCORE_H_
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#define _CHCORE_H_
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#if CH_DBG_ENABLE_STACK_CHECK
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#error "option CH_DBG_ENABLE_STACK_CHECK not supported by this port"
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#endif
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/*===========================================================================*/
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/* Port constants (common). */
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/*===========================================================================*/
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/* Added to make the header stand-alone when included from asm.*/
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#ifndef FALSE
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#define FALSE 0
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#endif
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#ifndef TRUE
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#define TRUE (!FALSE)
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#endif
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/**
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* @name Supported core variants
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* @{
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*/
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#define PPC_VARIANT_e200z0 200
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#define PPC_VARIANT_e200z3 203
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#define PPC_VARIANT_e200z4 204
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/** @} */
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#include "vectors.h"
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#include "ppcparams.h"
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/*===========================================================================*/
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/* Port macros (common). */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Port configurable parameters (common). */
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/*===========================================================================*/
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/**
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* @brief Use VLE instruction set.
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* @note This parameter is usually set in the Makefile.
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*/
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#if !defined(PPC_USE_VLE)
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#define PPC_USE_VLE TRUE
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#endif
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/**
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* @brief Enables the use of the @p WFI instruction.
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*/
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#if !defined(PPC_ENABLE_WFI_IDLE)
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#define PPC_ENABLE_WFI_IDLE FALSE
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#endif
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/*===========================================================================*/
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/* Port derived parameters (common). */
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/*===========================================================================*/
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#if PPC_USE_VLE && !PPC_SUPPORTS_VLE
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#error "the selected MCU does not support VLE instructions set"
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#endif
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#if !PPC_USE_VLE && !PPC_SUPPORTS_BOOKE
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#error "the selected MCU does not support BookE instructions set"
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#endif
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/*===========================================================================*/
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/* Port exported info (common). */
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/*===========================================================================*/
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/**
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* @brief Unique macro for the implemented architecture.
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*/
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#define CH_ARCHITECTURE_PPC
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/**
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* @brief Name of the implemented architecture.
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*/
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#define CH_ARCHITECTURE_NAME "Power Architecture"
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/**
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* @brief Name of the architecture variant.
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*/
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#if (PPC_VARIANT == PPC_VARIANT_e200z0) || defined(__DOXYGEN__)
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#define CH_CORE_VARIANT_NAME "e200z0"
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#elif PPC_VARIANT == PPC_VARIANT_e200z3
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#define CH_CORE_VARIANT_NAME "e200z3"
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#elif PPC_VARIANT == PPC_VARIANT_e200z4
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#define CH_CORE_VARIANT_NAME "e200z4"
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#else
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#error "unknown or unsupported PowerPC variant specified"
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#endif
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/**
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* @brief Name of the compiler supported by this port.
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*/
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#define CH_COMPILER_NAME "GCC " __VERSION__
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/**
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* @brief Port-specific information string.
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*/
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#if PPC_USE_VLE
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#define CH_PORT_INFO "VLE mode"
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#else
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#define CH_PORT_INFO "Book-E mode"
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#endif
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/*===========================================================================*/
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/* Port implementation part (common). */
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/*===========================================================================*/
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#if !defined(_FROM_ASM_)
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/**
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* @brief Base type for stack and memory alignment.
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*/
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typedef struct {
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uint8_t a[8];
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} stkalign_t __attribute__((aligned(8)));
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/**
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* @brief Generic PPC register.
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*/
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typedef void *regppc_t;
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/**
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* @brief Mandatory part of a stack frame.
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*/
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struct eabi_frame {
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regppc_t slink; /**< Stack back link. */
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regppc_t shole; /**< Stack hole for LR storage. */
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};
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/**
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* @brief Interrupt saved context.
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* @details This structure represents the stack frame saved during a
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* preemption-capable interrupt handler.
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* @note R2 and R13 are not saved because those are assumed to be immutable
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* during the system life cycle.
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*/
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struct extctx {
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struct eabi_frame frame;
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/* Start of the e_stmvsrrw frame (offset 8).*/
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regppc_t pc;
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regppc_t msr;
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/* Start of the e_stmvsprw frame (offset 16).*/
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regppc_t cr;
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regppc_t lr;
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regppc_t ctr;
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regppc_t xer;
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/* Start of the e_stmvgprw frame (offset 32).*/
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regppc_t r0;
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regppc_t r3;
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regppc_t r4;
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regppc_t r5;
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regppc_t r6;
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regppc_t r7;
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regppc_t r8;
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regppc_t r9;
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regppc_t r10;
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regppc_t r11;
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regppc_t r12;
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regppc_t padding;
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};
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/**
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* @brief System saved context.
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* @details This structure represents the inner stack frame during a context
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* switching.
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* @note R2 and R13 are not saved because those are assumed to be immutable
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* during the system life cycle.
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* @note LR is stored in the caller contex so it is not present in this
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* structure.
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*/
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struct intctx {
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regppc_t cr; /* Part of it is not volatile... */
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regppc_t r14;
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regppc_t r15;
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regppc_t r16;
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regppc_t r17;
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regppc_t r18;
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regppc_t r19;
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regppc_t r20;
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regppc_t r21;
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regppc_t r22;
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regppc_t r23;
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regppc_t r24;
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regppc_t r25;
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regppc_t r26;
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regppc_t r27;
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regppc_t r28;
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regppc_t r29;
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regppc_t r30;
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regppc_t r31;
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regppc_t padding;
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};
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/**
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* @brief Platform dependent part of the @p Thread structure.
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* @details This structure usually contains just the saved stack pointer
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* defined as a pointer to a @p intctx structure.
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*/
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struct context {
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struct intctx *sp;
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};
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/**
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* @brief Platform dependent part of the @p chThdCreateI() API.
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* @details This code usually setup the context switching frame represented
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* by an @p intctx structure.
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*/
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#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
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uint8_t *sp = (uint8_t *)workspace + wsize - sizeof(struct eabi_frame); \
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((struct eabi_frame *)sp)->slink = 0; \
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((struct eabi_frame *)sp)->shole = _port_thread_start; \
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tp->p_ctx.sp = (struct intctx *)(sp - sizeof(struct intctx)); \
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tp->p_ctx.sp->r31 = arg; \
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tp->p_ctx.sp->r30 = pf; \
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}
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/**
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* @brief Stack size for the system idle thread.
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* @details This size depends on the idle thread implementation, usually
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* the idle thread should take no more space than those reserved
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* by @p PORT_INT_REQUIRED_STACK.
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*/
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#ifndef PORT_IDLE_THREAD_STACK_SIZE
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#define PORT_IDLE_THREAD_STACK_SIZE 32
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#endif
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/**
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* @brief Per-thread stack overhead for interrupts servicing.
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* @details This constant is used in the calculation of the correct working
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* area size.
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*/
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#ifndef PORT_INT_REQUIRED_STACK
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#define PORT_INT_REQUIRED_STACK 256
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#endif
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/**
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* @brief Enforces a correct alignment for a stack area size value.
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*/
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#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
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/**
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* @brief Computes the thread working area global size.
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*/
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#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
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sizeof(struct intctx) + \
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sizeof(struct extctx) + \
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(n) + (PORT_INT_REQUIRED_STACK))
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/**
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* @brief Static working area allocation.
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* @details This macro is used to allocate a static thread working area
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* aligned as both position and size.
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*/
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#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
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/**
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* @brief IRQ prologue code.
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* @details This macro must be inserted at the start of all IRQ handlers
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* enabled to invoke system APIs.
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*/
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#define PORT_IRQ_PROLOGUE()
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/**
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* @brief IRQ epilogue code.
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* @details This macro must be inserted at the end of all IRQ handlers
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* enabled to invoke system APIs.
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*/
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#define PORT_IRQ_EPILOGUE()
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/**
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* @brief IRQ handler function declaration.
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* @note @p id can be a function name or a vector number depending on the
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* port implementation.
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*/
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#define PORT_IRQ_HANDLER(id) void id(void)
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/**
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* @details Implemented as global interrupt disable.
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*/
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#define port_lock() asm volatile ("wrteei 0" : : : "memory")
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/**
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* @details Implemented as global interrupt enable.
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*/
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#define port_unlock() asm volatile("wrteei 1" : : : "memory")
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/**
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* @details Implemented as global interrupt disable.
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*/
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#define port_lock_from_isr() /*asm ("wrteei 0")*/
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/**
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* @details Implemented as global interrupt enable.
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*/
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#define port_unlock_from_isr() /*asm ("wrteei 1")*/
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/**
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* @details Implemented as global interrupt disable.
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*/
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#define port_disable() asm volatile ("wrteei 0" : : : "memory")
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/**
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* @details Same as @p port_disable() in this port, there is no difference
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* between the two states.
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*/
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#define port_suspend() asm volatile ("wrteei 0" : : : "memory")
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/**
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* @details Implemented as global interrupt enable.
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*/
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#define port_enable() asm volatile ("wrteei 1" : : : "memory")
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/**
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* @brief Performs a context switch between two threads.
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* @details This is the most critical code in any port, this function
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* is responsible for the context switch between 2 threads.
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* @note The implementation of this code affects <b>directly</b> the context
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* switch performance so optimize here as much as you can.
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*
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* @param[in] ntp the thread to be switched in
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* @param[in] otp the thread to be switched out
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*/
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#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
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#define port_switch(ntp, otp) _port_switch(ntp, otp)
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#else
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#define port_switch(ntp, otp) { \
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register struct intctx *sp asm ("%r1"); \
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if ((stkalign_t *)(sp - 1) < otp->p_stklimit) \
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chDbgPanic("stack overflow"); \
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_port_switch(ntp, otp); \
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}
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#endif
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/**
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* @brief Writes to a special register.
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*
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* @param[in] spr special register number
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* @param[in] val value to be written
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*/
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#define port_mtspr(spr, val) \
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asm volatile ("mtspr %0,%1" : : "n" (spr), "r" (val))
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/**
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* @details This port function is implemented as inlined code for performance
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* reasons.
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*/
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#if PPC_ENABLE_WFI_IDLE
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#if !defined(port_wait_for_interrupt)
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#define port_wait_for_interrupt() { \
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asm volatile ("wait" : : : "memory"); \
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}
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#endif
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#else
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#define port_wait_for_interrupt()
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#endif
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|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
extern "C" {
|
||
|
|
#endif
|
||
|
|
void port_init(void);
|
||
|
|
void port_halt(void);
|
||
|
|
void _port_switch(Thread *ntp, Thread *otp);
|
||
|
|
void _port_thread_start(void);
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* _FROM_ASM_ */
|
||
|
|
|
||
|
|
#endif /* _CHCORE_H_ */
|
||
|
|
|
||
|
|
/** @} */
|