2008-05-07 13:08:43 +00:00
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/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <ch.h>
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2009-06-14 13:10:38 +00:00
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#include <pal.h>
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2008-05-07 15:47:40 +00:00
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#include <signal.h>
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2008-05-07 13:08:43 +00:00
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#include "board.h"
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2008-10-12 10:04:26 +00:00
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#include "msp430_serial.h"
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2008-05-07 13:08:43 +00:00
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2009-06-21 08:52:44 +00:00
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/*
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2009-06-21 09:35:39 +00:00
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* Digital I/O ports static configuration as defined in @p board.h.
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2009-06-21 08:52:44 +00:00
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*/
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static const MSP430DIOConfig config =
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{
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2009-06-21 09:35:39 +00:00
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{VAL_P1OUT, VAL_P1DIR},
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{VAL_P2OUT, VAL_P2DIR},
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{VAL_P3OUT, VAL_P3DIR},
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{VAL_P4OUT, VAL_P4DIR},
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{VAL_P5OUT, VAL_P5DIR},
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{VAL_P6OUT, VAL_P6DIR},
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2009-06-21 08:52:44 +00:00
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};
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2008-05-07 13:08:43 +00:00
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/*
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* Hardware initialization goes here.
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* NOTE: Interrupts are still disabled.
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*/
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void hwinit(void) {
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2008-05-07 15:47:40 +00:00
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2008-05-08 10:12:19 +00:00
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/*
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* Clock sources setup.
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*/
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DCOCTL = VAL_DCOCTL;
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BCSCTL1 = VAL_BCSCTL1;
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2008-10-11 10:29:06 +00:00
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#if defined(MSP_USE_XT2CLK)
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do {
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int i;
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IFG1 &= ~OFIFG;
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for (i = 255; i > 0; i--)
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asm("nop");
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} while (IFG1 & OFIFG);
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#endif
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2008-05-08 10:12:19 +00:00
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BCSCTL2 = VAL_BCSCTL2;
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2008-05-07 15:47:40 +00:00
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/*
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2009-06-21 08:52:44 +00:00
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* I/O ports initialization.
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2008-05-07 15:47:40 +00:00
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*/
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2009-06-21 08:52:44 +00:00
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palInit(&config);
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2008-05-07 15:47:40 +00:00
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/*
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2008-05-08 15:32:09 +00:00
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* Timer 0 setup, uses SMCLK as source.
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2008-05-07 15:47:40 +00:00
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*/
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2008-10-14 21:03:26 +00:00
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TACCR0 = SMCLK / 4 / CH_FREQUENCY - 1;/* Counter limit. */
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2008-05-07 15:47:40 +00:00
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TACTL = TACLR; /* Clean start. */
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2008-10-14 21:03:26 +00:00
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TACTL = TASSEL_2 | ID_2 | MC_1; /* Src=SMCLK, ID=4, cmp=TACCR0. */
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2008-05-07 15:47:40 +00:00
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TACCTL0 = CCIE; /* Interrupt on compare. */
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2008-10-12 10:04:26 +00:00
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/*
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* Other subsystems.
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*/
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2009-02-06 22:07:17 +00:00
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serial_init();
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2008-05-07 15:47:40 +00:00
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}
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2009-01-19 20:56:24 +00:00
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CH_IRQ_HANDLER(TIMERA0_VECTOR) {
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2008-05-07 15:47:40 +00:00
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2009-01-10 16:21:27 +00:00
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CH_IRQ_PROLOGUE();
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2009-01-09 11:05:26 +00:00
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2009-01-24 17:59:51 +00:00
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chSysLockFromIsr();
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2008-05-07 15:47:40 +00:00
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chSysTimerHandlerI();
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2009-01-24 17:59:51 +00:00
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chSysUnlockFromIsr();
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2009-01-09 11:05:26 +00:00
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2009-01-10 16:21:27 +00:00
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CH_IRQ_EPILOGUE();
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2008-05-07 13:08:43 +00:00
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}
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