429 lines
14 KiB
C
429 lines
14 KiB
C
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/*
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32/LLD/ADCv1/adc_lld.h
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* @brief STM32 ADC subsystem low level driver header.
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*
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* @addtogroup ADC
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* @{
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*/
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#ifndef _ADC_LLD_H_
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#define _ADC_LLD_H_
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#if HAL_USE_ADC || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @name Sampling rates
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* @{
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*/
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#define ADC_SMPR_SMP_1P5 0U /**< @brief 14 cycles conversion time */
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#define ADC_SMPR_SMP_7P5 1U /**< @brief 21 cycles conversion time. */
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#define ADC_SMPR_SMP_13P5 2U /**< @brief 28 cycles conversion time. */
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#define ADC_SMPR_SMP_28P5 3U /**< @brief 41 cycles conversion time. */
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#define ADC_SMPR_SMP_41P5 4U /**< @brief 54 cycles conversion time. */
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#define ADC_SMPR_SMP_55P5 5U /**< @brief 68 cycles conversion time. */
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#define ADC_SMPR_SMP_71P5 6U /**< @brief 84 cycles conversion time. */
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#define ADC_SMPR_SMP_239P5 7U /**< @brief 252 cycles conversion time. */
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/** @} */
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/**
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* @name CFGR1 register configuration helpers
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* @{
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*/
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#define ADC_CFGR1_RES_12BIT (0U << 3U)
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#define ADC_CFGR1_RES_10BIT (1U << 3U)
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#define ADC_CFGR1_RES_8BIT (2U << 3U)
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#define ADC_CFGR1_RES_6BIT (3U << 3U)
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#define ADC_CFGR1_EXTSEL_MASK (15U << 6U)
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#define ADC_CFGR1_EXTSEL_SRC(n) ((n) << 6U)
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#define ADC_CFGR1_EXTEN_MASK (3U << 10U)
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#define ADC_CFGR1_EXTEN_DISABLED (0U << 10U)
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#define ADC_CFGR1_EXTEN_RISING (1U << 10U)
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#define ADC_CFGR1_EXTEN_FALLING (2U << 10U)
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#define ADC_CFGR1_EXTEN_BOTH (3U << 10U)
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/** @} */
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/**
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* @name CFGR2 register configuration helpers
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* @{
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*/
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#define STM32_ADC_CKMODE_MASK (3U << 30U)
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#define STM32_ADC_CKMODE_ADCCLK (0U << 30U)
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#define STM32_ADC_CKMODE_PCLK_DIV2 (1U << 30U)
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#define STM32_ADC_CKMODE_PCLK_DIV4 (2U << 30U)
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#define STM32_ADC_CKMODE_PCLK (3U << 30U)
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#if (STM32_ADC_SUPPORTS_OVERSAMPLING == TRUE) || defined(__DOXYGEN__)
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#define ADC_CFGR2_OVSR_MASK (7U << 2U)
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#define ADC_CFGR2_OVSR_2X (0U << 2U)
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#define ADC_CFGR2_OVSR_4X (1U << 2U)
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#define ADC_CFGR2_OVSR_8X (2U << 2U)
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#define ADC_CFGR2_OVSR_16X (3U << 2U)
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#define ADC_CFGR2_OVSR_32X (4U << 2U)
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#define ADC_CFGR2_OVSR_64X (5U << 2U)
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#define ADC_CFGR2_OVSR_128X (6U << 2U)
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#define ADC_CFGR2_OVSR_256X (7U << 2U)
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#define ADC_CFGR2_OVSS_MASK (15 << 5U)
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#define ADC_CFGR2_OVSS_SHIFT(n) ((n) << 5U)
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#endif
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/** @} */
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/**
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* @name Threashold register initializer
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* @{
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*/
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#define ADC_TR(low, high) (((uint32_t)(high) << 16U) | \
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(uint32_t)(low))
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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/**
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* @brief ADC1 driver enable switch.
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* @details If set to @p TRUE the support for ADC1 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
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#define STM32_ADC_USE_ADC1 FALSE
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#endif
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/**
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* @brief ADC1 DMA priority (0..3|lowest..highest).
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*/
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#if !defined(STM32_ADC_ADC1_DMA_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC1_DMA_PRIORITY 2
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#endif
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/**
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* @brief ADC interrupt priority level setting.
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*/
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#if !defined(STM32_ADC_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_IRQ_PRIORITY 2
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#endif
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/**
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* @brief ADC1 DMA interrupt priority level setting.
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*/
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#if !defined(STM32_ADC_ADC1_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 2
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#endif
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/**
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* @brief ADC clock source selection.
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*/
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#if !defined(STM32_ADC_CKMODE) || defined(__DOXYGEN__)
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#define STM32_ADC_CKMODE STM32_ADC_CKMODE_ADCCLK
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#endif
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#if (STM32_ADC_SUPPORTS_PRESCALER == TRUE) || defined(__DOXYGEN__)
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/**
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* @brief ADC prescaler setting.
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* @note This setting has effect only in asynchronous clock mode (the
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* default, @p STM32_ADC_CKMODE_ADCCLK).
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*/
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#if !defined(STM32_ADC_PRESCALER_VALUE) || defined(__DOXYGEN__)
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#define STM32_ADC_PRESCALER_VALUE 1
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#endif
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
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#error "ADC1 not present in the selected device"
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#endif
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#if !STM32_ADC_USE_ADC1
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#error "ADC driver activated but no ADC peripheral assigned"
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#endif
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#if STM32_ADC_USE_ADC1 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to ADC1"
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#endif
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#if STM32_ADC_USE_ADC1 && \
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!OSAL_IRQ_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_IRQ_PRIORITY)
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#error "Invalid IRQ priority assigned to ADC1 DMA"
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#endif
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#if STM32_ADC_USE_ADC1 && \
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!STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC1_DMA_PRIORITY)
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#error "Invalid DMA priority assigned to ADC1"
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#endif
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#if STM32_ADC_SUPPORTS_PRESCALER == TRUE
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#if STM32_ADC_PRESCALER_VALUE == 1
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#define STM32_ADC_PRESC 0U
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#elif STM32_ADC_PRESCALER_VALUE == 2
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#define STM32_ADC_PRESC 1U
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#elif STM32_ADC_PRESCALER_VALUE == 4
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#define STM32_ADC_PRESC 2U
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#elif STM32_ADC_PRESCALER_VALUE == 6
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#define STM32_ADC_PRESC 3U
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#elif STM32_ADC_PRESCALER_VALUE == 8
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#define STM32_ADC_PRESC 4U
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#elif STM32_ADC_PRESCALER_VALUE == 10
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#define STM32_ADC_PRESC 5U
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#elif STM32_ADC_PRESCALER_VALUE == 12
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#define STM32_ADC_PRESC 6U
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#elif STM32_ADC_PRESCALER_VALUE == 16
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#define STM32_ADC_PRESC 7U
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#elif STM32_ADC_PRESCALER_VALUE == 32
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#define STM32_ADC_PRESC 8U
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#elif STM32_ADC_PRESCALER_VALUE == 64
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#define STM32_ADC_PRESC 9U
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#elif STM32_ADC_PRESCALER_VALUE == 128
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#define STM32_ADC_PRESC 10U
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#elif STM32_ADC_PRESCALER_VALUE == 256
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#define STM32_ADC_PRESC 11U
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#else
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#error "Invalid value assigned to STM32_ADC_PRESCALER_VALUE"
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#endif
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#endif
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#if !defined(STM32_DMA_REQUIRED)
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#define STM32_DMA_REQUIRED
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief ADC sample data type.
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*/
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typedef uint16_t adcsample_t;
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/**
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* @brief Channels number in a conversion group.
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*/
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typedef uint16_t adc_channels_num_t;
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/**
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* @brief Possible ADC failure causes.
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* @note Error codes are architecture dependent and should not relied
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* upon.
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*/
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typedef enum {
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ADC_ERR_DMAFAILURE = 0, /**< DMA operations failure. */
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ADC_ERR_OVERFLOW = 1, /**< ADC overflow condition. */
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ADC_ERR_AWD = 2 /**< Analog watchdog triggered. */
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} adcerror_t;
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/**
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* @brief Type of a structure representing an ADC driver.
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*/
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typedef struct ADCDriver ADCDriver;
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/**
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* @brief ADC notification callback type.
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*
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* @param[in] adcp pointer to the @p ADCDriver object triggering the
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* callback
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* @param[in] buffer pointer to the most recent samples data
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* @param[in] n number of buffer rows available starting from @p buffer
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*/
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typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
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/**
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* @brief ADC error callback type.
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*
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* @param[in] adcp pointer to the @p ADCDriver object triggering the
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* callback
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* @param[in] err ADC error code
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*/
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typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
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/**
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* @brief Conversion group configuration structure.
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* @details This implementation-dependent structure describes a conversion
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* operation.
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* @note The use of this configuration structure requires knowledge of
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* STM32 ADC cell registers interface, please refer to the STM32
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* reference manual for details.
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*/
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typedef struct {
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/**
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* @brief Enables the circular buffer mode for the group.
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*/
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bool circular;
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/**
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* @brief Number of the analog channels belonging to the conversion group.
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*/
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adc_channels_num_t num_channels;
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/**
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* @brief Callback function associated to the group or @p NULL.
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*/
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adccallback_t end_cb;
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/**
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* @brief Error callback or @p NULL.
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*/
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adcerrorcallback_t error_cb;
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/* End of the mandatory fields.*/
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/**
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* @brief ADC CFGR1 register initialization data.
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* @note The bits DMAEN and DMACFG are enforced internally
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* to the driver, keep them to zero.
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* @note The bits @p ADC_CFGR1_CONT or @p ADC_CFGR1_DISCEN must be
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* specified in continuous more or if the buffer depth is
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* greater than one.
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*/
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uint32_t cfgr1;
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#if (STM32_ADC_SUPPORTS_OVERSAMPLING == TRUE) || defined(__DOXYGEN__)
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/**
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* @brief ADC CFGR2 register initialization data.
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* @note CKMODE bits must not be specified in this field and left to
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* zero.
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*/
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uint32_t cfgr2;
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#endif
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/**
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* @brief ADC TR register initialization data.
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*/
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uint32_t tr;
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/**
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* @brief ADC SMPR register initialization data.
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*/
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uint32_t smpr;
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/**
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* @brief ADC CHSELR register initialization data.
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* @details The number of bits at logic level one in this register must
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* be equal to the number in the @p num_channels field.
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*/
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uint32_t chselr;
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} ADCConversionGroup;
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/**
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* @brief Driver configuration structure.
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* @note It could be empty on some architectures.
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*/
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typedef struct {
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uint32_t dummy;
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} ADCConfig;
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/**
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* @brief Structure representing an ADC driver.
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*/
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struct ADCDriver {
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/**
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* @brief Driver state.
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*/
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adcstate_t state;
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/**
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* @brief Current configuration data.
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*/
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const ADCConfig *config;
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/**
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* @brief Current samples buffer pointer or @p NULL.
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*/
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adcsample_t *samples;
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/**
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* @brief Current samples buffer depth or @p 0.
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*/
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size_t depth;
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/**
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* @brief Current conversion group pointer or @p NULL.
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*/
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const ADCConversionGroup *grpp;
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#if ADC_USE_WAIT || defined(__DOXYGEN__)
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/**
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* @brief Waiting thread.
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*/
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thread_reference_t thread;
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#endif
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#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
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/**
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* @brief Mutex protecting the peripheral.
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*/
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mutex_t mutex;
|
||
|
|
#endif /* ADC_USE_MUTUAL_EXCLUSION */
|
||
|
|
#if defined(ADC_DRIVER_EXT_FIELDS)
|
||
|
|
ADC_DRIVER_EXT_FIELDS
|
||
|
|
#endif
|
||
|
|
/* End of the mandatory fields.*/
|
||
|
|
/**
|
||
|
|
* @brief Pointer to the ADCx registers block.
|
||
|
|
*/
|
||
|
|
ADC_TypeDef *adc;
|
||
|
|
/**
|
||
|
|
* @brief Pointer to associated DMA channel.
|
||
|
|
*/
|
||
|
|
const stm32_dma_stream_t *dmastp;
|
||
|
|
/**
|
||
|
|
* @brief DMA mode bit mask.
|
||
|
|
*/
|
||
|
|
uint32_t dmamode;
|
||
|
|
};
|
||
|
|
|
||
|
|
/*===========================================================================*/
|
||
|
|
/* Driver macros. */
|
||
|
|
/*===========================================================================*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Changes the value of the ADC CCR register.
|
||
|
|
* @details Use this function in order to enable or disable the internal
|
||
|
|
* analog sources. See the documentation in the STM32 Reference
|
||
|
|
* Manual.
|
||
|
|
* @note PRESC bits must not be specified and left to zero.
|
||
|
|
*/
|
||
|
|
#define adcSTM32SetCCR(ccr) (ADC->CCR = (ccr))
|
||
|
|
|
||
|
|
/*===========================================================================*/
|
||
|
|
/* External declarations. */
|
||
|
|
/*===========================================================================*/
|
||
|
|
|
||
|
|
#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
|
||
|
|
extern ADCDriver ADCD1;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
extern "C" {
|
||
|
|
#endif
|
||
|
|
void adc_lld_init(void);
|
||
|
|
void adc_lld_start(ADCDriver *adcp);
|
||
|
|
void adc_lld_stop(ADCDriver *adcp);
|
||
|
|
void adc_lld_start_conversion(ADCDriver *adcp);
|
||
|
|
void adc_lld_stop_conversion(ADCDriver *adcp);
|
||
|
|
void adc_lld_serve_interrupt(ADCDriver *adcp);
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* HAL_USE_ADC */
|
||
|
|
|
||
|
|
#endif /* _ADC_LLD_H_ */
|
||
|
|
|
||
|
|
/** @} */
|