212 lines
10 KiB
Plaintext
212 lines
10 KiB
Plaintext
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @defgroup IAR_ARMCMx ARM Cortex-Mx
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* @details ARM Cortex-Mx port for the IAR compiler.
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* @section IAR_ARMCMx_INTRO Introduction
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* This port supports all the cores implementing the ARMv6-M and ARMv7-M
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* architectures.
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*
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* @section IAR_ARMCMx_STATES_A System logical states in ARMv6-M mode
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* The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM
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* Cortex-M0 port:
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* - <b>Init</b>. This state is represented by the startup code and the
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* initialization code before @p chSysInit() is executed. It has not a
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* special hardware state associated.
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* - <b>Normal</b>. This is the state the system has after executing
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* @p chSysInit(). In this state interrupts are enabled. The processor
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* is running in thread-privileged mode.
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* - <b>Suspended</b>. In this state the interrupt sources are globally
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* disabled. The processor is running in thread-privileged mode. In this
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* mode this state is not different from the <b>Disabled</b> state.
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* - <b>Disabled</b>. In this state the interrupt sources are globally
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* disabled. The processor is running in thread-privileged mode. In this
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* mode this state is not different from the <b>Suspended</b> state.
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* - <b>Sleep</b>. This state is entered with the execution of the specific
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* instruction @p <b>wfi</b>.
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* - <b>S-Locked</b>. In this state the interrupt sources are globally
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* disabled. The processor is running in thread-privileged mode.
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* - <b>I-Locked</b>. In this state the interrupt sources are globally
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* disabled. The processor is running in exception-privileged mode.
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* - <b>Serving Regular Interrupt</b>. In this state the interrupt sources are
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* not globally masked but only interrupts with higher priority can preempt
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* the current handler. The processor is running in exception-privileged
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* mode.
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* - <b>Serving Fast Interrupt</b>. This state is not implemented in the
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* ARMv6-M implementation.
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* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific
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* asynchronous NMI vector and several synchronous fault vectors that can
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* be considered belonging to this category.
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* - <b>Halted</b>. Implemented as an infinite loop after globally masking all
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* the maskable interrupt sources. The ARM state is whatever the processor
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* was running when @p chSysHalt() was invoked.
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*
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* @section IAR_ARMCMx_STATES_B System logical states in ARMv7-M mode
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* The ChibiOS/RT logical @ref system_states are mapped as follow in the ARM
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* Cortex-M3 port:
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* - <b>Init</b>. This state is represented by the startup code and the
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* initialization code before @p chSysInit() is executed. It has not a
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* special hardware state associated.
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* - <b>Normal</b>. This is the state the system has after executing
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* @p chSysInit(). In this state the ARM Cortex-M3 has the BASEPRI register
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* set at @p CORTEX_BASEPRI_USER level, interrupts are not masked. The
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* processor is running in thread-privileged mode.
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* - <b>Suspended</b>. In this state the interrupt sources are not globally
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* masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
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* masking any interrupt source with lower or equal priority. The processor
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* is running in thread-privileged mode.
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* - <b>Disabled</b>. Interrupt sources are globally masked. The processor
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* is running in thread-privileged mode.
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* - <b>Sleep</b>. This state is entered with the execution of the specific
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* instruction @p <b>wfi</b>.
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* - <b>S-Locked</b>. In this state the interrupt sources are not globally
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* masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
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* masking any interrupt source with lower or equal priority. The processor
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* is running in thread-privileged mode.
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* - <b>I-Locked</b>. In this state the interrupt sources are not globally
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* masked but the BASEPRI register is set to @p CORTEX_BASEPRI_KERNEL thus
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* masking any interrupt source with lower or equal priority. The processor
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* is running in exception-privileged mode.
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* - <b>Serving Regular Interrupt</b>. In this state the interrupt sources are
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* not globally masked but only interrupts with higher priority can preempt
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* the current handler. The processor is running in exception-privileged
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* mode.
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* - <b>Serving Fast Interrupt</b>. It is basically the same of the SRI state
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* but it is not possible to switch to the I-Locked state because fast
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* interrupts can preempt the kernel critical zone.
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* - <b>Serving Non-Maskable Interrupt</b>. The Cortex-M3 has a specific
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* asynchronous NMI vector and several synchronous fault vectors that can
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* be considered belonging to this category.
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* - <b>Halted</b>. Implemented as an infinite loop after globally masking all
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* the maskable interrupt sources. The ARM state is whatever the processor
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* was running when @p chSysHalt() was invoked.
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* .
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* @section IAR_ARMCMx_NOTES ARM Cortex-Mx/IAR port notes
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* The ARM Cortex-Mx port is organized as follow:
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* - The @p main() function is invoked in thread-privileged mode.
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* - Each thread has a private process stack, the system has a single main
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* stack where all the interrupts and exceptions are processed.
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* - The threads are started in thread-privileged mode.
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* - Interrupt nesting and the other advanced core/NVIC features are supported.
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* - When using an STM32 one of the following macros must be defined on the
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* compiler command line or in a file named <tt>board.h</tt>:
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* - @p STM32F10X_LD
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* - @p STM32F10X_LD_VL
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* - @p STM32F10X_MD
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* - @p STM32F10X_MD_VL
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* - @p STM32F10X_HD
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* - @p STM32F10X_XL
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* - @p STM32F10X_CL
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* .
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* This is required in order to include a vectors table with the correct
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* length for the STM32 model, see the file
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* <tt>./os/ports/IAR/ARMCMx/STM32/vectors.s</tt>.
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* - The Cortex-Mx port is perfectly generic, support for more devices can be
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* easily added by adding a subdirectory under <tt>./os/ports/IAR/ARMCMx</tt>
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* and giving it the name of the new device, then copy the files from another
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* device into the new directory and customize them for the new device.
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* .
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* @ingroup iar
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*/
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/**
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* @defgroup IAR_ARMCMx_CONF Configuration Options
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* @details ARM Cortex-Mx Configuration Options. The ARMCMx port allows some
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* architecture-specific configurations settings that can be overridden
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* by redefining them in @p chconf.h. Usually there is no need to change
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* the default values.
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* - @p INT_REQUIRED_STACK, this value represent the amount of stack space used
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* by an interrupt handler between the @p extctx and @p intctx
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* structures.
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* - @p IDLE_THREAD_STACK_SIZE, stack area size to be assigned to the IDLE
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* thread. Usually there is no need to change this value unless inserting
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* code in the IDLE thread using the @p IDLE_LOOP_HOOK hook macro.
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* - @p CORTEX_BASEPRI_KERNEL, this is the @p BASEPRI value for the kernel lock
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* code. Code running at higher priority levels must not invoke any OS API.
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* This setting is specific to the ARMv7-M architecture.
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* - @p CORTEX_PRIORITY_SYSTICK, priority of the SYSTICK handler.
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* - @p CORTEX_PRIORITY_SVCALL, priority of the SVCALL handler.
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* - @p CORTEX_PRIORITY_PENDSV, priority of the PENDSV handler.
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* - @p CORTEX_ENABLE_WFI_IDLE, if set to @p TRUE enables the use of the
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* @p <b>wfi</b> instruction from within the idle loop. This option is
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* defaulted to FALSE because it can create problems with some debuggers.
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* Setting this option to TRUE reduces the system power requirements.
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* .
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* @ingroup IAR_ARMCMx
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*/
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/**
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* @defgroup IAR_ARMCMx_CORE Core Port Implementation
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* @details ARM Cortex-Mx specific port code, structures and macros.
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*
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* @ingroup IAR_ARMCMx
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*/
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/**
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* @defgroup IAR_ARMCMx_V6M_CORE ARMv6-M Specific Implementation
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* @details ARMv6-M specific port code, structures and macros.
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*
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* @ingroup IAR_ARMCMx_CORE
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*/
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/**
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* @defgroup IAR_ARMCMx_V7M_CORE ARMv7-M Specific Implementation
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* @details ARMv7-M specific port code, structures and macros.
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*
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* @ingroup IAR_ARMCMx_CORE
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*/
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/**
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* @defgroup IAR_ARMCMx_STARTUP Startup Support
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* @details ChibiOS/RT provides its own generic startup file for the ARM
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* Cortex-Mx port.
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* Of course it is not mandatory to use it but care should be taken about the
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* startup phase details.
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*
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* @section IAR_ARMCMx_STARTUP_1 Startup Process
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* The startup process, as implemented, is the following:
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* -# Interrupts are masked globally.
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* -# The two stacks are initialized by assigning them the sizes defined in the
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* linker script (usually named @p ch.icf).
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* -# The CPU state is switched to Privileged and the PSP stack is used.
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* -# An early initialization routine @p __early_init() is invoked, if the
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* symbol is not defined then an empty default routine is executed
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* (weak symbol).
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* -# Control is passed to the C runtime entry point @p __cmain that performs
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* the required initializations before invoking the @p main() function.
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* .
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* @ingroup IAR_ARMCMx
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*/
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/**
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* @defgroup IAR_ARMCMx_NVIC NVIC Support
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* @details ARM Cortex-Mx NVIC support.
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*
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* @ingroup IAR_ARMCMx
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*/
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/**
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* @defgroup IAR_ARMCMx_SPECIFIC Specific Implementations
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* @details Platform-specific port code.
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*
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* @ingroup IAR_ARMCMx
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*/
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