2007-09-18 12:39:01 +00:00
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/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <ch.h>
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#include "lpc214x.h"
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2007-12-09 09:16:33 +00:00
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#include "vic.h"
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2007-09-18 12:39:01 +00:00
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#include "lpc214x_serial.h"
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2007-12-18 09:41:28 +00:00
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#include "board.h"
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2007-09-18 12:39:01 +00:00
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FullDuplexDriver COM1;
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2008-03-04 16:08:22 +00:00
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static uint8_t ib1[SERIAL_BUFFERS_SIZE];
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static uint8_t ob1[SERIAL_BUFFERS_SIZE];
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2007-09-18 12:39:01 +00:00
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FullDuplexDriver COM2;
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2008-03-04 16:08:22 +00:00
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static uint8_t ib2[SERIAL_BUFFERS_SIZE];
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static uint8_t ob2[SERIAL_BUFFERS_SIZE];
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2007-09-18 12:39:01 +00:00
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static void SetError(IOREG32 err, FullDuplexDriver *com) {
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2008-03-05 10:59:11 +00:00
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dflags_t sts = 0;
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2007-09-18 12:39:01 +00:00
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if (err & LSR_OVERRUN)
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sts |= SD_OVERRUN_ERROR;
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if (err & LSR_PARITY)
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sts |= SD_PARITY_ERROR;
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if (err & LSR_FRAMING)
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sts |= SD_FRAMING_ERROR;
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if (err & LSR_BREAK)
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sts |= SD_BREAK_DETECTED;
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2009-01-24 17:59:51 +00:00
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chSysLockFromIsr();
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2007-09-18 12:39:01 +00:00
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chFDDAddFlagsI(com, sts);
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2009-01-24 17:59:51 +00:00
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chSysUnlockFromIsr();
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2007-09-18 12:39:01 +00:00
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}
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/*
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* Tries hard to clear all the pending interrupt sources, we dont want to
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* go through the whole ISR and have another interrupt soon after.
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*/
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2009-01-10 15:20:40 +00:00
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__attribute__((noinline))
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2007-09-18 12:39:01 +00:00
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static void ServeInterrupt(UART *u, FullDuplexDriver *com) {
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while (TRUE) {
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switch (u->UART_IIR & IIR_SRC_MASK) {
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case IIR_SRC_NONE:
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return;
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case IIR_SRC_ERROR:
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SetError(u->UART_LSR, com);
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break;
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case IIR_SRC_TIMEOUT:
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case IIR_SRC_RX:
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2009-01-10 15:20:40 +00:00
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while (u->UART_LSR & LSR_RBR_FULL) {
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2009-01-24 17:59:51 +00:00
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chSysLockFromIsr();
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2007-11-26 16:00:25 +00:00
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if (chIQPutI(&com->sd_iqueue, u->UART_RBR) < Q_OK)
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chFDDAddFlagsI(com, SD_OVERRUN_ERROR);
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2009-01-24 17:59:51 +00:00
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chSysUnlockFromIsr();
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2009-01-10 15:20:40 +00:00
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}
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2009-01-24 17:59:51 +00:00
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chSysLockFromIsr();
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2008-07-23 10:38:16 +00:00
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chEvtBroadcastI(&com->sd_ievent);
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2009-01-24 17:59:51 +00:00
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chSysUnlockFromIsr();
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2007-09-18 12:39:01 +00:00
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break;
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case IIR_SRC_TX:
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{
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2007-10-24 12:12:43 +00:00
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#ifdef FIFO_PRELOAD
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2007-10-24 13:33:36 +00:00
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int i = FIFO_PRELOAD;
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do {
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2009-01-24 17:59:51 +00:00
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chSysLockFromIsr();
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2008-03-05 10:59:11 +00:00
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msg_t b = chOQGetI(&com->sd_oqueue);
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2009-01-24 17:59:51 +00:00
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chSysUnlockFromIsr();
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2007-10-24 12:12:43 +00:00
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if (b < Q_OK) {
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u->UART_IER &= ~IER_THRE;
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2009-01-24 17:59:51 +00:00
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chSysLockFromIsr();
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2008-07-23 10:38:16 +00:00
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chEvtBroadcastI(&com->sd_oevent);
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2009-01-24 17:59:51 +00:00
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chSysUnlockFromIsr();
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2007-10-24 12:12:43 +00:00
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break;
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}
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u->UART_THR = b;
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2007-10-24 13:33:36 +00:00
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} while (--i);
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2007-10-24 12:12:43 +00:00
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#else
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2009-01-24 17:59:51 +00:00
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chSysLockFromIsr();
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2008-03-05 10:59:11 +00:00
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msg_t b = chFDDRequestDataI(com);
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2009-01-24 17:59:51 +00:00
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chSysUnlockFromIsr();
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2007-09-18 12:39:01 +00:00
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if (b < Q_OK)
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u->UART_IER &= ~IER_THRE;
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else
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u->UART_THR = b;
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2007-10-24 12:12:43 +00:00
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#endif
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2007-09-18 12:39:01 +00:00
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}
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default:
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u->UART_THR;
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u->UART_RBR;
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}
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}
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}
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2009-01-19 15:10:41 +00:00
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CH_IRQ_HANDLER(UART0IrqHandler) {
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2007-10-24 13:33:36 +00:00
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2009-01-10 16:21:27 +00:00
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CH_IRQ_PROLOGUE();
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2007-12-09 09:16:33 +00:00
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ServeInterrupt(U0Base, &COM1);
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2008-02-22 11:17:42 +00:00
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VICVectAddr = 0;
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2009-01-10 16:21:27 +00:00
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CH_IRQ_EPILOGUE();
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2007-10-24 13:33:36 +00:00
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}
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2009-01-19 15:10:41 +00:00
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CH_IRQ_HANDLER(UART1IrqHandler) {
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2007-10-24 13:33:36 +00:00
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2009-01-10 16:21:27 +00:00
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CH_IRQ_PROLOGUE();
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2007-12-09 09:16:33 +00:00
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ServeInterrupt(U1Base, &COM2);
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2008-02-22 11:17:42 +00:00
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VICVectAddr = 0;
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2009-01-10 16:21:27 +00:00
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CH_IRQ_EPILOGUE();
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2007-10-24 13:33:36 +00:00
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}
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2007-10-24 12:12:43 +00:00
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#ifdef FIFO_PRELOAD
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2007-10-27 07:37:32 +00:00
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static void preload(UART *u, FullDuplexDriver *com) {
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2007-10-24 13:33:36 +00:00
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if (u->UART_LSR & LSR_THRE) {
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int i = FIFO_PRELOAD;
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do {
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2009-01-24 17:59:51 +00:00
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chSysLockFromIsr();
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2008-03-05 10:59:11 +00:00
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msg_t b = chOQGetI(&com->sd_oqueue);
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2009-01-24 17:59:51 +00:00
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chSysUnlockFromIsr();
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2007-10-24 13:33:36 +00:00
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if (b < Q_OK) {
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2009-01-24 17:59:51 +00:00
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chSysLockFromIsr();
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2008-07-23 10:38:16 +00:00
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chEvtBroadcastI(&com->sd_oevent);
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2009-01-24 17:59:51 +00:00
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chSysUnlockFromIsr();
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2007-10-24 13:33:36 +00:00
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return;
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}
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2007-10-24 12:12:43 +00:00
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u->UART_THR = b;
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2007-10-24 13:33:36 +00:00
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} while (--i);
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}
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2007-10-27 07:37:32 +00:00
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u->UART_IER |= IER_THRE;
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}
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#endif
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/*
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* Invoked by the high driver when one or more bytes are inserted in the
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* output queue.
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*/
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static void OutNotify1(void) {
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#ifdef FIFO_PRELOAD
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preload(U0Base, &COM1);
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2007-10-24 12:12:43 +00:00
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#else
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2007-10-27 07:37:32 +00:00
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UART *u = U0Base;
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2009-01-10 15:20:40 +00:00
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if (u->UART_LSR & LSR_THRE) {
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2009-01-24 17:59:51 +00:00
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chSysLockFromIsr();
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2007-09-18 12:39:01 +00:00
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u->UART_THR = chOQGetI(&COM1.sd_oqueue);
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2009-01-24 17:59:51 +00:00
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chSysUnlockFromIsr();
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2009-01-10 15:20:40 +00:00
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}
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2007-09-18 12:39:01 +00:00
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u->UART_IER |= IER_THRE;
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2007-10-27 07:37:32 +00:00
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#endif
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2007-09-18 12:39:01 +00:00
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}
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/*
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* Invoked by the high driver when one or more bytes are inserted in the
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* output queue.
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*/
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static void OutNotify2(void) {
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2007-10-24 12:12:43 +00:00
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#ifdef FIFO_PRELOAD
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2007-10-27 07:37:32 +00:00
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preload(U1Base, &COM2);
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2007-10-24 12:12:43 +00:00
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#else
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2007-10-27 07:37:32 +00:00
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UART *u = U1Base;
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2007-10-24 13:33:36 +00:00
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if (u->UART_LSR & LSR_THRE)
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2007-10-23 19:50:46 +00:00
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u->UART_THR = chOQGetI(&COM2.sd_oqueue);
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2007-09-18 12:39:01 +00:00
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u->UART_IER |= IER_THRE;
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2007-10-27 07:37:32 +00:00
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#endif
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2007-09-18 12:39:01 +00:00
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}
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/*
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* UART setup, must be invoked with interrupts disabled.
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*/
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2009-01-24 17:59:51 +00:00
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void SetUART(UART *u, int speed, int lcr, int fcr) {
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2007-09-18 12:39:01 +00:00
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int div = PCLK / (speed << 4);
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u->UART_LCR = lcr | LCR_DLAB;
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u->UART_DLL = div;
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u->UART_DLM = div >> 8;
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u->UART_LCR = lcr;
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u->UART_FCR = FCR_ENABLE | FCR_RXRESET | FCR_TXRESET | fcr;
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u->UART_ACR = 0;
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u->UART_FDR = 0x10;
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u->UART_TER = TER_ENABLE;
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u->UART_IER = IER_RBR | IER_STATUS;
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}
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/*
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* Serial subsystem initialization.
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*/
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2007-12-09 09:16:33 +00:00
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void InitSerial(int vector1, int vector2) {
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SetVICVector(UART0IrqHandler, vector1, SOURCE_UART0);
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SetVICVector(UART1IrqHandler, vector2, SOURCE_UART1);
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2007-09-18 12:39:01 +00:00
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PCONP = (PCONP & PCALL) | PCUART0 | PCUART1;
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chFDDInit(&COM1, ib1, sizeof ib1, NULL, ob1, sizeof ob1, OutNotify1);
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2009-01-24 17:59:51 +00:00
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SetUART(U0Base, 38400, LCR_WL8 | LCR_STOP1 | LCR_NOPARITY, FCR_TRIGGER0);
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2007-09-18 12:39:01 +00:00
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chFDDInit(&COM2, ib2, sizeof ib2, NULL, ob2, sizeof ob2, OutNotify2);
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2009-01-24 17:59:51 +00:00
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SetUART(U1Base, 38400, LCR_WL8 | LCR_STOP1 | LCR_NOPARITY, FCR_TRIGGER0);
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2007-09-18 12:39:01 +00:00
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2007-10-23 18:43:39 +00:00
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VICIntEnable = INTMASK(SOURCE_UART0) | INTMASK(SOURCE_UART1);
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2007-09-18 12:39:01 +00:00
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}
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