2012-03-05 18:15:19 +00:00
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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2012-03-05 20:39:09 +00:00
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the Free software Foundation; either version 3 of the License, or
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2012-03-05 18:15:19 +00:00
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file stm32_otg.h
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* @brief STM32 OTG registers layout header.
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*
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* @addtogroup USB
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* @{
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*/
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#ifndef _STM32_OTG_H_
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#define _STM32_OTG_H_
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/**
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2012-03-05 20:39:09 +00:00
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* @brief Number of the implemented endpoints.
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2012-03-05 18:15:19 +00:00
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* @details This value does not include the endpoint 0 that is always present.
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*/
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#define STM32_OTG_ENDOPOINTS_NUMBER 3
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/**
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* @brief Host channel registers group.
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*/
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typedef struct {
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volatile uint32_t HCCHAR; /**< @brief Host channel characteristics
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register. */
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volatile uint32_t resvd8;
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volatile uint32_t HCINT; /**< @brief Host channel interrupt register.*/
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volatile uint32_t HCINTMSK; /**< @brief Host channel interrupt mask
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register. */
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volatile uint32_t HCTSIZ; /**< @brief Host channel transfer size
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register. */
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volatile uint32_t resvd14;
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volatile uint32_t resvd18;
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volatile uint32_t resvd1c;
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} stm32_otg_host_chn_t;
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/**
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2012-03-05 20:39:09 +00:00
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* @brief Device input endpoint registers group.
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2012-03-05 18:15:19 +00:00
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*/
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typedef struct {
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volatile uint32_t DIEPCTL; /**< @brief Device control IN endpoint control
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register. */
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volatile uint32_t resvd4;
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volatile uint32_t DIEPINT; /**< @brief Device IN endpoint interrupt
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register. */
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volatile uint32_t resvdC;
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volatile uint32_t DIEPTSIZ; /**< @brief Device IN endpoint transfer size
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register. */
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volatile uint32_t resvd14;
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volatile uint32_t DTXFSTS; /**< @brief Device IN endpoint transmit FIFO
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status register. */
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volatile uint32_t resvd1C;
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} stm32_otg_in_ep_t;
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/**
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2012-03-05 20:39:09 +00:00
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* @brief Device output endpoint registers group.
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2012-03-05 18:15:19 +00:00
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*/
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typedef struct {
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volatile uint32_t DOEPCTL; /**< @brief Device control OUT endpoint control
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register. */
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volatile uint32_t resvd4;
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volatile uint32_t DOEPINT; /**< @brief Device OUT endpoint interrupt
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register. */
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volatile uint32_t resvdC;
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volatile uint32_t DOEPTSIZ; /**< @brief Device OUT endpoint transfer size
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register. */
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volatile uint32_t resvd14;
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volatile uint32_t resvd18;
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volatile uint32_t resvd1C;
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} stm32_t_out_ep_t;
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/**
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* @brief USB registers memory map.
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*/
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typedef struct {
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volatile uint32_t GOTGCTL; /**< @brief OTG control and status register.*/
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volatile uint32_t GOTGINT; /**< @brief OTG interrupt register. */
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volatile uint32_t GAHBCFG; /**< @brief AHB configuration register. */
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volatile uint32_t GUSBCFG; /**< @brief USB configuration register. */
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volatile uint32_t GRSTCTL; /**< @brief Reset register size. */
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volatile uint32_t GINTSTS; /**< @brief Interrupt register. */
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volatile uint32_t GINTMSK; /**< @brief Interrupt mask register. */
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volatile uint32_t GRXSTSR; /**< @brief Receive status debug read
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register. */
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volatile uint32_t GRXSTSP; /**< @brief Receive status read/pop
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register. */
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volatile uint32_t GRXFSIZ; /**< @brief Receive FIFO size register. */
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volatile uint32_t DIEPTXF0; /**< @brief endpoint 0 transmit FIFO size
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register. */
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volatile uint32_t HNPTXSTS; /**< @brief non-periodic transmit FIFO/queue
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status register. */
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volatile uint32_t resvd30;
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volatile uint32_t resvd34;
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volatile uint32_t GCCFG; /**< @brief General core configuration. */
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volatile uint32_t CID; /**< @brief Core ID register. */
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volatile uint32_t resvd58[48];
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volatile uint32_t HPTXFSIZ; /**< @brief Host periodic transmit FIFO size
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register. */
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volatile uint32_t DIEPTXF[15];/**< @brief Ddevice IN endpoint transmit FIFO
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size registers. */
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volatile uint32_t resvd140[176];
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volatile uint32_t HCFG; /**< @brief Host configuration register. */
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volatile uint32_t HFIR; /**< @brief Host frame interval register. */
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volatile uint32_t HFNUM; /**< @brief Host frame number/frame time
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Remaining register. */
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volatile uint32_t resvd40C;
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volatile uint32_t HPTXSTS; /**< @brief Host periodic transmit FIFO/queue
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status register. */
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volatile uint32_t HAINT; /**< @brief Host all channels interrupt
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register. */
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volatile uint32_t HAINTMSK; /**< @brief Host all channels interrupt mask
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register. */
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volatile uint32_t resvd41C[9];
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volatile uint32_t HPRT; /**< @brief Host port control and status
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register. */
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volatile uint32_t resvd444[47];
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stm32_otg_host_chn_t hc[16]; /**< @brief Host channels array. */
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volatile uint32_t resvd700[64];
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volatile uint32_t DCFG; /**< @brief Device configuration register. */
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volatile uint32_t DCTL; /**< @brief Device control register. */
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volatile uint32_t DSTS; /**< @brief Device status register. */
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volatile uint32_t resvd80C;
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volatile uint32_t DIEPMSK; /**< @brief Device IN endpoint common
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interrupt mask register. */
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volatile uint32_t DOEPMSK; /**< @brief Device OUT endpoint common
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interrupt mask register. */
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volatile uint32_t DAINT; /**< @brief Device all endpoints interrupt
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register. */
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volatile uint32_t DAINTMSK; /**< @brief Device all endpoints interrupt
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mask register. */
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volatile uint32_t resvd820;
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volatile uint32_t resvd824;
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volatile uint32_t DVBUSDIS; /**< @brief Device VBUS Discharge time
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register. */
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volatile uint32_t DVBUSPULSE; /**< @brief Device VBUS Pulsing time
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register. */
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volatile uint32_t resvd830;
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volatile uint32_t DIEPEMPMSK; /**< @brief Device IN endpoint FIFO empty
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interrupt mask register. */
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volatile uint32_t resvd838;
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volatile uint32_t resvd83C;
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volatile uint32_t resvd840[16];
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volatile uint32_t resvd880[16];
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volatile uint32_t resvd8C0[16];
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stm32_otg_in_ep_t ie[16]; /**< @brief Input endpoints. */
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stm32_t_out_ep_t oe[16]; /**< @brief Output endpoints. */
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volatile uint32_t resvdD00[64];
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volatile uint32_t PCGCCTL; /**< @brief Power and clock gating control
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register. */
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volatile uint32_t resvdE04[127];
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} stm32_otg_t;
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2012-03-05 20:39:09 +00:00
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/**
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* @name GOTGCTL register bit definitions
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* @{
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*/
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#define GOTGCTL_BSVLD (1U<<19) /**< B-Session Valid. */
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#define GOTGCTL_ASVLD (1U<<18) /**< A-Session Valid. */
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#define GOTGCTL_DBCT (1U<<17) /**< Long/Short debounce time. */
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#define GOTGCTL_CIDSTS (1U<<16) /**< Connector ID status. */
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#define GOTGCTL_DHNPEN (1U<<11) /**< Device HNP enabled. */
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#define GOTGCTL_HSHNPEN (1U<<10) /**< Host Set HNP enable. */
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#define GOTGCTL_HNPRQ (1U<<9) /**< HNP request. */
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#define GOTGCTL_HNGSCS (1U<<8) /**< Host negotiation success. */
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#define GOTGCTL_SRQ (1U<<1) /**< Session request. */
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#define GOTGCTL_SRQSCS (1U<<0) /**< Session request success. */
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/** @} */
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2012-03-05 20:39:09 +00:00
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/**
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* @name GOTGINT register bit definitions
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* @{
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*/
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#define GOTGINT_DBCDNE (1U<<19) /**< Debounce done. */
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#define GOTGINT_ADTOCHG (1U<<18) /**< A-Device timeout change. */
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#define GOTGINT_HNGDET (1U<<17) /**< Host negotiation detected. */
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#define GOTGINT_HNSSCHG (1U<<9) /**< Host negotiation success
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status change. */
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#define GOTGINT_SRSSCHG (1U<<8) /**< Session request success
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status change. */
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#define GOTGINT_SEDET (1U<<2) /**< Session end detected. */
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/** @} */
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2012-03-05 20:39:09 +00:00
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/**
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* @name GAHBCFG register bit definitions
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* @{
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*/
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#define GAHBCFG_PTXFELVL (1U<<8) /**< Periodic TxFIFO empty
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level. */
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#define GAHBCFG_TXFELVL (1U<<7) /**< non-periodic TxFIFO empty
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level. */
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#define GAHBCFG_GINTMSK (1U<<0) /**< Global interrupt mask. */
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/** @} */
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2012-03-05 20:39:09 +00:00
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/**
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* @name GUSBCFG register bit definitions
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* @{
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*/
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#define GUSBCFG_CTXPKT (1U<<31) /**< Corrupt Tx packet. */
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#define GUSBCFG_FDMOD (1U<<30) /**< Force Device Mode. */
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#define GUSBCFG_FHMOD (1U<<29) /**< Force Host Mode. */
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#define GUSBCFG_TRDT_MASK (15U<<10) /**< USB Turnaround time field
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mask. */
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#define GUSBCFG_TRDT(n) ((n##U)<<10)/**< USB Turnaround time field
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value. */
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#define GUSBCFG_HNPCAP (1U<<9) /**< HNP-Capable. */
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#define GUSBCFG_SRPCAP (1U<<8) /**< SRP-Capable. */
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#define GUSBCFG_PHYSEL (1U<<6) /**< USB 2.0 High-Speed PHY or
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USB 1.1 Full-Speed serial
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transceiver Select. */
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#define GUSBCFG_TOCAL_MASK (7U<<0) /**< HS/FS timeout calibration
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field mask. */
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#define GUSBCFG_TOCAL(n) ((n##U)<<0) /**< HS/FS timeout calibration
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field value. */
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/** @} */
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/**
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* @name GRSTCTL register bit definitions
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* @{
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*/
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#define GRSTCTL_AHBIDL (1U<<31) /**< AHB Master Idle. */
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#define GRSTCTL_TXFNUM_MASK (31U<<6) /**< TxFIFO number field mask. */
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#define GRSTCTL_TXFNUM(n) ((n##U)<<6) /**< TxFIFO number field value. */
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#define GRSTCTL_TXFFLSH (1U<<5) /**< TxFIFO flush. */
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#define GRSTCTL_RXFFLSH (1U<<4) /**< RxFIFO flush. */
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#define GRSTCTL_FCRST (1U<<2) /**< Host frame counter reset. */
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#define GRSTCTL_HSRST (1U<<1) /**< HClk soft reset. */
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#define GRSTCTL_CSRST (1U<<0) /**< Core soft reset. */
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/** @} */
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2012-03-05 20:39:09 +00:00
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/**
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* @name GINTSTS register bit definitions
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* @{
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*/
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#define GINTSTS_WKUPINT (1U<<31) /**< Resume/Remote wakeup
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detected interrupt. */
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#define GINTSTS_SRQINT (1U<<30) /**< Session request/New session
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detected interrupt. */
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#define GINTSTS_DISCINT (1U<<29) /**< Disconnect detected
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interrupt. */
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#define GINTSTS_CIDSCHG (1U<<28) /**< Connector ID status change.*/
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#define GINTSTS_PTXFE (1U<<26) /**< Periodic TxFIFO empty. */
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#define GINTSTS_HCINT (1U<<25) /**< Host channels interrupt. */
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#define GINTSTS_HPRTINT (1U<<24) /**< Host port interrupt. */
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#define GINTSTS_IPXFR (1U<<21) /**< Incomplete periodic
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transfer. */
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#define GINTSTS_IISOOXFR (1U<<21) /**< Incomplete isochronous OUT
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transfer. */
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#define GINTSTS_IISOIXFR (1U<<20) /**< Incomplete isochronous IN
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transfer. */
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#define GINTSTS_OEPINT (1U<<19) /**< OUT endpoints interrupt. */
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#define GINTSTS_IEPINT (1U<<18) /**< IN endpoints interrupt. */
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#define GINTSTS_EOPF (1U<<15) /**< End of periodic frame
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interrupt. */
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#define GINTSTS_ISOODRP (1U<<14) /**< Isochronous OUT packet
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dropped interrupt. */
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#define GINTSTS_ENUMDNE (1U<<13) /**< Enumeration done. */
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#define GINTSTS_USBRST (1U<<12) /**< USB reset. */
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#define GINTSTS_USBSUSP (1U<<11) /**< USB suspend. */
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#define GINTSTS_ESUSP (1U<<10) /**< Early suspend. */
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|
|
|
#define GINTSTS_GONAKEFF (1U<<7) /**< Global OUT NAK effective. */
|
|
|
|
|
#define GINTSTS_GINAKEFF (1U<<6) /**< Global IN non-periodic NAK
|
|
|
|
|
effective. */
|
|
|
|
|
#define GINTSTS_NPTXFE (1U<<5) /**< Non-periodic TxFIFO empty. */
|
|
|
|
|
#define GINTSTS_RXFLVL (1U<<4) /**< RxFIFO non-empty. */
|
|
|
|
|
#define GINTSTS_SOF (1U<<3) /**< Start of frame. */
|
|
|
|
|
#define GINTSTS_OTGINT (1U<<2) /**< OTG interrupt. */
|
|
|
|
|
#define GINTSTS_MMIS (1U<<1) /**< Mode Mismatch interrupt. */
|
|
|
|
|
#define GINTSTS_CMOD (1U<<0) /**< Current mode of operation. */
|
|
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name GINTMSK register bit definitions
|
|
|
|
|
* @{
|
|
|
|
|
*/
|
|
|
|
|
#define GINTMSK_WKUM (1U<<31) /**< Resume/remote wakeup
|
|
|
|
|
detected interrupt mask. */
|
|
|
|
|
#define GINTMSK_SRQM (1U<<30) /**< Session request/New session
|
|
|
|
|
detected interrupt mask. */
|
|
|
|
|
#define GINTMSK_DISCM (1U<<29) /**< Disconnect detected
|
|
|
|
|
interrupt mask. */
|
|
|
|
|
#define GINTMSK_CIDSCHGM (1U<<28) /**< Connector ID status change
|
|
|
|
|
mask. */
|
|
|
|
|
#define GINTMSK_PTXFEM (1U<<26) /**< Periodic TxFIFO empty mask.*/
|
|
|
|
|
#define GINTMSK_HCM (1U<<25) /**< Host channels interrupt
|
|
|
|
|
mask. */
|
|
|
|
|
#define GINTMSK_HPRTM (1U<<24) /**< Host port interrupt mask. */
|
|
|
|
|
#define GINTMSK_IPXFRM (1U<<21) /**< Incomplete periodic
|
|
|
|
|
transfer mask. */
|
|
|
|
|
#define GINTMSK_IISOOXFRM (1U<<21) /**< Incomplete isochronous OUT
|
|
|
|
|
transfer mask. */
|
|
|
|
|
#define GINTMSK_IISOIXFRM (1U<<20) /**< Incomplete isochronous IN
|
|
|
|
|
transfer mask. */
|
|
|
|
|
#define GINTMSK_OEPM (1U<<19) /**< OUT endpoints interrupt
|
|
|
|
|
mask. */
|
|
|
|
|
#define GINTMSK_IEPM (1U<<18) /**< IN endpoints interrupt
|
|
|
|
|
mask. */
|
|
|
|
|
#define GINTMSK_EPMISM (1U<<17) /**< Endpoint Mismatch interrupt
|
|
|
|
|
mask. */
|
|
|
|
|
#define GINTMSK_EOPFM (1U<<15) /**< End of periodic frame
|
|
|
|
|
interrupt mask. */
|
|
|
|
|
#define GINTMSK_ISOODRPM (1U<<14) /**< Isochronous OUT packet
|
|
|
|
|
dropped interrupt mask. */
|
|
|
|
|
#define GINTMSK_ENUMDNEM (1U<<13) /**< Enumeration done mask. */
|
|
|
|
|
#define GINTMSK_USBRSTM (1U<<12) /**< USB reset mask. */
|
|
|
|
|
#define GINTMSK_USBSUSPM (1U<<11) /**< USB suspend mask. */
|
|
|
|
|
#define GINTMSK_ESUSPM (1U<<10) /**< Early suspend mask. */
|
|
|
|
|
#define GINTMSK_GONAKEFFM (1U<<7) /**< Global OUT NAK effective
|
|
|
|
|
mask. */
|
|
|
|
|
#define GINTMSK_GINAKEFFM (1U<<6) /**< Global non-periodic IN NAK
|
|
|
|
|
effective mask. */
|
|
|
|
|
#define GINTMSK_NPTXFEM (1U<<5) /**< Non-periodic TxFIFO empty
|
|
|
|
|
mask. */
|
|
|
|
|
#define GINTMSK_RXFLVLM (1U<<4) /**< Receive FIFO non-empty
|
|
|
|
|
mask. */
|
|
|
|
|
#define GINTMSK_SOFM (1U<<3) /**< Start of (micro)frame mask.*/
|
|
|
|
|
#define GINTMSK_OTGM (1U<<2) /**< OTG interrupt mask. */
|
|
|
|
|
#define GINTMSK_MMISM (1U<<1) /**< Mode Mismatch interrupt
|
|
|
|
|
mask. */
|
|
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name GRXSTSR register bit definitions
|
|
|
|
|
* @{
|
|
|
|
|
*/
|
|
|
|
|
#define GRXSTSR_PKTSTS_MASK (15U<<17) /**< Packet status mask. */
|
|
|
|
|
#define GRXSTSR_PKTSTS(n) ((n##U)<<17)/**< Packet status value. */
|
|
|
|
|
#define GRXSTSR_OUT_GLOBAL_NAK GRXSTSR_PKTSTS(1)
|
|
|
|
|
#define GRXSTSR_OUT_DATA GRXSTSR_PKTSTS(2)
|
|
|
|
|
#define GRXSTSR_OUT_COMP GRXSTSR_PKTSTS(3)
|
|
|
|
|
#define GRXSTSR_SETUP_COMP GRXSTSR_PKTSTS(4)
|
|
|
|
|
#define GRXSTSR_SETUP_DATA GRXSTSR_PKTSTS(6)
|
|
|
|
|
#define GRXSTSR_DPID_MASK (3U<<15) /**< Data PID mask. */
|
|
|
|
|
#define GRXSTSR_DPID(n) ((n##U)<<15)/**< Data PID value. */
|
|
|
|
|
#define GRXSTSR_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */
|
|
|
|
|
#define GRXSTSR_BCNT(n) ((n##U)<<4) /**< Byte count value. */
|
|
|
|
|
#define GRXSTSR_CHNUM_MASK (15U<<0) /**< Channel number mask. */
|
|
|
|
|
#define GRXSTSR_CHNUM(n) ((n##U)<<0) /**< Channel number value. */
|
|
|
|
|
#define GRXSTSR_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */
|
|
|
|
|
#define GRXSTSR_EPNUM(n) ((n##U)<<0) /**< Endpoint number value. */
|
|
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name GRXSTSP register bit definitions
|
|
|
|
|
* @{
|
|
|
|
|
*/
|
|
|
|
|
#define GRXSTSP_PKTSTS_MASK (15<<17) /**< Packet status mask. */
|
|
|
|
|
#define GRXSTSP_PKTSTS(n) ((n##U)<<17)/**< Packet status value. */
|
|
|
|
|
#define GRXSTSP_OUT_GLOBAL_NAK GRXSTSP_PKTSTS(1)
|
|
|
|
|
#define GRXSTSP_OUT_DATA GRXSTSP_PKTSTS(2)
|
|
|
|
|
#define GRXSTSP_OUT_COMP GRXSTSP_PKTSTS(3)
|
|
|
|
|
#define GRXSTSP_SETUP_COMP GRXSTSP_PKTSTS(4)
|
|
|
|
|
#define GRXSTSP_SETUP_DATA GRXSTSP_PKTSTS(6)
|
|
|
|
|
#define GRXSTSP_DPID_MASK (3U<<15) /**< Data PID mask. */
|
|
|
|
|
#define GRXSTSP_DPID(n) ((n##U)<<15)/**< Data PID value. */
|
|
|
|
|
#define GRXSTSP_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */
|
|
|
|
|
#define GRXSTSP_BCNT(n) ((n##U)<<4) /**< Byte count value. */
|
|
|
|
|
#define GRXSTSP_CHNUM_MASK (15U<<0) /**< Channel number mask. */
|
|
|
|
|
#define GRXSTSP_CHNUM(n) ((n##U)<<0) /**< Channel number value. */
|
|
|
|
|
#define GRXSTSP_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */
|
|
|
|
|
#define GRXSTSP_EPNUM(n) ((n##U)<<0) /**< Endpoint number value. */
|
|
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name GRXFSIZ register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
2012-03-05 20:39:09 +00:00
|
|
|
#define GRXFSIZ_RXFD_MASK (0xFFFF<<0) /**< RxFIFO depth mask. */
|
|
|
|
|
#define GRXFSIZ_RXFD(n) ((n##U)<<0) /**< RxFIFO depth value. */
|
|
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name GNPTXFSIZ register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
2012-03-05 20:39:09 +00:00
|
|
|
#define GNPTXFSIZ_NPTXFD_MASK (0xFFFFU<<16)/**< Non-periodic TxFIFO depth
|
|
|
|
|
mask. */
|
|
|
|
|
#define GNPTXFSIZ_NPTXFD(n) ((n##U)<<16)/**< Non-periodic TxFIFO depth
|
|
|
|
|
value. */
|
|
|
|
|
#define GNPTXFSIZ_NPTXFSA_MASK (0xFFFFU<<0)/**< Non-periodic transmit RAM
|
|
|
|
|
start address mask. */
|
|
|
|
|
#define GNPTXFSIZ_NPTXFSA(n) ((n##U)<<0) /**< Non-periodic transmit RAM
|
|
|
|
|
start address value. */
|
|
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name GNPTXSTS register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
2012-03-05 20:39:09 +00:00
|
|
|
#define GNPTXSTS_NPTxQTop_MASK (0x7F<<24) /**< Top of the non-periodic
|
|
|
|
|
transmit request queue
|
2012-03-05 18:15:19 +00:00
|
|
|
mask. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define GNPTXSTS_NPTxQTop(n) ((n)<<24) /**< Top of the non-periodic
|
|
|
|
|
transmit request queue
|
2012-03-05 18:15:19 +00:00
|
|
|
value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define GNPTXSTS_NPTxQSpcAvail_MASK (0xFF<<16) /**< non-periodic transmit
|
|
|
|
|
request queue Space
|
2012-03-05 18:15:19 +00:00
|
|
|
Available mask. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define GNPTXSTS_NPTxQSpcAvail(n) ((n)<<16) /**< non-periodic transmit
|
|
|
|
|
request queue Space
|
2012-03-05 18:15:19 +00:00
|
|
|
Available value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define GNPTXSTS_NPTxFSpcAvail_MASK (0xFFFF<<0) /**< non-periodic TxFIFO
|
2012-03-05 18:15:19 +00:00
|
|
|
Space Available mask. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define GNPTXSTS_NPTxFSpcAvail(n) ((n)<<0) /**< non-periodic TxFIFO
|
2012-03-05 18:15:19 +00:00
|
|
|
Space Available value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name HPTXFSIZ register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
|
|
|
|
#define HPTXFSIZ_PTxFsize_MASK (0xFFFF<<16)/**< Host periodic TxFIFO
|
|
|
|
|
Depth mask. */
|
|
|
|
|
#define HPTXFSIZ_PTxFsize(n) ((n)<<16) /**< Host periodic TxFIFO
|
|
|
|
|
Depth value. */
|
|
|
|
|
#define HPTXFSIZ_PTxFStAddr_MASK (0xFFFF<<0) /**< Host periodic TxFIFO
|
|
|
|
|
Start Address mask. */
|
|
|
|
|
#define HPTXFSIZ_PTxFStAddr(n) ((n)<<0) /**< Host periodic TxFIFO
|
|
|
|
|
Start Address value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name DPTXFSIZ register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
|
|
|
|
#define DPTXFSIZ_DPTxFsize_MASK (0xFFFF<<16 /**< Device periodic TxFIFO
|
|
|
|
|
size mask. */
|
|
|
|
|
#define DPTXFSIZ_DPTxFsize(n) ((n)<<16) /**< Device periodic TxFIFO
|
|
|
|
|
size value. */
|
|
|
|
|
#define DPTXFSIZ_DPTxFStAddr_MASK (0xFFFF<<0) /**< Device periodic TxFIFO
|
|
|
|
|
RAM Start Address mask.*/
|
|
|
|
|
#define DPTXFSIZ_DPTxFStAddr(n) ((n)<<0) /**< Device periodic TxFIFO
|
|
|
|
|
RAM Start Address
|
|
|
|
|
value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name HCFG register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
|
|
|
|
#define HCFG_ResValid_MASK (0xFF<<8) /**< Resume Validation
|
|
|
|
|
Period mask. */
|
|
|
|
|
#define HCFG_ResValid(n) ((n)<<8) /**< Resume Validation
|
|
|
|
|
Period value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCFG_Ena32KHzS (1U<<7) /**< enable 32-KHz suspend
|
2012-03-05 18:15:19 +00:00
|
|
|
Mode. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCFG_FSLSSupp (1U<<2) /**< FS- and LS-Only
|
2012-03-05 18:15:19 +00:00
|
|
|
Support. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCFG_FSLSPclkSel_MASK (3<<0) /**< FS/LS PHY clock Select
|
2012-03-05 18:15:19 +00:00
|
|
|
mask. */
|
|
|
|
|
#define HCFG_FSLSPclkSel_30_60 (0<<0) /**< PHY clock is running at
|
|
|
|
|
30/60 MHz. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCFG_FSLSPclkSel_48 (1U<<0) /**< PHY clock is running at
|
2012-03-05 18:15:19 +00:00
|
|
|
48 MHz. */
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name HFIR register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
|
|
|
|
#define HFIR_FrInt_MASK (0xFFFF<<0) /**< frame interval mask. */
|
|
|
|
|
#define HFIR_FrInt(n) ((n)<<0) /**< frame interval value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name HFNUM register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
|
|
|
|
#define HFNUM_FrRem_MASK (0xFFFF<<16)/**< frame time Remaining
|
|
|
|
|
mask. */
|
|
|
|
|
#define HFNUM_FrRem(n) ((n)<<16) /**< frame time Remaining
|
|
|
|
|
value. */
|
|
|
|
|
#define HFNUM_FrNum_MASK (0xFFFF<<0) /**< frame number mask. */
|
|
|
|
|
#define HFNUM_FrNum(n) ((n)<<0) /**< frame number value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name HPTXSTS register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
|
|
|
|
#define HPTXSTS_PTxQTop_MASK (0xFF<<24) /**< Top of the periodic
|
2012-03-05 20:39:09 +00:00
|
|
|
transmit request queue
|
2012-03-05 18:15:19 +00:00
|
|
|
mask. */
|
|
|
|
|
#define HPTXSTS_PTxQTop(n) ((n)<<24) /**< Top of the periodic
|
2012-03-05 20:39:09 +00:00
|
|
|
transmit request queue
|
2012-03-05 18:15:19 +00:00
|
|
|
value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HPTXSTS_PTxQSpcAvail_MASK (0xFF<<16) /**< periodic transmit request
|
2012-03-05 18:15:19 +00:00
|
|
|
queue Space Available
|
|
|
|
|
mask. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HPTXSTS_PTxQSpcAvail(n) ((n)<<16) /**< periodic transmit request
|
2012-03-05 18:15:19 +00:00
|
|
|
queue Space Available
|
|
|
|
|
value. */
|
|
|
|
|
#define HPTXSTS_PTxFSpcAvail_MASK (0xFFFF<<0) /**< periodic transmit Data
|
|
|
|
|
FIFO Space Available
|
|
|
|
|
mask. */
|
|
|
|
|
#define HPTXSTS_PTxFSpcAvail(n) ((n)<<0) /**< periodic transmit Data
|
|
|
|
|
FIFO Space Available
|
|
|
|
|
value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name HAINT register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
|
|
|
|
#define HAINT_HAINT_MASK (0xFFFF<<0) /**< channel interrupts
|
|
|
|
|
mask. */
|
|
|
|
|
#define HAINT_HAINT(n) ((n)<<0) /**< channel interrupts
|
|
|
|
|
value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name HAINTMSK register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
|
|
|
|
#define HAINTMSK_HAINTMsk_MASK (0xFFFF<<0) /**< channel interrupt mask
|
|
|
|
|
mask. */
|
|
|
|
|
#define HAINTMSK_HAINTMsk(n) ((n)<<0) /**< channel interrupt mask
|
|
|
|
|
value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name HPRT register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
|
|
|
|
#define HPRT_PrtSpd_MASK (3<<17) /**< port Speed mask. */
|
|
|
|
|
#define HPRT_PrtSpd_HS (0<<17) /**< High Speed value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HPRT_PrtSpd_FS (1U<<17) /**< Full Speed value. */
|
2012-03-05 18:15:19 +00:00
|
|
|
#define HPRT_PrtSpd_LS (2<<17) /**< Low Speed value. */
|
|
|
|
|
#define HPRT_PrtTstCtl_MASK (15<<13) /**< port Test control mask.*/
|
|
|
|
|
#define HPRT_PrtTstCtl(n) ((n)<<13) /**< port Test control
|
|
|
|
|
value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HPRT_PrtPwr (1U<<12) /**< port power. */
|
2012-03-05 18:15:19 +00:00
|
|
|
#define HPRT_PrtLnSts_MASK (3<<11) /**< port Line status mask. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HPRT_PrtLnSts_DM (1U<<11) /**< Logic level of D-. */
|
|
|
|
|
#define HPRT_PrtLnSts_DP (1U<<10) /**< Logic level of D+. */
|
|
|
|
|
#define HPRT_PrtRst (1U<<8) /**< port reset. */
|
|
|
|
|
#define HPRT_PrtSusp (1U<<7) /**< port suspend. */
|
|
|
|
|
#define HPRT_PrtRes (1U<<6) /**< port Resume. */
|
|
|
|
|
#define HPRT_PrtOvrCurrChng (1U<<5) /**< port Overcurrent
|
|
|
|
|
change. */
|
|
|
|
|
#define HPRT_PrtOvrCurrAct (1U<<4) /**< port Overcurrent
|
2012-03-05 18:15:19 +00:00
|
|
|
Active. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HPRT_PrtEnChng (1U<<3) /**< port enable/Disable
|
|
|
|
|
change. */
|
|
|
|
|
#define HPRT_PrtEna (1U<<2) /**< port enable. */
|
|
|
|
|
#define HPRT_PrtConnDet (1U<<1) /**< port Connect detected. */
|
|
|
|
|
#define HPRT_PrtConnSts (1U<<0) /**< .*/
|
|
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name HCCHAR register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCCHAR_ChEna (1u<<31) /**< channel enable. */
|
|
|
|
|
#define HCCHAR_ChDis (1U<<30) /**< channel Disable. */
|
|
|
|
|
#define HCCHAR_OddFrm (1U<<29) /**< Odd frame. */
|
2012-03-05 18:15:19 +00:00
|
|
|
#define HCCHAR_DevAddr_MASK (0x7F<<22) /**< Device Address mask. */
|
|
|
|
|
#define HCCHAR_DevAddr(n) ((n)<<22) /**< Device Address value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCCHAR_MC_EC_MASK (3<<20) /**< Multi count (MC) / Error
|
|
|
|
|
count mask. */
|
|
|
|
|
#define HCCHAR_MC_EC(n) ((n)<<20) /**< Multi count (MC) / Error
|
|
|
|
|
count value. */
|
2012-03-05 18:15:19 +00:00
|
|
|
#define HCCHAR_EPType_MASK (3<<18) /**< .*/
|
|
|
|
|
#define HCCHAR_EPType(n) ((n)<<18) /**< endpoint Type mask. */
|
|
|
|
|
#define HCCHAR_EPType_control (0<<18) /**< control endpoint value.*/
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCCHAR_EPType_isochronous (1U<<18) /**< isochronous endpoint
|
2012-03-05 18:15:19 +00:00
|
|
|
value. */
|
|
|
|
|
#define HCCHAR_EPType_Bulk (2<<18) /**< Bulk endpoint value. */
|
|
|
|
|
#define HCCHAR_EPType_interrupt (3<<18) /**< interrupt endpoint
|
|
|
|
|
value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCCHAR_LSpdDev (1U<<17) /**< Low-Speed Device. */
|
|
|
|
|
#define HCCHAR_EPDir (1U<<15) /**< endpoint Direction. */
|
2012-03-05 18:15:19 +00:00
|
|
|
#define HCCHAR_EPNum_MASK (15<<11) /**< endpoint number mask. */
|
|
|
|
|
#define HCCHAR_EPNum(n) ((n)<<11) /**< endpoint number value. */
|
|
|
|
|
#define HCCHAR_MPS_MASK (11<<0) /**< Maximum Packet size
|
|
|
|
|
mask. */
|
|
|
|
|
#define HCCHAR_MPS(n) (11<<0) /**< Maximum Packet size
|
|
|
|
|
value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name HCSPLT register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCSPLT_SpltEna (1u<<31) /**< Split enable. */
|
|
|
|
|
#define HCSPLT_CompSplt (1U<<16) /**< Do Complete Split. */
|
2012-03-05 18:15:19 +00:00
|
|
|
#define HCSPLT_XactPos_MASK (3<<14) /**< Transaction Position. */
|
|
|
|
|
#define HCSPLT_XactPos_Mid (0<<14) /**< Middle. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCSPLT_XactPos_end (1U<<14) /**< End. */
|
2012-03-05 18:15:19 +00:00
|
|
|
#define HCSPLT_XactPos_Begin (2<<14) /**< Begin. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCSPLT_XactPos_all (3<<14) /**< All. */
|
2012-03-05 18:15:19 +00:00
|
|
|
#define HCSPLT_HubAddr_MASK (0x7F<<6) /**< Hub Address mask. */
|
|
|
|
|
#define HCSPLT_HubAddr(n) ((n)<<n) /**< Hub Address value. */
|
|
|
|
|
#define HCSPLT_PrtAddr_MASK (0x7F<<0) /**< port Address mask. */
|
|
|
|
|
#define HCSPLT_PrtAddr(n) ((n)<<0) /**< port Address value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name HCINT register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCINT_DataTglErr (1U<<10) /**< Data Toggle Error. */
|
|
|
|
|
#define HCINT_FrmOvrun (1U<<9) /**< frame Overrun. */
|
|
|
|
|
#define HCINT_BblErr (1U<<8) /**< Babble Error. */
|
|
|
|
|
#define HCINT_XactErr (1U<<7) /**< Transaction Error. */
|
|
|
|
|
#define HCINT_NYET (1U<<6) /**< NYET Response Received
|
2012-03-05 18:15:19 +00:00
|
|
|
interrupt. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCINT_ACK (1U<<5) /**< ACK Response
|
2012-03-05 18:15:19 +00:00
|
|
|
Received/transmitted
|
|
|
|
|
interrupt. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCINT_NAK (1U<<4) /**< NAK Response Received
|
2012-03-05 18:15:19 +00:00
|
|
|
interrupt. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCINT_STALL (1U<<3) /**< STALL Response Received
|
2012-03-05 18:15:19 +00:00
|
|
|
interrupt. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCINT_ChHltd (1U<<1) /**< channel Halted. */
|
|
|
|
|
#define HCINT_XferCompl (1U<<0) /**< transfer completed. */
|
|
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name HCINTMSK register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCINTMSK_DataTglErrMsk (1U<<10) /**< Data Toggle Error mask.*/
|
|
|
|
|
#define HCINTMSK_FrmOvrunMsk (1U<<9) /**< frame Overrun mask. */
|
|
|
|
|
#define HCINTMSK_BblErrMsk (1U<<8) /**< Babble Error mask. */
|
|
|
|
|
#define HCINTMSK_XactErrMsk (1U<<7) /**< Transaction Error mask.*/
|
|
|
|
|
#define HCINTMSK_NyetMsk (1U<<6) /**< NYET Response Received
|
2012-03-05 18:15:19 +00:00
|
|
|
interrupt mask. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCINTMSK_AckMsk (1U<<5) /**< ACK Response
|
2012-03-05 18:15:19 +00:00
|
|
|
Received/transmitted
|
|
|
|
|
interrupt mask. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCINTMSK_NakMsk (1U<<4) /**< NAK Response Received
|
2012-03-05 18:15:19 +00:00
|
|
|
interrupt mask. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCINTMSK_StallMsk (1U<<3) /**< STALL Response Received
|
2012-03-05 18:15:19 +00:00
|
|
|
interrupt mask. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCINTMSK_ChHltdMsk (1U<<1) /**< channel Halted mask. */
|
|
|
|
|
#define HCINTMSK_XferComplMsk (1U<<0) /**< transfer completed
|
2012-03-05 18:15:19 +00:00
|
|
|
mask.*/
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name HCTSIZ register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCTSIZ_DoPng (1U<<31) /**< Do Ping. */
|
2012-03-05 18:15:19 +00:00
|
|
|
#define HCTSIZ_Pid_MASK (3<<29) /**< PID mask. */
|
|
|
|
|
#define HCTSIZ_Pid_DATA0 (0<<29) /**< DATA0. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define HCTSIZ_Pid_DATA2 (1U<<29) /**< DATA2. */
|
2012-03-05 18:15:19 +00:00
|
|
|
#define HCTSIZ_Pid_DATA1 (2<<29) /**< DATA1. */
|
|
|
|
|
#define HCTSIZ_Pid_MDATA (3<<29) /**< MDATA. */
|
|
|
|
|
#define HCTSIZ_Xfersize_MASK (0x7FFFF<<0)/**< transfer size mask. */
|
|
|
|
|
#define HCTSIZ_Xfersize(n) ((n)<<0) /**< transfer size value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name DCFG register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
|
|
|
|
#define DCFG_ResValid_MASK (0x3F<<26) /**< Resume Validation Period
|
|
|
|
|
mask. */
|
|
|
|
|
#define DCFG_ResValid(n) ((n)<<26) /**< Resume Validation Period
|
|
|
|
|
value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DCFG_EPMiscnt_MASK (0x1F<<18) /**< IN endpoint Mismatch
|
|
|
|
|
count mask. */
|
|
|
|
|
#define DCFG_EPMiscnt(n) ((n)<<18) /**< IN endpoint Mismatch
|
|
|
|
|
count value. */
|
2012-03-05 18:15:19 +00:00
|
|
|
#define DCFG_PerFrInt_MASK (3<<11) /**< periodic frame interval
|
|
|
|
|
mask. */
|
|
|
|
|
#define DCFG_PerFrInt(n) ((n)<<11) /**< periodic frame interval
|
|
|
|
|
value. */
|
|
|
|
|
#define DCFG_DevAddr_MASK (0x7F<<4) /**< Device Address mask. */
|
|
|
|
|
#define DCFG_DevAddr(n) ((n)<<4) /**< Device Address value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DCFG_Ena32KHzS (1U<<3) /**< enable 32-KHz suspend
|
2012-03-05 18:15:19 +00:00
|
|
|
Mode. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DCFG_NZStsOUTHShk (1U<<2) /**< non-Zero-Length status
|
2012-03-05 18:15:19 +00:00
|
|
|
OUT Handshake. */
|
|
|
|
|
#define DCFG_DevSpd_MASK (3<<0) /**< Device Speed mask. */
|
|
|
|
|
#define DCFG_DevSpd_HS20 (0<<0) /**< High speed (USB 2.0 PHY
|
|
|
|
|
clock is 30 MHz or 60
|
|
|
|
|
MHz). */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DCFG_DevSpd_FS20 (1U<<0) /**< Full speed (USB 2.0 PHY
|
2012-03-05 18:15:19 +00:00
|
|
|
clock is 30 MHz or 60
|
|
|
|
|
MHz). */
|
|
|
|
|
#define DCFG_DevSpd_Reserved (2<<0) /**< Reserved. */
|
|
|
|
|
#define DCFG_DevSpd_FS11 (3<<0) /**< Full speed (USB 1.1
|
|
|
|
|
transceiver clock is 48
|
|
|
|
|
MHz). */
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name DCTL register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DCTL_NakOnBble (1U<<16) /**< Set NAK automatically on
|
2012-03-05 18:15:19 +00:00
|
|
|
babble. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DCTL_PWROnPrgdone (1U<<11) /**< power-On Programming
|
|
|
|
|
done. */
|
|
|
|
|
#define DCTL_CGOUTNak (1U<<10) /**< Clear Global OUT NAK. */
|
|
|
|
|
#define DCTL_SGOUTNak (1U<<9) /**< Set Global OUT NAK. */
|
|
|
|
|
#define DCTL_CGNPInNak (1U<<8) /**< Clear Global non-periodic
|
2012-03-05 18:15:19 +00:00
|
|
|
IN NAK. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DCTL_SGNPInNak (1U<<7) /**< Set Global non-periodic
|
2012-03-05 18:15:19 +00:00
|
|
|
IN NAK. */
|
|
|
|
|
#define DCTL_TstCtl_MASK (7<<4) /**< Test control mask. */
|
|
|
|
|
#define DCTL_TstCtl(n) ((n)<<4) /**< Test control value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DCTL_GOUTNakSts (1U<<3) /**< Global OUT NAK status. */
|
|
|
|
|
#define DCTL_GNPINNakSts (1U<<2) /**< Global non-periodic IN
|
2012-03-05 18:15:19 +00:00
|
|
|
NAK status. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DCTL_SftDiscon (1U<<1) /**< Soft disconnect. */
|
|
|
|
|
#define DCTL_RmtWkUpSig (1U<<0) /**< Remote wakeup
|
|
|
|
|
signaling. */
|
|
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name DSTS register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
|
|
|
|
#define DSTS_SOFFN_MASK (0x3FFF<<8) /**< frame or Microframe
|
|
|
|
|
number of the Received
|
|
|
|
|
SOF mask. */
|
|
|
|
|
#define DSTS_SOFFN(n) ((n)<<8) /**< frame or Microframe
|
|
|
|
|
number of the Received
|
|
|
|
|
SOF value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DSTS_ErrticErr (1U<<3) /**< Erratic Error. */
|
2012-03-05 18:15:19 +00:00
|
|
|
#define DSTS_EnumSpd_MASK (3<<1) /**< Enumerated Speed mask. */
|
|
|
|
|
#define DSTS_EnumSpd_HS_30_60 (0<<1) /**< High speed (PHY clock is
|
|
|
|
|
running at 30 or 60
|
|
|
|
|
MHz). */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DSTS_EnumSpd_FS_30_60 (1U<<1) /**< Full speed (PHY clock is
|
2012-03-05 18:15:19 +00:00
|
|
|
running at 30 or 60
|
|
|
|
|
MHz). */
|
|
|
|
|
#define DSTS_EnumSpd_LS_48_6 (2<<1) /**< Low speed (PHY clock is
|
|
|
|
|
running at 48 MHz,
|
|
|
|
|
internal phy_clk at 6
|
|
|
|
|
MHz). */
|
|
|
|
|
#define DSTS_EnumSpd_FS_48 (3<<1) /**< Full speed (PHY clock is
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running at 48 MHz). */
|
2012-03-05 20:39:09 +00:00
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#define DSTS_SuspSts (1U<<0) /**< suspend status. */
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/** @} */
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2012-03-05 18:15:19 +00:00
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2012-03-05 20:39:09 +00:00
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/**
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* @name DIEPMSK register bit definitions
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* @{
|
2012-03-05 18:15:19 +00:00
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*/
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2012-03-05 20:39:09 +00:00
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#define DIEPMSK_NAKMsk (1U<<13) /**< NAK interrupt mask. */
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#define DIEPMSK_BNAInIntrMsk (1U<<9) /**< BNA interrupt mask. */
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#define DIEPMSK_TxfifoUndrnMsk (1U<<8) /**< Fifo Underrun mask. */
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#define DIEPMSK_INEPNakEffMsk (1U<<6) /**< IN endpoint NAK Effective
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2012-03-05 18:15:19 +00:00
|
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mask. */
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2012-03-05 20:39:09 +00:00
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#define DIEPMSK_INTknEPMisMsk (1U<<5) /**< IN Token received with
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2012-03-05 18:15:19 +00:00
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EP Mismatch mask. */
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2012-03-05 20:39:09 +00:00
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#define DIEPMSK_INTknTXFEmpMsk (1U<<4) /**< IN Token Received When
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TxFIFO empty mask. */
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#define DIEPMSK_timeOUTMsk (1U<<3) /**< timeout condition mask.*/
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#define DIEPMSK_AHBErrMsk (1U<<2) /**< AHB Error mask. */
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#define DIEPMSK_EPDisbldMsk (1U<<1) /**< endpoint disabled
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2012-03-05 18:15:19 +00:00
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interrupt mask. */
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2012-03-05 20:39:09 +00:00
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#define DIEPMSK_XferComplMsk (1U<<0) /**< transfer completed
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2012-03-05 18:15:19 +00:00
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interrupt mask. */
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2012-03-05 20:39:09 +00:00
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/** @} */
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2012-03-05 18:15:19 +00:00
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2012-03-05 20:39:09 +00:00
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/**
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* @name DOEPMSK register bit definitions
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* @{
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*/
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#define DOEPMSK_NYETMsk (1U<<14) /**< NYET interrupt mask. */
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#define DOEPMSK_NAKMsk (1U<<13) /**< NAK interrupt mask. */
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#define DOEPMSK_BbleErrMsk (1U<<12) /**< Babble interrupt mask. */
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#define DOEPMSK_BnaOutIntrMsk (1U<<9) /**< BNA interrupt mask. */
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#define DOEPMSK_OutPktErrMsk (1U<<8) /**< OUT Packet Error mask. */
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#define DOEPMSK_Back2BackSETup (1U<<6) /**< Back-to-Back SETUP
|
2012-03-05 18:15:19 +00:00
|
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Packets Received mask. */
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2012-03-05 20:39:09 +00:00
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#define DOEPMSK_OUTTknEPdisMsk (1U<<4) /**< OUT Token Received when
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endpoint disabled mask.*/
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#define DOEPMSK_SetUPMsk (1U<<3) /**< SETUP phase done mask. */
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#define DOEPMSK_AHBErrMsk (1U<<2) /**< AHB Error. */
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#define DOEPMSK_EPDisbldMsk (1U<<1) /**< endpoint disabled
|
2012-03-05 18:15:19 +00:00
|
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interrupt mask. */
|
2012-03-05 20:39:09 +00:00
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#define DOEPMSK_XferComplMsk (1U<<0) /**< transfer completed
|
2012-03-05 18:15:19 +00:00
|
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interrupt mask. */
|
2012-03-05 20:39:09 +00:00
|
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/** @} */
|
2012-03-05 18:15:19 +00:00
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2012-03-05 20:39:09 +00:00
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/**
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* @name DAINT register bit definitions
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* @{
|
2012-03-05 18:15:19 +00:00
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*/
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#define DAINT_OutEPInt_MASK (0xFFFF<<16)/**< OUT endpoint interrupt
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Bits mask. */
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#define DAINT_OutEPInt(n) ((n)<<16) /**< OUT endpoint interrupt
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Bits value. */
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#define DAINT_InEpInt_MASK (0xFFFF<<0) /**< IN endpoint interrupt
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Bits mask. */
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#define DAINT_InEpInt(n) ((n)<<0) /**< IN endpoint interrupt
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Bits value. */
|
2012-03-05 20:39:09 +00:00
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|
/** @} */
|
2012-03-05 18:15:19 +00:00
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2012-03-05 20:39:09 +00:00
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/**
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|
* @name DAINTMSK register bit definitions
|
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|
* @{
|
2012-03-05 18:15:19 +00:00
|
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*/
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#define DAINTMSK_OutEpMsk_MASK (0xFFFF<<16)/**< OUT EP interrupt mask
|
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Bits mask. */
|
2012-03-05 20:39:09 +00:00
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#define DAINTMSK_OutEpMsk(n) (1U<<(16+(n)))/**< OUT EP interrupt mask
|
2012-03-05 18:15:19 +00:00
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Bits value. */
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|
#define DAINTMSK_InEpMsk_MASK (0xFFFF<<0) /**< IN EP interrupt mask
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Bits mask. */
|
2012-03-05 20:39:09 +00:00
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#define DAINTMSK_InEpMsk(n) (1U<<(n)) /**< IN EP interrupt mask
|
2012-03-05 18:15:19 +00:00
|
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Bits value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
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|
2012-03-05 20:39:09 +00:00
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/**
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|
* @name DVBUSDIS register bit definitions
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|
* @{
|
2012-03-05 18:15:19 +00:00
|
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*/
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#define DVBUSDIS_DVBUSDis_MASK (0xFFFF<<0) /**< Device VBUS Discharge
|
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|
time mask. */
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|
#define DVBUSDIS_DVBUSDis(n) ((n)<<0) /**< Device VBUS Discharge
|
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|
time value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
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|
2012-03-05 20:39:09 +00:00
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|
/**
|
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|
|
* @name DVBUSPULSE register bit definitions
|
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|
* @{
|
2012-03-05 18:15:19 +00:00
|
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|
*/
|
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|
#define DVBUSPULSE_DVBUSPulse_MASK (0xFFF<<0) /**< Device VBUS Pulsing time
|
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|
|
mask. */
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|
#define DVBUSPULSE_DVBUSPulse(n) ((n)<<0) /**< Device VBUS Pulsing time
|
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|
|
value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
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|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
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|
|
* @name DIEPCTL register bit definitions
|
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|
|
* @{
|
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|
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|
*/
|
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|
#define DIEPCTL_EPEna (1u<<31) /**< endpoint enable. */
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|
#define DIEPCTL_EPDis (1U<<30) /**< endpoint Disable. */
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|
#define DIEPCTL_SetD1PID (1U<<29) /**< Set DATA1 PID. */
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|
#define DIEPCTL_SetD0PID (1U<<28) /**< Set DATA0 PID. */
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|
#define DIEPCTL_SNAK (1U<<27) /**< Set NAK. */
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|
#define DIEPCTL_CNAK (1U<<26) /**< Clear NAK. */
|
2012-03-05 18:15:19 +00:00
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|
#define DIEPCTL_TxFNum_MASK (15<<22) /**< TxFIFO number mask. */
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|
#define DIEPCTL_TxFNum(n) ((n)<<22) /**< TxFIFO number value. */
|
2012-03-05 20:39:09 +00:00
|
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|
#define DIEPCTL_Stall (1U<<21) /**< STALL Handshake. */
|
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|
#define DIEPCTL_Snp (1U<<20) /**< Snoop Mode. */
|
2012-03-05 18:15:19 +00:00
|
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|
#define DIEPCTL_EPType_MASK (3<<18) /**< endpoint Type mask. */
|
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|
#define DIEPCTL_EPType_control (0<<18) /**< control. */
|
2012-03-05 20:39:09 +00:00
|
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|
#define DIEPCTL_EPType_isochronous (1U<<18) /**< isochronous. */
|
2012-03-05 18:15:19 +00:00
|
|
|
#define DIEPCTL_EPType_Bulk (2<<18) /**< Bulk. */
|
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|
|
|
#define DIEPCTL_EPType_interrupt (3<<18) /**< interrupt. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DIEPCTL_NAKSts (1U<<17) /**< NAK status. */
|
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|
|
#define DIEPCTL_DPID (1U<<16) /**< endpoint Data PID. */
|
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|
|
#define DIEPCTL_USBActEP (1U<<15) /**< USB Active endpoint. */
|
2012-03-05 18:15:19 +00:00
|
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|
#define DIEPCTL_NextEp_MASK (15<<11) /**< Next endpoint mask. */
|
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|
#define DIEPCTL_NextEp(n) ((n)<<11) /**< Next endpoint value. */
|
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|
|
|
#define DIEPCTL_MPS_MASK (0x3FF<<0) /**< Maximum Packet size
|
|
|
|
|
mask. */
|
|
|
|
|
#define DIEPCTL_MPS(n) ((n)<<0) /**< Maximum Packet size
|
|
|
|
|
value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name DIEPINT register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DIEPINT_NYETIntrpt (1U<<14) /**< NYET interrupt. */
|
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|
|
|
#define DIEPINT_NAKIntrpt (1U<<13) /**< NAK interrupt. */
|
|
|
|
|
#define DIEPINT_BbleErrIntrpt (1U<<12) /**< BbleErr (Babble Error)
|
2012-03-05 18:15:19 +00:00
|
|
|
interrupt. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DIEPINT_TxFEmp (1U<<7) /**< transmit FIFO empty. */
|
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|
|
|
#define DIEPINT_INEPNakEff (1U<<6) /**< IN endpoint NAK
|
2012-03-05 18:15:19 +00:00
|
|
|
Effective. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DIEPINT_INTknEPMis (1U<<5) /**< IN Token Received with
|
2012-03-05 18:15:19 +00:00
|
|
|
EP Mismatch. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DIEPINT_INTknTXFEmp (1U<<4) /**< IN Token Received When
|
|
|
|
|
TxFIFO is empty. */
|
|
|
|
|
#define DIEPINT_timeOUT (1U<<3) /**< timeout condition. */
|
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|
|
|
#define DIEPINT_AHBErr (1U<<2) /**< AHB Error. */
|
|
|
|
|
#define DIEPINT_EPDisbld (1U<<1) /**< endpoint disabled
|
2012-03-05 18:15:19 +00:00
|
|
|
interrupt. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DIEPINT_XferCompl (1U<<0) /**< transfer completed */
|
|
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name DIEPTSIZ register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DIEPTSIZ_MC_MASK (3<<29) /**< Multi count mask. */
|
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|
|
|
#define DIEPTSIZ_MC(n) ((n)<<29) /**< Multi count value. */
|
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|
|
|
#define DIEPTSIZ_Pktcnt_MASK (0x3FF<<19) /**< Packet count mask. */
|
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|
|
|
#define DIEPTSIZ_Pktcnt(n) ((n)<<19) /**< Packet count value. */
|
2012-03-05 18:15:19 +00:00
|
|
|
#define DIEPTSIZ_Xfersize_MASK (0x7FFFF<<0)/**< transfer size mask. */
|
|
|
|
|
#define DIEPTSIZ_Xfersize(n) ((n)<<0) /**< transfer size value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name DOEPCTL register bit definitions.
|
|
|
|
|
* @{
|
|
|
|
|
*/
|
|
|
|
|
#define DOEPCTL_EPEna (1u<<31) /**< endpoint enable. */
|
|
|
|
|
#define DOEPCTL_EPDis (1U<<30) /**< endpoint Disable. */
|
|
|
|
|
#define DOEPCTL_SetOddFr (1U<<29) /**< Set Odd (micro)frame. */
|
|
|
|
|
#define DOEPCTL_SetEvenFr (1U<<28) /**< Set Even (micro)frame. */
|
|
|
|
|
#define DOEPCTL_SNAK (1U<<27) /**< Set NAK. */
|
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|
|
|
#define DOEPCTL_CNAK (1U<<26) /**< Clear NAK. */
|
|
|
|
|
#define DOEPCTL_Stall (1U<<21) /**< STALL Handshake. */
|
|
|
|
|
#define DOEPCTL_Snp (1U<<20) /**< Snoop Mode. */
|
2012-03-05 18:15:19 +00:00
|
|
|
#define DOEPCTL_EPType_MASK (3<<18) /**< endpoint Type mask. */
|
|
|
|
|
#define DOEPCTL_EPType_control (0<<18) /**< control. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DOEPCTL_EPType_isochronous (1U<<18) /**< Isochronous. */
|
2012-03-05 18:15:19 +00:00
|
|
|
#define DOEPCTL_EPType_Bulk (2<<18) /**< Bulk. */
|
|
|
|
|
#define DOEPCTL_EPType_interrupt (3<<18) /**< interrupt. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DOEPCTL_NAKSts (1U<<17) /**< NAK status. */
|
|
|
|
|
#define DOEPCTL_EO_FrNum (1U<<16) /**< Even/Odd (Micro)frame. */
|
|
|
|
|
#define DOEPCTL_USBActEP (1U<<15) /**< USB Active endpoint. */
|
2012-03-05 18:15:19 +00:00
|
|
|
#define DOEPCTL_NextEp_MASK (15<<11) /**< Next endpoint mask. */
|
|
|
|
|
#define DOEPCTL_NextEp(n) ((n)<<11) /**< Next endpoint value. */
|
|
|
|
|
#define DOEPCTL_MPS_MASK (0x3FF<<0) /**< Maximum Packet size
|
|
|
|
|
mask. */
|
|
|
|
|
#define DOEPCTL_MPS(n) ((n)<<0) /**< Maximum Packet size
|
|
|
|
|
value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name DOEPINT register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DOEPINT_NYETIntrpt (1U<<14) /**< NYET interrupt. */
|
|
|
|
|
#define DOEPINT_NAKIntrpt (1U<<13) /**< NAK interrupt. */
|
|
|
|
|
#define DOEPINT_BbleErrIntrpt (1U<<12) /**< BbleErr (Babble Error)
|
2012-03-05 18:15:19 +00:00
|
|
|
interrupt. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DOEPINT_Back2BackSETup (1U<<6) /**< Back-to-Back SETUP
|
2012-03-05 18:15:19 +00:00
|
|
|
Packets Received. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DOEPINT_OUTTknEPdis (1U<<4) /**< OUT Token Received When
|
|
|
|
|
endpoint disabled. */
|
|
|
|
|
#define DOEPINT_SetUp (1U<<3) /**< SETUP phase done. */
|
|
|
|
|
#define DOEPINT_AHBErr (1U<<2) /**< AHB Error. */
|
|
|
|
|
#define DOEPINT_EPDisbld (1U<<1) /**< endpoint disabled
|
2012-03-05 18:15:19 +00:00
|
|
|
interrupt. */
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DOEPINT_XferCompl (1U<<0) /**< transfer completed
|
2012-03-05 18:15:19 +00:00
|
|
|
interrupt. */
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name DOEPTSIZ register bit definitions
|
|
|
|
|
* @{
|
2012-03-05 18:15:19 +00:00
|
|
|
*/
|
2012-03-05 20:39:09 +00:00
|
|
|
#define DOEPTSIZ_SUPcnt_MASK (3<<29) /**< SETUP Packet cnt mask. */
|
|
|
|
|
#define DOEPTSIZ_SUPcnt(n) ((n)<<29) /**< SETUP Packet cnt value.*/
|
|
|
|
|
#define DOEPTSIZ_Pktcnt_MASK (0x3FF<<19) /**< Packet count mask. */
|
|
|
|
|
#define DOEPTSIZ_Pktcnt(n) ((n)<<19) /**< Packet count value. */
|
2012-03-05 18:15:19 +00:00
|
|
|
#define DOEPTSIZ_Xfersize_MASK (0x7FFFF<<0)/**< transfer size mask. */
|
|
|
|
|
#define DOEPTSIZ_Xfersize(n) ((n)<<0) /**< transfer size value. */
|
2012-03-05 20:39:09 +00:00
|
|
|
/** @} */
|
2012-03-05 18:15:19 +00:00
|
|
|
|
2012-03-05 20:39:09 +00:00
|
|
|
/**
|
|
|
|
|
* @name PCGCCTL register bit definitions
|
|
|
|
|
* @{
|
|
|
|
|
*/
|
|
|
|
|
#define PCGCCTL_resetafterSusp (1U<<8) /**< reset after suspend. */
|
|
|
|
|
#define PCGCCTL_L1suspended (1U<<7) /**< Deep sleep. */
|
|
|
|
|
#define PCGCCTL_Physleep (1U<<6) /**< PHY in sleep. */
|
|
|
|
|
#define PCGCCTL_Enbl_L1gating (1U<<5) /**< enable sleep clock
|
|
|
|
|
gating. */
|
|
|
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#define PCGCCTL_RstPdwnModule (1U<<3) /**< reset power-down
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modules. */
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#define PCGCCTL_PwrClmp (1U<<2) /**< Power clamp. */
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#define PCGCCTL_GateHclk (1U<<1) /**< Gate Hclk. */
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#define PCGCCTL_StopPclk (1U<<0) /**< Stop Pclk. */
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/** @} */
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2012-03-05 18:15:19 +00:00
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/**
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* @brief OTG registers block memory address.
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*/
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#define OTG_ADDR 0x50000000
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/**
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* @brief Accesses to the OTG registers block.
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*/
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#define OTG ((stm32_otg_t *)OTG_ADDR)
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/**
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* @brief Returns a FIFO address.
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*/
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#define OTG_FIFO(n) ((volatile uint32_t *)(OTG_ADDR + \
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0x1000 +
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(0x1000 * (n))))
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#endif /* _STM32_OTG_H_ */
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/** @} */
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