2010-11-14 16:47:38 +00:00
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/*
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2011-03-18 18:38:08 +00:00
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011 Giovanni Di Sirio.
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2010-11-14 16:47:38 +00:00
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @defgroup STM32F100_HAL STM32F100 HAL Support
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* @details HAL support for STM32 Value Line LD, MD and HD sub-families.
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*
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* @ingroup HAL
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*/
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/**
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* @file STM32/hal_lld_f100.h
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* @brief STM32F100 Value Line HAL subsystem low level driver header.
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*
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* @addtogroup STM32F100_HAL
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* @{
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*/
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#ifndef _HAL_LLD_F100_H_
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#define _HAL_LLD_F100_H_
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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#define STM32_HSICLK 8000000 /**< High speed internal clock. */
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#define STM32_LSICLK 40000 /**< Low speed internal clock. */
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/* RCC_CFGR register bits definitions.*/
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#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */
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#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */
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#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */
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#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */
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#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */
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#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */
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#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */
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#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */
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#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */
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#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */
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#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */
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#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */
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#define STM32_PPRE1_DIV1 (0 << 8) /**< HCLK divided by 1. */
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#define STM32_PPRE1_DIV2 (4 << 8) /**< HCLK divided by 2. */
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#define STM32_PPRE1_DIV4 (5 << 8) /**< HCLK divided by 4. */
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#define STM32_PPRE1_DIV8 (6 << 8) /**< HCLK divided by 8. */
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#define STM32_PPRE1_DIV16 (7 << 8) /**< HCLK divided by 16. */
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#define STM32_PPRE2_DIV1 (0 << 11) /**< HCLK divided by 1. */
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#define STM32_PPRE2_DIV2 (4 << 11) /**< HCLK divided by 2. */
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#define STM32_PPRE2_DIV4 (5 << 11) /**< HCLK divided by 4. */
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#define STM32_PPRE2_DIV8 (6 << 11) /**< HCLK divided by 8. */
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#define STM32_PPRE2_DIV16 (7 << 11) /**< HCLK divided by 16. */
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#define STM32_ADCPRE_DIV2 (0 << 14) /**< HCLK divided by 2. */
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#define STM32_ADCPRE_DIV4 (1 << 14) /**< HCLK divided by 4. */
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#define STM32_ADCPRE_DIV6 (2 << 14) /**< HCLK divided by 6. */
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#define STM32_ADCPRE_DIV8 (3 << 14) /**< HCLK divided by 8. */
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#define STM32_PLLSRC_HSI (0 << 16) /**< PLL clock source is HSI. */
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#define STM32_PLLSRC_HSE (1 << 16) /**< PLL clock source is HSE. */
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#define STM32_PLLXTPRE_DIV1 (0 << 17) /**< HSE divided by 1. */
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#define STM32_PLLXTPRE_DIV2 (1 << 17) /**< HSE divided by 2. */
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#define STM32_MCO_NOCLOCK (0 << 24) /**< No clock on MCO pin. */
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#define STM32_MCO_SYSCLK (4 << 24) /**< SYSCLK on MCO pin. */
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#define STM32_MCO_HSI (5 << 24) /**< HSI clock on MCO pin. */
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#define STM32_MCO_HSE (6 << 24) /**< HSE clock on MCO pin. */
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#define STM32_MCO_PLLDIV2 (7 << 24) /**< PLL/2 clock on MCO pin. */
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2011-09-20 17:33:38 +00:00
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#define STM32_RTC_NOCLOCK (0 << 8) /**< No clock. */
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#define STM32_RTC_LSE (1 << 8) /**< LSE used as RTC clock. */
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#define STM32_RTC_LSI (2 << 8) /**< LSI used as RTC clock. */
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#define STM32_RTC_HSE (3 << 8) /**< HSE divided by 128 used as
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RTC clock. */
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2011-09-20 07:18:29 +00:00
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2010-11-14 16:47:38 +00:00
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/*===========================================================================*/
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/* Platform specific friendly IRQ names. */
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/*===========================================================================*/
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#define WWDG_IRQHandler Vector40 /**< Window Watchdog. */
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#define PVD_IRQHandler Vector44 /**< PVD through EXTI Line
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detect. */
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#define TAMPER_IRQHandler Vector48 /**< Tamper. */
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#define RTC_IRQHandler Vector4C /**< RTC. */
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#define FLASH_IRQHandler Vector50 /**< Flash. */
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#define RCC_IRQHandler Vector54 /**< RCC. */
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#define EXTI0_IRQHandler Vector58 /**< EXTI Line 0. */
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#define EXTI1_IRQHandler Vector5C /**< EXTI Line 1. */
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#define EXTI2_IRQHandler Vector60 /**< EXTI Line 2. */
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#define EXTI3_IRQHandler Vector64 /**< EXTI Line 3. */
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#define EXTI4_IRQHandler Vector68 /**< EXTI Line 4. */
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#define DMA1_Ch1_IRQHandler Vector6C /**< DMA1 Channel 1. */
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#define DMA1_Ch2_IRQHandler Vector70 /**< DMA1 Channel 2. */
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#define DMA1_Ch3_IRQHandler Vector74 /**< DMA1 Channel 3. */
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#define DMA1_Ch4_IRQHandler Vector78 /**< DMA1 Channel 4. */
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#define DMA1_Ch5_IRQHandler Vector7C /**< DMA1 Channel 5. */
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#define DMA1_Ch6_IRQHandler Vector80 /**< DMA1 Channel 6. */
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#define DMA1_Ch7_IRQHandler Vector84 /**< DMA1 Channel 7. */
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#define ADC1_2_IRQHandler Vector88 /**< ADC1_2. */
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#define EXTI9_5_IRQHandler Vector9C /**< EXTI Line 9..5. */
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#define TIM1_BRK_IRQHandler VectorA0 /**< TIM1 Break. */
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#define TIM1_UP_IRQHandler VectorA4 /**< TIM1 Update. */
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#define TIM1_TRG_COM_IRQHandler VectorA8 /**< TIM1 Trigger and
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Commutation. */
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#define TIM1_CC_IRQHandler VectorAC /**< TIM1 Capture Compare. */
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#define TIM2_IRQHandler VectorB0 /**< TIM2. */
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#define TIM3_IRQHandler VectorB4 /**< TIM3. */
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#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
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#define TIM4_IRQHandler VectorB8 /**< TIM4. */
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#endif
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#define I2C1_EV_IRQHandler VectorBC /**< I2C1 Event. */
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#define I2C1_ER_IRQHandler VectorC0 /**< I2C1 Error. */
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#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
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#define I2C2_EV_IRQHandler VectorC4 /**< I2C2 Event. */
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#define I2C2_ER_IRQHandler VectorC8 /**< I2C2 Error. */
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#endif
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#define SPI1_IRQHandler VectorCC /**< SPI1. */
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#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
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#define SPI2_IRQHandler VectorD0 /**< SPI2. */
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#endif
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#define USART1_IRQHandler VectorD4 /**< USART1. */
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#define USART2_IRQHandler VectorD8 /**< USART2. */
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#if !defined(STM32F10X_LD_VL) || defined(__DOXYGEN__)
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#define USART3_IRQHandler VectorDC /**< USART3. */
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#endif
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#define EXTI15_10_IRQHandler VectorE0 /**< EXTI Line 15..10. */
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2011-09-20 17:33:38 +00:00
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#define RTC_Alarm_IRQHandler VectorE4 /**< RTC Alarm through EXTI. */
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#define CEC_IRQHandler VectorE8 /**< CEC. */
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2010-11-14 16:47:38 +00:00
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#define TIM12_IRQHandler VectorEC /**< TIM12. */
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#define TIM13_IRQHandler VectorF0 /**< TIM13. */
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#define TIM14_IRQHandler VectorF4 /**< TIM14. */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief Main clock source selection.
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* @note If the selected clock source is not the PLL then the PLL is not
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* initialized and started.
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* @note The default value is calculated for a 72MHz system clock from
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* a 8MHz crystal using the PLL.
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*/
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#if !defined(STM32_SW) || defined(__DOXYGEN__)
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#define STM32_SW STM32_SW_PLL
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#endif
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/**
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* @brief Clock source for the PLL.
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* @note This setting has only effect if the PLL is selected as the
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* system clock source.
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* @note The default value is calculated for a 72MHz system clock from
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* a 8MHz crystal using the PLL.
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*/
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#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
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#define STM32_PLLSRC STM32_PLLSRC_HSE
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#endif
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/**
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* @brief Crystal PLL pre-divider.
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* @note This setting has only effect if the PLL is selected as the
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* system clock source.
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* @note The default value is calculated for a 72MHz system clock from
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* a 8MHz crystal using the PLL.
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*/
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#if !defined(STM32_PLLXTPRE) || defined(__DOXYGEN__)
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#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1
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#endif
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/**
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* @brief PLL multiplier value.
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* @note The allowed range is 2...16.
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* @note The default value is calculated for a 72MHz system clock from
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* a 8MHz crystal using the PLL.
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*/
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#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
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#define STM32_PLLMUL_VALUE 9
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#endif
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/**
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* @brief AHB prescaler value.
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* @note The default value is calculated for a 72MHz system clock from
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* a 8MHz crystal using the PLL.
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*/
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#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
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#define STM32_HPRE STM32_HPRE_DIV1
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#endif
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/**
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* @brief APB1 prescaler value.
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*/
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#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
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#define STM32_PPRE1 STM32_PPRE1_DIV2
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#endif
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/**
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* @brief APB2 prescaler value.
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*/
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#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
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#define STM32_PPRE2 STM32_PPRE2_DIV2
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#endif
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/**
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* @brief ADC prescaler value.
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*/
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#if !defined(STM32_ADCPRE) || defined(__DOXYGEN__)
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#define STM32_ADCPRE STM32_ADCPRE_DIV4
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#endif
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/**
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* @brief MCO pin setting.
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*/
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#if !defined(STM32_MCO) || defined(__DOXYGEN__)
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#define STM32_MCO STM32_MCO_NOCLOCK
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#endif
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2011-09-20 07:02:14 +00:00
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/**
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* @brief Clock source selecting. LSI by default.
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*/
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#if !defined(STM32_RTC) || defined(__DOXYGEN__)
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#define STM32_RTC STM32_RTC_LSI
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#endif
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2010-11-14 16:47:38 +00:00
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/* HSE prescaler setting check.*/
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#if (STM32_PLLXTPRE != STM32_PLLXTPRE_DIV1) && \
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(STM32_PLLXTPRE != STM32_PLLXTPRE_DIV2)
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#error "invalid STM32_PLLXTPRE value specified"
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#endif
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/**
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* @brief PLLMUL field.
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*/
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#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) || \
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defined(__DOXYGEN__)
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#define STM32_PLLMUL ((STM32_PLLMUL_VALUE - 2) << 18)
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#else
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#error "invalid STM32_PLLMUL_VALUE value specified"
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#endif
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/**
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* @brief PLL input clock frequency.
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*/
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#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
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#if STM32_PLLXTPRE == STM32_PLLXTPRE_DIV1
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#define STM32_PLLCLKIN (STM32_HSECLK / 1)
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#else
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#define STM32_PLLCLKIN (STM32_HSECLK / 2)
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#endif
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#elif STM32_PLLSRC == STM32_PLLSRC_HSI
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#define STM32_PLLCLKIN (STM32_HSICLK / 2)
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#else
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#error "invalid STM32_PLLSRC value specified"
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#endif
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/* PLL input frequency range check.*/
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#if (STM32_PLLCLKIN < 1000000) || (STM32_PLLCLKIN > 24000000)
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#error "STM32_PLLCLKIN outside acceptable range (1...24MHz)"
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#endif
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/**
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* @brief PLL output clock frequency.
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*/
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#define STM32_PLLCLKOUT (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
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/* PLL output frequency range check.*/
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#if (STM32_PLLCLKOUT < 16000000) || (STM32_PLLCLKOUT > 24000000)
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#error "STM32_PLLCLKOUT outside acceptable range (16...24MHz)"
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#endif
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/**
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* @brief System clock source.
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*/
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#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
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#define STM32_SYSCLK STM32_PLLCLKOUT
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#elif (STM32_SW == STM32_SW_HSI)
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#define STM32_SYSCLK STM32_HSICLK
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#elif (STM32_SW == STM32_SW_HSE)
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#define STM32_SYSCLK STM32_HSECLK
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#else
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#error "invalid STM32_SYSCLK_SW value specified"
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#endif
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/* Check on the system clock.*/
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#if STM32_SYSCLK > 24000000
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#error "STM32_SYSCLK above maximum rated frequency (24MHz)"
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#endif
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/**
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* @brief AHB frequency.
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*/
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#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
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#define STM32_HCLK (STM32_SYSCLK / 1)
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#elif STM32_HPRE == STM32_HPRE_DIV2
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#define STM32_HCLK (STM32_SYSCLK / 2)
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#elif STM32_HPRE == STM32_HPRE_DIV4
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#define STM32_HCLK (STM32_SYSCLK / 4)
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#elif STM32_HPRE == STM32_HPRE_DIV8
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#define STM32_HCLK (STM32_SYSCLK / 8)
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#elif STM32_HPRE == STM32_HPRE_DIV16
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#define STM32_HCLK (STM32_SYSCLK / 16)
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#elif STM32_HPRE == STM32_HPRE_DIV64
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#define STM32_HCLK (STM32_SYSCLK / 64)
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#elif STM32_HPRE == STM32_HPRE_DIV128
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#define STM32_HCLK (STM32_SYSCLK / 128)
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#elif STM32_HPRE == STM32_HPRE_DIV256
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#define STM32_HCLK (STM32_SYSCLK / 256)
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#elif STM32_HPRE == STM32_HPRE_DIV512
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#define STM32_HCLK (STM32_SYSCLK / 512)
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#else
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#error "invalid STM32_HPRE value specified"
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#endif
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/* AHB frequency check.*/
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#if STM32_HCLK > 24000000
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#error "STM32_HCLK exceeding maximum frequency (24MHz)"
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#endif
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/**
|
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* @brief APB1 frequency.
|
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*/
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|
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
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|
#define STM32_PCLK1 (STM32_HCLK / 1)
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|
#elif STM32_PPRE1 == STM32_PPRE1_DIV2
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|
#define STM32_PCLK1 (STM32_HCLK / 2)
|
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|
|
#elif STM32_PPRE1 == STM32_PPRE1_DIV4
|
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|
|
#define STM32_PCLK1 (STM32_HCLK / 4)
|
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|
|
#elif STM32_PPRE1 == STM32_PPRE1_DIV8
|
|
|
|
|
#define STM32_PCLK1 (STM32_HCLK / 8)
|
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|
|
#elif STM32_PPRE1 == STM32_PPRE1_DIV16
|
|
|
|
|
#define STM32_PCLK1 (STM32_HCLK / 16)
|
|
|
|
|
#else
|
|
|
|
|
#error "invalid STM32_PPRE1 value specified"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* APB1 frequency check.*/
|
2011-07-19 18:48:10 +00:00
|
|
|
#if STM32_PCLK1 > 24000000
|
2010-11-14 16:47:38 +00:00
|
|
|
#error "STM32_PCLK1 exceeding maximum frequency (24MHz)"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief APB2 frequency.
|
|
|
|
|
*/
|
|
|
|
|
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_PCLK2 (STM32_HCLK / 1)
|
|
|
|
|
#elif STM32_PPRE2 == STM32_PPRE2_DIV2
|
|
|
|
|
#define STM32_PCLK2 (STM32_HCLK / 2)
|
|
|
|
|
#elif STM32_PPRE2 == STM32_PPRE2_DIV4
|
|
|
|
|
#define STM32_PCLK2 (STM32_HCLK / 4)
|
|
|
|
|
#elif STM32_PPRE2 == STM32_PPRE2_DIV8
|
|
|
|
|
#define STM32_PCLK2 (STM32_HCLK / 8)
|
|
|
|
|
#elif STM32_PPRE2 == STM32_PPRE2_DIV16
|
|
|
|
|
#define STM32_PCLK2 (STM32_HCLK / 16)
|
|
|
|
|
#else
|
|
|
|
|
#error "invalid STM32_PPRE2 value specified"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* APB2 frequency check.*/
|
|
|
|
|
#if STM32_PCLK2 > 24000000
|
|
|
|
|
#error "STM32_PCLK2 exceeding maximum frequency (24MHz)"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief ADC frequency.
|
|
|
|
|
*/
|
|
|
|
|
#if (STM32_ADCPRE == STM32_ADCPRE_DIV2) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_ADCCLK (STM32_PCLK2 / 2)
|
|
|
|
|
#elif STM32_ADCPRE == STM32_ADCPRE_DIV4
|
|
|
|
|
#define STM32_ADCCLK (STM32_PCLK2 / 4)
|
|
|
|
|
#elif STM32_ADCPRE == STM32_ADCPRE_DIV6
|
|
|
|
|
#define STM32_ADCCLK (STM32_PCLK2 / 6)
|
|
|
|
|
#elif STM32_ADCPRE == STM32_ADCPRE_DIV8
|
|
|
|
|
#define STM32_ADCCLK (STM32_PCLK2 / 8)
|
|
|
|
|
#else
|
|
|
|
|
#error "invalid STM32_ADCPRE value specified"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* ADC frequency check.*/
|
|
|
|
|
#if STM32_ADCCLK > 12000000
|
|
|
|
|
#error "STM32_ADCCLK exceeding maximum frequency (12MHz)"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Timers 2, 3, 4, 5, 6, 7, 12, 13, 14 clock.
|
|
|
|
|
*/
|
|
|
|
|
#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
|
|
|
|
|
#else
|
|
|
|
|
#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Timers 1, 8, 9, 10, 11 clock.
|
|
|
|
|
*/
|
|
|
|
|
#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
|
|
|
|
|
#else
|
|
|
|
|
#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Flash settings.
|
|
|
|
|
*/
|
|
|
|
|
#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
|
|
|
|
|
#define STM32_FLASHBITS 0x00000010
|
|
|
|
|
#elif STM32_HCLK <= 48000000
|
|
|
|
|
#define STM32_FLASHBITS 0x00000011
|
|
|
|
|
#else
|
|
|
|
|
#define STM32_FLASHBITS 0x00000012
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#endif /* _HAL_LLD_F100_H_ */
|
|
|
|
|
|
|
|
|
|
/** @} */
|
