160 lines
9.8 KiB
C
160 lines
9.8 KiB
C
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* SPC560B/Cxx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 1...15 Lowest...Highest.
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*/
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#define SPC560BCxx_MCUCONF
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/*
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* HAL driver system settings.
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*/
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#define SPC5_NO_INIT FALSE
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#define SPC5_ALLOW_OVERCLOCK FALSE
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#define SPC5_FMPLL0_IDF_VALUE 5
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#define SPC5_FMPLL0_NDIV_VALUE 32
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#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
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#define SPC5_FMPLL1_IDF_VALUE 5
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#define SPC5_FMPLL1_NDIV_VALUE 60
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#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
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#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \
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SPC5_ME_ME_RUN2 | \
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SPC5_ME_ME_RUN3 | \
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SPC5_ME_ME_HALT0 | \
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SPC5_ME_ME_STOP0)
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#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO)
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#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
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SPC5_ME_RUN_PC_RUN1 | \
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SPC5_ME_RUN_PC_RUN2 | \
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SPC5_ME_RUN_PC_RUN3)
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#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \
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SPC5_ME_RUN_PC_RUN1 | \
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SPC5_ME_RUN_PC_RUN2 | \
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SPC5_ME_RUN_PC_RUN3)
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#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \
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SPC5_ME_RUN_PC_RUN1 | \
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SPC5_ME_RUN_PC_RUN2 | \
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SPC5_ME_RUN_PC_RUN3)
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#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \
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SPC5_ME_RUN_PC_RUN1 | \
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SPC5_ME_RUN_PC_RUN2 | \
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SPC5_ME_RUN_PC_RUN3)
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#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \
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SPC5_ME_RUN_PC_RUN1 | \
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SPC5_ME_RUN_PC_RUN2 | \
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SPC5_ME_RUN_PC_RUN3)
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#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
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SPC5_ME_LP_PC_STOP0)
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#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
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SPC5_ME_LP_PC_STOP0)
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#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \
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SPC5_ME_LP_PC_STOP0)
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#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
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SPC5_ME_LP_PC_STOP0)
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#define SPC5_PIT3_IRQ_PRIORITY 4
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/*
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* SERIAL driver system settings.
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*/
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#define SPC5_SERIAL_USE_LINFLEX0 TRUE
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#define SPC5_SERIAL_USE_LINFLEX1 TRUE
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#define SPC5_SERIAL_LINFLEX0_PRIORITY 8
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#define SPC5_SERIAL_LINFLEX1_PRIORITY 8
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#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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