2014-02-26 13:44:13 +00:00
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/*
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2015-01-11 13:45:54 +00:00
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ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio.
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2014-02-26 13:44:13 +00:00
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2014-07-26 09:00:40 +00:00
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This file is part of ChibiOS.
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2014-02-26 13:44:13 +00:00
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2014-07-26 09:00:40 +00:00
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ChibiOS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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2014-02-26 13:44:13 +00:00
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2014-07-26 09:00:40 +00:00
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ChibiOS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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2014-02-26 13:44:13 +00:00
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*/
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/**
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* @file SPC564Axx/boot.s
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* @brief SPC564Axx boot-related code.
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*
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* @addtogroup PPC_BOOT
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* @{
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*/
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#include "boot.h"
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#if !defined(__DOXYGEN__)
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/* BAM record.*/
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.section .boot, "ax"
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#if BOOT_USE_VLE
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.long 0x015A0000
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#else
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.long 0x005A0000
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#endif
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.long _reset_address
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.align 2
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.globl _reset_address
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.type _reset_address, @function
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_reset_address:
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#if BOOT_PERFORM_CORE_INIT
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bl _coreinit
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#endif
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bl _ivinit
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#if BOOT_RELOCATE_IN_RAM
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/*
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* Image relocation in RAM.
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*/
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lis %r4, __ram_reloc_start__@h
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ori %r4, %r4, __ram_reloc_start__@l
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lis %r5, __ram_reloc_dest__@h
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ori %r5, %r5, __ram_reloc_dest__@l
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lis %r6, __ram_reloc_end__@h
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ori %r6, %r6, __ram_reloc_end__@l
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.relloop:
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cmpl cr0, %r4, %r6
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bge cr0, .relend
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lwz %r7, 0(%r4)
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addi %r4, %r4, 4
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stw %r7, 0(%r5)
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addi %r5, %r5, 4
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b .relloop
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.relend:
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lis %r3, _boot_address@h
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ori %r3, %r3, _boot_address@l
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mtctr %r3
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bctrl
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#else
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b _boot_address
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#endif
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#if BOOT_PERFORM_CORE_INIT
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.align 2
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_ramcode:
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tlbwe
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isync
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blr
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.align 2
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_coreinit:
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/*
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* Invalidating all TLBs except TLB1.
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*/
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lis %r3, 0
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mtspr 625, %r3 /* MAS1 */
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mtspr 626, %r3 /* MAS2 */
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mtspr 627, %r3 /* MAS3 */
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(0))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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lis %r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
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mtspr 624, %r3 /* MAS0 */
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tlbwe
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/*
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* TLB0 allocated to internal RAM.
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*/
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lis %r3, TLB0_MAS0@h
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mtspr 624, %r3 /* MAS0 */
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lis %r3, TLB0_MAS1@h
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ori %r3, %r3, TLB0_MAS1@l
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mtspr 625, %r3 /* MAS1 */
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lis %r3, TLB0_MAS2@h
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ori %r3, %r3, TLB0_MAS2@l
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mtspr 626, %r3 /* MAS2 */
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lis %r3, TLB0_MAS3@h
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ori %r3, %r3, TLB0_MAS3@l
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mtspr 627, %r3 /* MAS3 */
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tlbwe
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/*
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* TLB2 allocated to internal Peripherals Bridge A.
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*/
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lis %r3, TLB2_MAS0@h
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mtspr 624, %r3 /* MAS0 */
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lis %r3, TLB2_MAS1@h
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ori %r3, %r3, TLB2_MAS1@l
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mtspr 625, %r3 /* MAS1 */
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lis %r3, TLB2_MAS2@h
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ori %r3, %r3, TLB2_MAS2@l
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mtspr 626, %r3 /* MAS2 */
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lis %r3, TLB2_MAS3@h
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ori %r3, %r3, TLB2_MAS3@l
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mtspr 627, %r3 /* MAS3 */
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tlbwe
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/*
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* TLB3 allocated to internal Peripherals Bridge B.
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*/
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lis %r3, TLB3_MAS0@h
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mtspr 624, %r3 /* MAS0 */
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lis %r3, TLB3_MAS1@h
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ori %r3, %r3, TLB3_MAS1@l
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mtspr 625, %r3 /* MAS1 */
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lis %r3, TLB3_MAS2@h
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ori %r3, %r3, TLB3_MAS2@l
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mtspr 626, %r3 /* MAS2 */
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lis %r3, TLB3_MAS3@h
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ori %r3, %r3, TLB3_MAS3@l
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mtspr 627, %r3 /* MAS3 */
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tlbwe
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/*
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* TLB4 allocated to on-platform peripherals.
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*/
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lis %r3, TLB4_MAS0@h
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mtspr 624, %r3 /* MAS0 */
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lis %r3, TLB4_MAS1@h
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ori %r3, %r3, TLB4_MAS1@l
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mtspr 625, %r3 /* MAS1 */
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lis %r3, TLB4_MAS2@h
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ori %r3, %r3, TLB4_MAS2@l
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mtspr 626, %r3 /* MAS2 */
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lis %r3, TLB4_MAS3@h
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ori %r3, %r3, TLB4_MAS3@l
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mtspr 627, %r3 /* MAS3 */
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tlbwe
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/*
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* RAM clearing, this device requires a write to all RAM location in
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* order to initialize the ECC detection hardware, this is going to
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* slow down the startup but there is no way around.
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*/
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xor %r0, %r0, %r0
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xor %r1, %r1, %r1
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xor %r2, %r2, %r2
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xor %r3, %r3, %r3
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xor %r4, %r4, %r4
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xor %r5, %r5, %r5
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xor %r6, %r6, %r6
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xor %r7, %r7, %r7
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xor %r8, %r8, %r8
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xor %r9, %r9, %r9
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xor %r10, %r10, %r10
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xor %r11, %r11, %r11
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xor %r12, %r12, %r12
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xor %r13, %r13, %r13
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xor %r14, %r14, %r14
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xor %r15, %r15, %r15
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xor %r16, %r16, %r16
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xor %r17, %r17, %r17
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xor %r18, %r18, %r18
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xor %r19, %r19, %r19
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xor %r20, %r20, %r20
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xor %r21, %r21, %r21
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xor %r22, %r22, %r22
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xor %r23, %r23, %r23
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xor %r24, %r24, %r24
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xor %r25, %r25, %r25
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xor %r26, %r26, %r26
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xor %r27, %r27, %r27
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xor %r28, %r28, %r28
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xor %r29, %r29, %r29
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xor %r30, %r30, %r30
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xor %r31, %r31, %r31
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lis %r4, __ram_start__@h
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ori %r4, %r4, __ram_start__@l
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lis %r5, __ram_end__@h
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ori %r5, %r5, __ram_end__@l
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.cleareccloop:
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cmpl %cr0, %r4, %r5
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bge %cr0, .cleareccend
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stmw %r16, 0(%r4)
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addi %r4, %r4, 64
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b .cleareccloop
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.cleareccend:
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/*
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* *Finally* the TLB1 is re-allocated to flash, note, the final phase
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* is executed from RAM.
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*/
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lis %r3, TLB1_MAS0@h
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mtspr 624, %r3 /* MAS0 */
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lis %r3, TLB1_MAS1@h
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ori %r3, %r3, TLB1_MAS1@l
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mtspr 625, %r3 /* MAS1 */
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lis %r3, TLB1_MAS2@h
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ori %r3, %r3, TLB1_MAS2@l
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mtspr 626, %r3 /* MAS2 */
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lis %r3, TLB1_MAS3@h
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ori %r3, %r3, TLB1_MAS3@l
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mtspr 627, %r3 /* MAS3 */
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mflr %r4
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lis %r6, _ramcode@h
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ori %r6, %r6, _ramcode@l
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lis %r7, 0x40010000@h
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mtctr %r7
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lwz %r3, 0(%r6)
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stw %r3, 0(%r7)
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lwz %r3, 4(%r6)
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stw %r3, 4(%r7)
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lwz %r3, 8(%r6)
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stw %r3, 8(%r7)
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bctrl
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mtlr %r4
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/*
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* Branch prediction enabled.
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*/
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li %r3, BOOT_BUCSR_DEFAULT
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mtspr 1013, %r3 /* BUCSR */
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/*
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* Cache invalidated and then enabled.
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*/
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li %r3, LICSR1_ICINV
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mtspr 1011, %r3 /* LICSR1 */
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.inv: mfspr %r3, 1011 /* LICSR1 */
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andi. %r3, %r3, LICSR1_ICINV
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bne .inv
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lis %r3, BOOT_LICSR1_DEFAULT@h
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ori %r3, %r3, BOOT_LICSR1_DEFAULT@l
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mtspr 1011, %r3 /* LICSR1 */
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blr
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#endif /* BOOT_PERFORM_CORE_INIT */
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/*
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* Exception vectors initialization.
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*/
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.align 2
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_ivinit:
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/* MSR initialization.*/
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lis %r3, BOOT_MSR_DEFAULT@h
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ori %r3, %r3, BOOT_MSR_DEFAULT@l
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mtMSR %r3
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/* IVPR initialization.*/
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lis %r3, __ivpr_base__@h
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ori %r3, %r3, __ivpr_base__@l
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mtIVPR %r3
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/* IVORs initialization.*/
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lis %r3, _unhandled_exception@h
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ori %r3, %r3, _unhandled_exception@l
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mtspr 400, %r3 /* IVOR0-15 */
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mtspr 401, %r3
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mtspr 402, %r3
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mtspr 403, %r3
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mtspr 404, %r3
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mtspr 405, %r3
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mtspr 406, %r3
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mtspr 407, %r3
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mtspr 408, %r3
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mtspr 409, %r3
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mtspr 410, %r3
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mtspr 411, %r3
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mtspr 412, %r3
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mtspr 413, %r3
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mtspr 414, %r3
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mtspr 415, %r3
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mtspr 528, %r3 /* IVOR32-34 */
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mtspr 529, %r3
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mtspr 530, %r3
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blr
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.section .handlers, "ax"
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/*
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* Unhandled exceptions handler.
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*/
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.weak _unhandled_exception
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.type _unhandled_exception, @function
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_unhandled_exception:
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b _unhandled_exception
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#endif /* !defined(__DOXYGEN__) */
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/** @} */
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