492 lines
13 KiB
C
492 lines
13 KiB
C
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/*
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ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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This driver is based on the work done by Matteo Serva available at
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http://github.com/matteoserva/ChibiOS-AVR
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*/
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/**
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* @file AVR/pwm_lld.c
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* @brief AVR PWM driver subsystem low level driver.
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*
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* @addtogroup PWM
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* @{
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*/
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#include "hal.h"
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#if HAL_USE_PWM || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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typedef struct {
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volatile uint8_t *tccra;
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volatile uint8_t *tccrb;
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volatile uint8_t *ocrah;
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volatile uint8_t *ocral;
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volatile uint8_t *ocrbh;
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volatile uint8_t *ocrbl;
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volatile uint8_t *ocrch;
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volatile uint8_t *ocrcl;
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volatile uint8_t *tifr;
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volatile uint8_t *timsk;
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} timer_registers_t;
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static timer_registers_t regs_table[]=
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{
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#if AVR_PWM_USE_TIM1 || defined(__DOXYGEN__)
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#if defined(OCR1C)
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{&TCCR1A, &TCCR1B, &OCR1AH, &OCR1AL, &OCR1BH, &OCR1BL, &OCR1CH, &OCR1CL, &TIFR1, &TIMSK1},
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#else
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{&TCCR1A, &TCCR1B, &OCR1AH, &OCR1AL, &OCR1BH, &OCR1BL, NULL, NULL, &TIFR1, &TIMSK1},
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#endif
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#endif
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#if AVR_PWM_USE_TIM2 || defined(__DOXYGEN__)
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{&TCCR2A, &TCCR2B, &OCR2A, &OCR2A, &OCR2B, &OCR2B, NULL, NULL, &TIFR2, &TIMSK2},
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#endif
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#if AVR_PWM_USE_TIM3 || defined(__DOXYGEN__)
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{&TCCR3A, &TCCR3B, &OCR3AH, &OCR3AL, &OCR3BH, &OCR3BL, &OCR3CH, &OCR3CL, &TIFR3, &TIMSK3},
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#endif
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#if AVR_PWM_USE_TIM4 || defined(__DOXYGEN__)
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{&TCCR4A, &TCCR4B, &OCR4AH, &OCR4AL, &OCR4CH, &OCR4CL, &OCR4CH, &OCR4CL, &TIFR4, &TIMSK4},
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#endif
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#if AVR_PWM_USE_TIM5 || defined(__DOXYGEN__)
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{&TCCR5A, &TCCR5B, &OCR5AH, &OCR5AL, &OCR5BH, &OCR5BL, &OCR5CH, &OCR5CL, &TIFR5, &TIMSK5},
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#endif
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};
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief PWM driver identifiers.*/
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#if AVR_PWM_USE_TIM1 || defined(__DOXYGEN__)
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PWMDriver PWMD1;
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#endif
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#if AVR_PWM_USE_TIM2 || defined(__DOXYGEN__)
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PWMDriver PWMD2;
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#endif
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#if AVR_PWM_USE_TIM3 || defined(__DOXYGEN__)
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PWMDriver PWMD3;
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#endif
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#if AVR_PWM_USE_TIM4 || defined(__DOXYGEN__)
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PWMDriver PWMD4;
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#endif
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#if AVR_PWM_USE_TIM5 || defined(__DOXYGEN__)
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PWMDriver PWMD5;
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#endif
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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static void config_channel(volatile uint8_t *tccra,
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uint8_t com1,
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uint8_t com0,
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pwmmode_t mode)
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{
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*tccra &= ~((1 << com1) | (1 << com0));
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if (mode == PWM_OUTPUT_ACTIVE_HIGH)
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*tccra |= ((1 << com1) | (0 << com0)); /* non inverting mode */
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else if (mode == PWM_OUTPUT_ACTIVE_LOW)
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*tccra |= (1 << com1) | (1 << com0); /* inverting mode */
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}
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static uint8_t timer_index(PWMDriver *pwmp)
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{
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uint8_t index = 0;
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#if AVR_PWM_USE_TIM1 || defined(__DOXYGEN__)
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if (pwmp == &PWMD1) return index;
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else index++;
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#endif
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#if AVR_PWM_USE_TIM2 || defined(__DOXYGEN__)
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if (pwmp == &PWMD2) return index;
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else index++;
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#endif
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#if AVR_PWM_USE_TIM3 || defined(__DOXYGEN__)
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if (pwmp == &PWMD3) return index;
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else index++;
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#endif
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#if AVR_PWM_USE_TIM4 || defined(__DOXYGEN__)
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if (pwmp == &PWMD4) return index;
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else index++;
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#endif
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#if AVR_PWM_USE_TIM5 || defined(__DOXYGEN__)
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if (pwmp == &PWMD5) return index;
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else index++;
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#endif
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*
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* interrupt for compare1&2 and clock overflow. pwmd1 & pwmd2
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*/
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#if AVR_PWM_USE_TIM1 || defined(__DOXYGEN__)
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OSAL_IRQ_HANDLER(TIMER1_OVF_vect)
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{
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OSAL_IRQ_PROLOGUE();
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PWMD1.config->callback(&PWMD1);
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OSAL_IRQ_EPILOGUE();
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}
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OSAL_IRQ_HANDLER(TIMER1_COMPA_vect)
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{
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OSAL_IRQ_PROLOGUE();
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PWMD1.config->channels[0].callback(&PWMD1);
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OSAL_IRQ_EPILOGUE();
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}
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OSAL_IRQ_HANDLER(TIMER1_COMPB_vect)
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{
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OSAL_IRQ_PROLOGUE();
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PWMD1.config->channels[1].callback(&PWMD1);
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OSAL_IRQ_EPILOGUE();
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}
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#if PWM_CHANNELS > 2
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OSAL_IRQ_HANDLER(TIMER1_COMPC_vect)
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{
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OSAL_IRQ_PROLOGUE();
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PWMD1.config->channels[2].callback(&PWMD1);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#endif
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#if AVR_PWM_USE_TIM2 || defined(__DOXYGEN__)
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OSAL_IRQ_HANDLER(TIMER2_OVF_vect)
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{
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OSAL_IRQ_PROLOGUE();
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PWMD2.config->callback(&PWMD2);
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OSAL_IRQ_EPILOGUE();
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}
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OSAL_IRQ_HANDLER(TIMER2_COMPA_vect)
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{
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OSAL_IRQ_PROLOGUE();
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PWMD2.config->channels[0].callback(&PWMD2);
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OSAL_IRQ_EPILOGUE();
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}
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OSAL_IRQ_HANDLER(TIMER2_COMPB_vect)
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{
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OSAL_IRQ_PROLOGUE();
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PWMD2.config->channels[1].callback(&PWMD2);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if AVR_PWM_USE_TIM3 || defined(__DOXYGEN__)
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OSAL_IRQ_HANDLER(TIMER3_OVF_vect)
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{
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OSAL_IRQ_PROLOGUE();
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PWMD3.config->callback(&PWMD3);
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OSAL_IRQ_EPILOGUE();
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}
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OSAL_IRQ_HANDLER(TIMER3_COMPA_vect)
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{
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OSAL_IRQ_PROLOGUE();
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PWMD3.config->channels[0].callback(&PWMD3);
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OSAL_IRQ_EPILOGUE();
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}
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OSAL_IRQ_HANDLER(TIMER3_COMPB_vect)
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{
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OSAL_IRQ_PROLOGUE();
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PWMD3.config->channels[1].callback(&PWMD3);
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OSAL_IRQ_EPILOGUE();
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}
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OSAL_IRQ_HANDLER(TIMER3_COMPC_vect)
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{
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OSAL_IRQ_PROLOGUE();
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PWMD3.config->channels[2].callback(&PWMD3);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if AVR_PWM_USE_TIM4 || defined(__DOXYGEN__)
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OSAL_IRQ_HANDLER(TIMER4_OVF_vect)
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{
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OSAL_IRQ_PROLOGUE();
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PWMD4.config->callback(&PWMD4);
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OSAL_IRQ_EPILOGUE();
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}
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OSAL_IRQ_HANDLER(TIMER4_COMPA_vect)
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{
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OSAL_IRQ_PROLOGUE();
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PWMD4.config->channels[0].callback(&PWMD4);
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OSAL_IRQ_EPILOGUE();
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}
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OSAL_IRQ_HANDLER(TIMER4_COMPB_vect)
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{
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OSAL_IRQ_PROLOGUE();
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PWMD4.config->channels[1].callback(&PWMD4);
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OSAL_IRQ_EPILOGUE();
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}
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OSAL_IRQ_HANDLER(TIMER4_COMPC_vect)
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{
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OSAL_IRQ_PROLOGUE();
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PWMD4.config->channels[2].callback(&PWMD4);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if AVR_PWM_USE_TIM5 || defined(__DOXYGEN__)
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OSAL_IRQ_HANDLER(TIMER5_OVF_vect)
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{
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OSAL_IRQ_PROLOGUE();
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PWMD5.config->callback(&PWMD5);
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OSAL_IRQ_EPILOGUE();
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}
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OSAL_IRQ_HANDLER(TIMER5_COMPA_vect)
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{
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OSAL_IRQ_PROLOGUE();
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PWMD5.config->channels[0].callback(&PWMD5);
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OSAL_IRQ_EPILOGUE();
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}
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OSAL_IRQ_HANDLER(TIMER5_COMPB_vect)
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{
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OSAL_IRQ_PROLOGUE();
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PWMD5.config->channels[1].callback(&PWMD5);
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OSAL_IRQ_EPILOGUE();
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}
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OSAL_IRQ_HANDLER(TIMER5_COMPC_vect)
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{
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OSAL_IRQ_PROLOGUE();
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PWMD5.config->channels[2].callback(&PWMD5);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level PWM driver initialization.
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*
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* @notapi
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*/
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void pwm_lld_init(void)
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{
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#if AVR_PWM_USE_TIM1 || defined(__DOXYGEN__)
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pwmObjectInit(&PWMD1);
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TCCR1A = (1 << WGM11) | (1 << WGM10);
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TCCR1B = (0 << WGM13) | (1 << WGM12);
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#endif
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#if AVR_PWM_USE_TIM2 || defined(__DOXYGEN__)
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pwmObjectInit(&PWMD2);
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TCCR2A = (1 << WGM21) | (1 << WGM20);
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TCCR2B = (0 << WGM22);
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#endif
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#if AVR_PWM_USE_TIM3 || defined(__DOXYGEN__)
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pwmObjectInit(&PWMD3);
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TCCR3A = (1 << WGM31) | (1 << WGM30);
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TCCR3B = (0 << WGM33) | (1 << WGM32);
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#endif
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#if AVR_PWM_USE_TIM4 || defined(__DOXYGEN__)
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pwmObjectInit(&PWMD4);
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TCCR4A = (1 << WGM41) | (1 << WGM40);
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TCCR4B = (0 << WGM43) | (1 << WGM42);
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#endif
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#if AVR_PWM_USE_TIM5 || defined(__DOXYGEN__)
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pwmObjectInit(&PWMD5);
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TCCR5A = (1 << WGM51) | (1 << WGM50);
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TCCR5B = (0 << WGM53) | (1 << WGM52);
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#endif
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}
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/**
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* @brief Configures and activates the PWM peripheral.
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*
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* @param[in] pwmp pointer to the @p PWMDriver object
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*
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* @notapi
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*/
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void pwm_lld_start(PWMDriver *pwmp)
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{
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if (pwmp->state == PWM_STOP) {
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#if AVR_PWM_USE_TIM2 || defined(__DOXYGEN__)
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if (pwmp == &PWMD2) {
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TCCR2B &= ~((1 << CS22) | (1 << CS21));
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TCCR2B |= (1 << CS20);
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if (pwmp->config->callback != NULL)
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TIMSK2 |= (1 << TOIE2);
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return;
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}
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#endif
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/* TODO: support other prescaler options */
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uint8_t i = timer_index(pwmp);
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*regs_table[i].tccrb &= ~(1 << CS11);
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*regs_table[i].tccrb |= (1 << CS12) | (1 << CS10);
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*regs_table[i].timsk = (1 << TOIE1);
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}
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}
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/**
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* @brief Deactivates the PWM peripheral.
|
||
|
|
*
|
||
|
|
* @param[in] pwmp pointer to the @p PWMDriver object
|
||
|
|
*
|
||
|
|
* @notapi
|
||
|
|
*/
|
||
|
|
void pwm_lld_stop(PWMDriver *pwmp)
|
||
|
|
{
|
||
|
|
uint8_t i = timer_index(pwmp);
|
||
|
|
*regs_table[i].tccrb &= ~((1 << CS12) | (1 << CS11) | (1 << CS10));
|
||
|
|
*regs_table[i].timsk = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Changes the period the PWM peripheral.
|
||
|
|
* @details This function changes the period of a PWM unit that has already
|
||
|
|
* been activated using @p pwmStart().
|
||
|
|
* @pre The PWM unit must have been activated using @p pwmStart().
|
||
|
|
* @post The PWM unit period is changed to the new value.
|
||
|
|
* @note The function has effect at the next cycle start.
|
||
|
|
* @note If a period is specified that is shorter than the pulse width
|
||
|
|
* programmed in one of the channels then the behavior is not
|
||
|
|
* guaranteed.
|
||
|
|
*
|
||
|
|
* @param[in] pwmp pointer to a @p PWMDriver object
|
||
|
|
* @param[in] period new cycle time in ticks
|
||
|
|
*
|
||
|
|
* @notapi
|
||
|
|
*/
|
||
|
|
void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Enables a PWM channel.
|
||
|
|
* @pre The PWM unit must have been activated using @p pwmStart().
|
||
|
|
* @post The channel is active using the specified configuration.
|
||
|
|
* @note Depending on the hardware implementation this function has
|
||
|
|
* effect starting on the next cycle (recommended implementation)
|
||
|
|
* or immediately (fallback implementation).
|
||
|
|
*
|
||
|
|
* @param[in] pwmp pointer to a @p PWMDriver object
|
||
|
|
* @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
|
||
|
|
* @param[in] width PWM pulse width as clock pulses number
|
||
|
|
*
|
||
|
|
* @notapi
|
||
|
|
*/
|
||
|
|
void pwm_lld_enable_channel(PWMDriver *pwmp,
|
||
|
|
pwmchannel_t channel,
|
||
|
|
pwmcnt_t width)
|
||
|
|
{
|
||
|
|
uint16_t val = width;
|
||
|
|
if (val > MAX_PWM_VALUE)
|
||
|
|
val = MAX_PWM_VALUE;
|
||
|
|
|
||
|
|
#if AVR_PWM_USE_TIM2 || defined(__DOXYGEN__)
|
||
|
|
if (pwmp == &PWMD2) {
|
||
|
|
config_channel(&TCCR2A,
|
||
|
|
7 - 2*channel,
|
||
|
|
6 - 2*channel,
|
||
|
|
pwmp->config->channels[channel].mode);
|
||
|
|
TIMSK2 |= (1 << (channel + 1));
|
||
|
|
/* Timer 2 is 8 bit */
|
||
|
|
if (val > 0xFF)
|
||
|
|
val = 0xFF;
|
||
|
|
if (pwmp->config->channels[channel].callback) {
|
||
|
|
switch (channel) {
|
||
|
|
case 0: OCR2A = val; break;
|
||
|
|
case 1: OCR2B = val; break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
uint8_t i = timer_index(pwmp);
|
||
|
|
config_channel(regs_table[i].tccra,
|
||
|
|
7 - 2*channel,
|
||
|
|
6 - 2*channel,
|
||
|
|
pwmp->config->channels[channel].mode);
|
||
|
|
volatile uint8_t *ocrh, *ocrl;
|
||
|
|
switch (channel) {
|
||
|
|
case 1:
|
||
|
|
ocrh = regs_table[i].ocrbh;
|
||
|
|
ocrl = regs_table[i].ocrbl;
|
||
|
|
break;
|
||
|
|
case 2:
|
||
|
|
ocrh = regs_table[i].ocrch;
|
||
|
|
ocrl = regs_table[i].ocrcl;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
ocrh = regs_table[i].ocrah;
|
||
|
|
ocrl = regs_table[i].ocral;
|
||
|
|
}
|
||
|
|
*ocrh = val >> 8;
|
||
|
|
*ocrl = val & 0xFF;
|
||
|
|
*regs_table[i].tifr |= (1 << (channel + 1));
|
||
|
|
if (pwmp->config->channels[channel].callback)
|
||
|
|
*regs_table[i].timsk |= (1 << (channel + 1));
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Disables a PWM channel.
|
||
|
|
* @pre The PWM unit must have been activated using @p pwmStart().
|
||
|
|
* @post The channel is disabled and its output line returned to the
|
||
|
|
* idle state.
|
||
|
|
* @note Depending on the hardware implementation this function has
|
||
|
|
* effect starting on the next cycle (recommended implementation)
|
||
|
|
* or immediately (fallback implementation).
|
||
|
|
*
|
||
|
|
* @param[in] pwmp pointer to a @p PWMDriver object
|
||
|
|
* @param[in] channel PWM channel identifier (0...PWM_CHANNELS-1)
|
||
|
|
*
|
||
|
|
* @notapi
|
||
|
|
*/
|
||
|
|
void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel)
|
||
|
|
{
|
||
|
|
uint8_t i = timer_index(pwmp);
|
||
|
|
config_channel(regs_table[i].tccra,
|
||
|
|
7 - 2*channel,
|
||
|
|
6 - 2*channel,
|
||
|
|
PWM_OUTPUT_DISABLED);
|
||
|
|
*regs_table[i].timsk &= ~(1 << (channel + 1));
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* HAL_USE_PWM */
|
||
|
|
|
||
|
|
/** @} */
|