494 lines
18 KiB
C
494 lines
18 KiB
C
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/**************************************************************************//**
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* @file LPC13xx.h
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* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
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* NXP LPC13xx Device Series
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* @version V1.01
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* @date 19. October 2009
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*
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* @note
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* Copyright (C) 2009 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#ifndef __LPC13xx_H__
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#define __LPC13xx_H__
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/*
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* ==========================================================================
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* ---------- Interrupt Number Definition -----------------------------------
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* ==========================================================================
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*/
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typedef enum IRQn
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{
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/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
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/****** LPC13xx Specific Interrupt Numbers *******************************************************/
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WAKEUP0_IRQn = 0, /*!< All I/O pins can be used as wakeup source. */
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WAKEUP1_IRQn = 1, /*!< There are 40 pins in total for LPC17xx */
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WAKEUP2_IRQn = 2,
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WAKEUP3_IRQn = 3,
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WAKEUP4_IRQn = 4,
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WAKEUP5_IRQn = 5,
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WAKEUP6_IRQn = 6,
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WAKEUP7_IRQn = 7,
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WAKEUP8_IRQn = 8,
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WAKEUP9_IRQn = 9,
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WAKEUP10_IRQn = 10,
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WAKEUP11_IRQn = 11,
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WAKEUP12_IRQn = 12,
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WAKEUP13_IRQn = 13,
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WAKEUP14_IRQn = 14,
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WAKEUP15_IRQn = 15,
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WAKEUP16_IRQn = 16,
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WAKEUP17_IRQn = 17,
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WAKEUP18_IRQn = 18,
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WAKEUP19_IRQn = 19,
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WAKEUP20_IRQn = 20,
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WAKEUP21_IRQn = 21,
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WAKEUP22_IRQn = 22,
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WAKEUP23_IRQn = 23,
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WAKEUP24_IRQn = 24,
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WAKEUP25_IRQn = 25,
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WAKEUP26_IRQn = 26,
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WAKEUP27_IRQn = 27,
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WAKEUP28_IRQn = 28,
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WAKEUP29_IRQn = 29,
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WAKEUP30_IRQn = 30,
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WAKEUP31_IRQn = 31,
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WAKEUP32_IRQn = 32,
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WAKEUP33_IRQn = 33,
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WAKEUP34_IRQn = 34,
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WAKEUP35_IRQn = 35,
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WAKEUP36_IRQn = 36,
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WAKEUP37_IRQn = 37,
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WAKEUP38_IRQn = 38,
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WAKEUP39_IRQn = 39,
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I2C_IRQn = 40, /*!< I2C Interrupt */
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TIMER_16_0_IRQn = 41, /*!< 16-bit Timer0 Interrupt */
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TIMER_16_1_IRQn = 42, /*!< 16-bit Timer1 Interrupt */
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TIMER_32_0_IRQn = 43, /*!< 32-bit Timer0 Interrupt */
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TIMER_32_1_IRQn = 44, /*!< 32-bit Timer1 Interrupt */
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SSP_IRQn = 45, /*!< SSP Interrupt */
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UART_IRQn = 46, /*!< UART Interrupt */
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USB_IRQn = 47, /*!< USB Regular Interrupt */
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USB_FIQn = 48, /*!< USB Fast Interrupt */
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ADC_IRQn = 49, /*!< A/D Converter Interrupt */
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WDT_IRQn = 50, /*!< Watchdog timer Interrupt */
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BOD_IRQn = 51, /*!< Brown Out Detect(BOD) Interrupt */
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EINT3_IRQn = 53, /*!< External Interrupt 3 Interrupt */
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EINT2_IRQn = 54, /*!< External Interrupt 2 Interrupt */
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EINT1_IRQn = 55, /*!< External Interrupt 1 Interrupt */
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EINT0_IRQn = 56, /*!< External Interrupt 0 Interrupt */
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} IRQn_Type;
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/*
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* ==========================================================================
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* ----------- Processor and Core Peripheral Section ------------------------
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* ==========================================================================
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*/
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/* Configuration of the Cortex-M3 Processor and Core Peripherals */
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#define __MPU_PRESENT 1 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
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#include "system_LPC13xx.h" /* System Header */
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/******************************************************************************/
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/* Device Specific Peripheral registers structures */
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/******************************************************************************/
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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/*------------- System Control (SYSCON) --------------------------------------*/
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typedef struct
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{
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__IO uint32_t SYSMEMREMAP; /* Sys mem. Remap, Offset 0x0 */
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__IO uint32_t PRESETCTRL;
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__IO uint32_t SYSPLLCTRL; /* Sys PLL control */
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__IO uint32_t SYSPLLSTAT;
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__IO uint32_t USBPLLCTRL; /* USB PLL control, offset 0x10 */
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__IO uint32_t USBPLLSTAT;
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uint32_t RESERVED0[2];
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__IO uint32_t SYSOSCCTRL; /* Offset 0x20 */
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__IO uint32_t WDTOSCCTRL;
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__IO uint32_t IRCCTRL;
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uint32_t RESERVED1[1];
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__IO uint32_t SYSRESSTAT; /* Offset 0x30 */
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uint32_t RESERVED2[3];
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__IO uint32_t SYSPLLCLKSEL; /* Offset 0x40 */
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__IO uint32_t SYSPLLCLKUEN;
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__IO uint32_t USBPLLCLKSEL;
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__IO uint32_t USBPLLCLKUEN;
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uint32_t RESERVED3[8];
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__IO uint32_t MAINCLKSEL; /* Offset 0x70 */
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__IO uint32_t MAINCLKUEN;
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__IO uint32_t SYSAHBCLKDIV;
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uint32_t RESERVED4[1];
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__IO uint32_t SYSAHBCLKCTRL; /* Offset 0x80 */
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uint32_t RESERVED5[4];
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__IO uint32_t SSPCLKDIV;
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__IO uint32_t UARTCLKDIV;
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uint32_t RESERVED6[4];
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__IO uint32_t TRACECLKDIV;
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__IO uint32_t SYSTICKCLKDIV; /* Offset 0xB0 */
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uint32_t RESERVED7[3];
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__IO uint32_t USBCLKSEL; /* Offset 0xC0 */
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__IO uint32_t USBCLKUEN;
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__IO uint32_t USBCLKDIV;
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uint32_t RESERVED8[1];
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__IO uint32_t WDTCLKSEL; /* Offset 0xD0 */
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__IO uint32_t WDTCLKUEN;
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__IO uint32_t WDTCLKDIV;
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uint32_t RESERVED9[1];
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__IO uint32_t CLKOUTCLKSEL; /* Offset 0xE0 */
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__IO uint32_t CLKOUTUEN;
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__IO uint32_t CLKOUTDIV;
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uint32_t RESERVED10[5];
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__IO uint32_t PIOPORCAP0; /* Offset 0x100 */
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__IO uint32_t PIOPORCAP1;
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uint32_t RESERVED11[18];
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__IO uint32_t BODCTRL; /* Offset 0x150 */
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uint32_t RESERVED12[1];
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__IO uint32_t SYSTCKCAL;
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uint32_t RESERVED13[41];
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__IO uint32_t STARTAPRP0; /* Offset 0x200 */
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__IO uint32_t STARTERP0;
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__IO uint32_t STARTRSRP0CLR;
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__IO uint32_t STARTSRP0;
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__IO uint32_t STARTAPRP1;
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__IO uint32_t STARTERP1;
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__IO uint32_t STARTRSRP1CLR;
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__IO uint32_t STARTSRP1;
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uint32_t RESERVED14[4];
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__IO uint32_t PDSLEEPCFG; /* Offset 0x230 */
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__IO uint32_t PDAWAKECFG;
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__IO uint32_t PDRUNCFG;
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uint32_t RESERVED15[110];
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__I uint32_t DEVICE_ID;
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} LPC_SYSCON_TypeDef;
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/*------------- Pin Connect Block (IOCON) --------------------------------*/
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typedef struct
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{
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__IO uint32_t PIO2_6;
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uint32_t RESERVED0[1];
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__IO uint32_t PIO2_0;
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__IO uint32_t RESET_PIO0_0;
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__IO uint32_t PIO0_1;
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__IO uint32_t PIO1_8;
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uint32_t RESERVED1[1];
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__IO uint32_t PIO0_2;
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__IO uint32_t PIO2_7;
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__IO uint32_t PIO2_8;
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__IO uint32_t PIO2_1;
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__IO uint32_t PIO0_3;
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__IO uint32_t PIO0_4;
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__IO uint32_t PIO0_5;
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__IO uint32_t PIO1_9;
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__IO uint32_t PIO3_4;
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__IO uint32_t PIO2_4;
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__IO uint32_t PIO2_5;
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__IO uint32_t PIO3_5;
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__IO uint32_t PIO0_6;
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__IO uint32_t PIO0_7;
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__IO uint32_t PIO2_9;
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__IO uint32_t PIO2_10;
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__IO uint32_t PIO2_2;
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__IO uint32_t PIO0_8;
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__IO uint32_t PIO0_9;
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__IO uint32_t JTAG_TCK_PIO0_10;
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__IO uint32_t PIO1_10;
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__IO uint32_t PIO2_11;
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__IO uint32_t JTAG_TDI_PIO0_11;
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__IO uint32_t JTAG_TMS_PIO1_0;
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__IO uint32_t JTAG_TDO_PIO1_1;
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__IO uint32_t JTAG_nTRST_PIO1_2;
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__IO uint32_t PIO3_0;
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__IO uint32_t PIO3_1;
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__IO uint32_t PIO2_3;
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__IO uint32_t ARM_SWDIO_PIO1_3;
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__IO uint32_t PIO1_4;
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__IO uint32_t PIO1_11;
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__IO uint32_t PIO3_2;
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__IO uint32_t PIO1_5;
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__IO uint32_t PIO1_6;
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__IO uint32_t PIO1_7;
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__IO uint32_t PIO3_3;
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__IO uint32_t SCKLOC; /* For HB1 only, new feature */
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} LPC_IOCON_TypeDef;
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/*------------- Power Management Unit (PMU) --------------------------*/
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typedef struct
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{
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__IO uint32_t PCON;
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__IO uint32_t GPREG0;
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__IO uint32_t GPREG1;
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__IO uint32_t GPREG2;
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__IO uint32_t GPREG3;
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__IO uint32_t GPREG4;
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} LPC_PMU_TypeDef;
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/*------------- General Purpose Input/Output (GPIO) --------------------------*/
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typedef struct
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{
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union {
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__IO uint32_t MASKED_ACCESS[4096];
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struct {
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uint32_t RESERVED0[4095];
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__IO uint32_t DATA;
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};
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};
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uint32_t RESERVED1[4096];
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__IO uint32_t DIR;
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__IO uint32_t IS;
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__IO uint32_t IBE;
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__IO uint32_t IEV;
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__IO uint32_t IE;
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__IO uint32_t RIS;
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__IO uint32_t MIS;
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__IO uint32_t IC;
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} LPC_GPIO_TypeDef;
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/*------------- Timer (TMR) --------------------------------------------------*/
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typedef struct
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{
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__IO uint32_t IR;
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__IO uint32_t TCR;
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__IO uint32_t TC;
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__IO uint32_t PR;
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__IO uint32_t PC;
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__IO uint32_t MCR;
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__IO uint32_t MR0;
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__IO uint32_t MR1;
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__IO uint32_t MR2;
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__IO uint32_t MR3;
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__IO uint32_t CCR;
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__I uint32_t CR0;
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uint32_t RESERVED1[3];
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__IO uint32_t EMR;
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uint32_t RESERVED2[12];
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__IO uint32_t CTCR;
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__IO uint32_t PWMC;
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} LPC_TMR_TypeDef;
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/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
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typedef struct
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{
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union {
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__I uint32_t RBR;
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__O uint32_t THR;
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__IO uint32_t DLL;
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};
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union {
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__IO uint32_t DLM;
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__IO uint32_t IER;
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};
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union {
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__I uint32_t IIR;
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__O uint32_t FCR;
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};
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__IO uint32_t LCR;
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__IO uint32_t MCR;
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__I uint32_t LSR;
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__I uint32_t MSR;
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__IO uint32_t SCR;
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__IO uint32_t ACR;
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__IO uint32_t ICR;
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__IO uint32_t FDR;
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uint32_t RESERVED0;
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__IO uint32_t TER;
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uint32_t RESERVED1[6];
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__IO uint32_t RS485CTRL;
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__IO uint32_t ADRMATCH;
|
||
|
|
__IO uint32_t RS485DLY;
|
||
|
|
__I uint32_t FIFOLVL;
|
||
|
|
} LPC_UART_TypeDef;
|
||
|
|
|
||
|
|
/*------------- Synchronous Serial Communication (SSP) -----------------------*/
|
||
|
|
typedef struct
|
||
|
|
{
|
||
|
|
__IO uint32_t CR0;
|
||
|
|
__IO uint32_t CR1;
|
||
|
|
__IO uint32_t DR;
|
||
|
|
__I uint32_t SR;
|
||
|
|
__IO uint32_t CPSR;
|
||
|
|
__IO uint32_t IMSC;
|
||
|
|
__IO uint32_t RIS;
|
||
|
|
__IO uint32_t MIS;
|
||
|
|
__IO uint32_t ICR;
|
||
|
|
} LPC_SSP_TypeDef;
|
||
|
|
|
||
|
|
/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
|
||
|
|
typedef struct
|
||
|
|
{
|
||
|
|
__IO uint32_t CONSET;
|
||
|
|
__I uint32_t STAT;
|
||
|
|
__IO uint32_t DAT;
|
||
|
|
__IO uint32_t ADR0;
|
||
|
|
__IO uint32_t SCLH;
|
||
|
|
__IO uint32_t SCLL;
|
||
|
|
__O uint32_t CONCLR;
|
||
|
|
__IO uint32_t MMCTRL;
|
||
|
|
__IO uint32_t ADR1;
|
||
|
|
__IO uint32_t ADR2;
|
||
|
|
__IO uint32_t ADR3;
|
||
|
|
__I uint32_t DATA_BUFFER;
|
||
|
|
__IO uint32_t MASK0;
|
||
|
|
__IO uint32_t MASK1;
|
||
|
|
__IO uint32_t MASK2;
|
||
|
|
__IO uint32_t MASK3;
|
||
|
|
} LPC_I2C_TypeDef;
|
||
|
|
|
||
|
|
/*------------- Watchdog Timer (WDT) -----------------------------------------*/
|
||
|
|
typedef struct
|
||
|
|
{
|
||
|
|
__IO uint32_t MOD;
|
||
|
|
__IO uint32_t TC;
|
||
|
|
__O uint32_t FEED;
|
||
|
|
__I uint32_t TV;
|
||
|
|
} LPC_WDT_TypeDef;
|
||
|
|
|
||
|
|
/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
|
||
|
|
typedef struct
|
||
|
|
{
|
||
|
|
__IO uint32_t CR;
|
||
|
|
__IO uint32_t GDR;
|
||
|
|
uint32_t RESERVED0;
|
||
|
|
__IO uint32_t INTEN;
|
||
|
|
__I uint32_t DR0;
|
||
|
|
__I uint32_t DR1;
|
||
|
|
__I uint32_t DR2;
|
||
|
|
__I uint32_t DR3;
|
||
|
|
__I uint32_t DR4;
|
||
|
|
__I uint32_t DR5;
|
||
|
|
__I uint32_t DR6;
|
||
|
|
__I uint32_t DR7;
|
||
|
|
__I uint32_t STAT;
|
||
|
|
} LPC_ADC_TypeDef;
|
||
|
|
|
||
|
|
|
||
|
|
/*------------- Universal Serial Bus (USB) -----------------------------------*/
|
||
|
|
typedef struct
|
||
|
|
{
|
||
|
|
__I uint32_t DevIntSt; /* USB Device Interrupt Registers */
|
||
|
|
__IO uint32_t DevIntEn;
|
||
|
|
__O uint32_t DevIntClr;
|
||
|
|
__O uint32_t DevIntSet;
|
||
|
|
|
||
|
|
__O uint32_t CmdCode; /* USB Device SIE Command Registers */
|
||
|
|
__I uint32_t CmdData;
|
||
|
|
|
||
|
|
__I uint32_t RxData; /* USB Device Transfer Registers */
|
||
|
|
__O uint32_t TxData;
|
||
|
|
__I uint32_t RxPLen;
|
||
|
|
__O uint32_t TxPLen;
|
||
|
|
__IO uint32_t Ctrl;
|
||
|
|
__O uint32_t DevFIQSel;
|
||
|
|
} LPC_USB_TypeDef;
|
||
|
|
|
||
|
|
#if defined ( __CC_ARM )
|
||
|
|
#pragma no_anon_unions
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
/******************************************************************************/
|
||
|
|
/* Peripheral memory map */
|
||
|
|
/******************************************************************************/
|
||
|
|
/* Base addresses */
|
||
|
|
#define LPC_FLASH_BASE (0x00000000UL)
|
||
|
|
#define LPC_RAM_BASE (0x10000000UL)
|
||
|
|
#define LPC_APB0_BASE (0x40000000UL)
|
||
|
|
#define LPC_AHB_BASE (0x50000000UL)
|
||
|
|
|
||
|
|
/* APB0 peripherals */
|
||
|
|
#define LPC_I2C_BASE (LPC_APB0_BASE + 0x00000)
|
||
|
|
#define LPC_WDT_BASE (LPC_APB0_BASE + 0x04000)
|
||
|
|
#define LPC_UART_BASE (LPC_APB0_BASE + 0x08000)
|
||
|
|
#define LPC_CT16B0_BASE (LPC_APB0_BASE + 0x0C000)
|
||
|
|
#define LPC_CT16B1_BASE (LPC_APB0_BASE + 0x10000)
|
||
|
|
#define LPC_CT32B0_BASE (LPC_APB0_BASE + 0x14000)
|
||
|
|
#define LPC_CT32B1_BASE (LPC_APB0_BASE + 0x18000)
|
||
|
|
#define LPC_ADC_BASE (LPC_APB0_BASE + 0x1C000)
|
||
|
|
#define LPC_USB_BASE (LPC_APB0_BASE + 0x20000)
|
||
|
|
#define LPC_PMU_BASE (LPC_APB0_BASE + 0x38000)
|
||
|
|
#define LPC_SSP_BASE (LPC_APB0_BASE + 0x40000)
|
||
|
|
#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
|
||
|
|
#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
|
||
|
|
|
||
|
|
/* AHB peripherals */
|
||
|
|
#define LPC_GPIO_BASE (LPC_AHB_BASE + 0x00000)
|
||
|
|
#define LPC_GPIO0_BASE (LPC_AHB_BASE + 0x00000)
|
||
|
|
#define LPC_GPIO1_BASE (LPC_AHB_BASE + 0x10000)
|
||
|
|
#define LPC_GPIO2_BASE (LPC_AHB_BASE + 0x20000)
|
||
|
|
#define LPC_GPIO3_BASE (LPC_AHB_BASE + 0x30000)
|
||
|
|
|
||
|
|
/******************************************************************************/
|
||
|
|
/* Peripheral declaration */
|
||
|
|
/******************************************************************************/
|
||
|
|
#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
|
||
|
|
#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
|
||
|
|
#define LPC_UART ((LPC_UART_TypeDef *) LPC_UART_BASE )
|
||
|
|
#define LPC_TMR16B0 ((LPC_TMR_TypeDef *) LPC_CT16B0_BASE)
|
||
|
|
#define LPC_TMR16B1 ((LPC_TMR_TypeDef *) LPC_CT16B1_BASE)
|
||
|
|
#define LPC_TMR32B0 ((LPC_TMR_TypeDef *) LPC_CT32B0_BASE)
|
||
|
|
#define LPC_TMR32B1 ((LPC_TMR_TypeDef *) LPC_CT32B1_BASE)
|
||
|
|
#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
|
||
|
|
#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
|
||
|
|
#define LPC_SSP ((LPC_SSP_TypeDef *) LPC_SSP_BASE )
|
||
|
|
#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
|
||
|
|
#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
|
||
|
|
#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
|
||
|
|
#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
|
||
|
|
#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
|
||
|
|
#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
|
||
|
|
#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
|
||
|
|
|
||
|
|
#endif // __LPC13xx_H__
|