159 lines
5.5 KiB
C
159 lines
5.5 KiB
C
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/*
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ChibiOS/RT - Copyright (C) 2006-2007 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32F103/pal_lld.c
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* @brief STM32 GPIO low level driver code
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* @addtogroup STM32F103_PAL
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* @{
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*/
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#include <ch.h>
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#include <pal.h>
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#if defined(STM32F10X_LD)
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#define APB2_RST_MASK (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | \
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RCC_APB2RSTR_IOPCRST | RCC_APB2RSTR_IOPDRST | \
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RCC_APB2RSTR_AFIORST)
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#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \
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RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \
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RCC_APB2ENR_AFIOEN)
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#elif defined(STM32F10X_HD)
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#define APB2_RST_MASK (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | \
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RCC_APB2RSTR_IOPCRST | RCC_APB2RSTR_IOPDRST | \
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RCC_APB2RSTR_IOPERST | RCC_APB2RSTR_IOPFRST | \
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RCC_APB2RSTR_IOPGRST | RCC_APB2RSTR_AFIORST);
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#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \
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RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \
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RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN | \
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RCC_APB2ENR_IOPGEN | RCC_APB2ENR_AFIOEN)
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#else
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/* Defaults on Medium Density devices.*/
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#define APB2_RST_MASK (RCC_APB2RSTR_IOPARST | RCC_APB2RSTR_IOPBRST | \
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RCC_APB2RSTR_IOPCRST | RCC_APB2RSTR_IOPDRST | \
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RCC_APB2RSTR_IOPERST | RCC_APB2RSTR_AFIORST);
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#define APB2_EN_MASK (RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | \
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RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | \
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RCC_APB2ENR_IOPEEN | RCC_APB2ENR_AFIOEN)
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#endif
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/**
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* @brief STM32 I/O ports configuration.
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* @details Ports A-D(E, F, G) clocks enabled, AFIO clock enabled.
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*
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* @param[in] config the STM32 ports configuration
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*/
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void _pal_lld_init(const STM32GPIOConfig *config) {
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/*
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* Enables the GPIO related clocks.
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*/
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RCC->APB2ENR |= APB2_EN_MASK;
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/*
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* Resets the GPIO ports and AFIO.
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*/
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RCC->APB2RSTR = APB2_RST_MASK;
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RCC->APB2RSTR = 0;
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IOPORT_A->ODR = config->PAData.odr;
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IOPORT_A->CRH = config->PAData.crh;
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IOPORT_A->CRL = config->PAData.crl;
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IOPORT_B->ODR = config->PBData.odr;
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IOPORT_B->CRH = config->PBData.crh;
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IOPORT_B->CRL = config->PBData.crl;
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IOPORT_C->ODR = config->PCData.odr;
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IOPORT_C->CRH = config->PCData.crh;
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IOPORT_C->CRL = config->PCData.crl;
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IOPORT_D->ODR = config->PDData.odr;
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IOPORT_D->CRH = config->PDData.crh;
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IOPORT_D->CRL = config->PDData.crl;
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#if !defined(STM32F10X_LD) || defined(__DOXYGEN__)
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IOPORT_E->ODR = config->PEData.odr;
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IOPORT_E->CRH = config->PEData.crh;
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IOPORT_E->CRL = config->PEData.crl;
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#endif
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#if defined(STM32F10X_HD) || defined(__DOXYGEN__)
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IOPORT_F->ODR = config->PFData.odr;
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IOPORT_F->CRH = config->PFData.crh;
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IOPORT_F->CRL = config->PFData.crl;
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IOPORT_G->ODR = config->PGData.odr;
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IOPORT_G->CRH = config->PGData.crh;
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IOPORT_G->CRL = config->PGData.crl;
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#endif
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}
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/**
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* @brief Pads mode setup.
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* @details This function programs a pads group belonging to the same port
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* with the specified mode.
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*
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* @param[in] port the port identifier
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* @param[in] mask the group mask
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* @param[in] mode the mode
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*
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* @note This function is not meant to be invoked directly by the application
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* code.
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* @note @p PAL_MODE_UNCONNECTED is implemented as push pull output at 2MHz.
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* @note Writing on pads programmed as pull-up or pull-down has the side
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* effect to modify the resistor setting because the output latched data
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* is used for the resistor selection.
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*/
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void _pal_lld_setgroupmode(ioportid_t port,
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ioportmask_t mask,
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uint_fast8_t mode) {
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static const uint8_t cfgtab[] = {
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4, /* PAL_MODE_RESET, implemented as input.*/
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2, /* PAL_MODE_UNCONNECTED, implemented as push pull output 2MHz.*/
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4, /* PAL_MODE_INPUT */
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8, /* PAL_MODE_INPUT_PULLUP */
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8, /* PAL_MODE_INPUT_PULLDOWN */
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3, /* PAL_MODE_OUTPUT_PUSHPULL, 50MHz.*/
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7, /* PAL_MODE_OUTPUT_OPENDRAIN, 50MHz.*/
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};
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uint32_t mh, ml, crh, crl, cfg;
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unsigned i;
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if (mode == PAL_MODE_INPUT_PULLUP)
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port->BSRR = mask;
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else if (mode == PAL_MODE_INPUT_PULLDOWN)
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port->BRR = mask;
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cfg = cfgtab[mode];
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mh = ml = crh = crl = 0;
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for (i = 0; i < 8; i++) {
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ml <<= 4;
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mh <<= 4;
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crl <<= 4;
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crh <<= 4;
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if ((mask & 1) == 0)
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ml |= 0xf;
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else
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crl |= cfg;
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if ((mask & 0x10000) == 0)
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mh |= 0xf;
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else
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crh |= cfg;
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mask >>= 1;
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}
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port->CRH = (port->CRH & mh) | crh;
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port->CRL = (port->CRL & ml) | crl;
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}
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/** @} */
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