2015-07-29 09:57:15 +00:00
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STM32 DMAv1 driver.
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Driver capability:
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- The driver supports the STM32 traditional DMA controller in the following
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configurations: 5ch, 7ch, 7ch+5ch.
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- Support for automatic the channel selection through the CSELR register.
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- For devices without CSELR register it is possible to select channels but
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the SYSCFG CFGR register is not configured, the user has to configure it
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before starting the DMA driver.
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- The driver supports shared ISR handlers with a quirk: the IRQ priority is
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established by the first allocated channel among the channels sharing the
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ISR.
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The file registry must export:
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2015-07-29 12:55:15 +00:00
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STM32_ADVANCED_DMA - TRUE not used by the DMA drivers but other
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drivers use it to enable checks on DMA
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channels. Probably will be removed in the
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future.
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STM32_DMA_SUPPORTS_CSELR - TRUE if the DMA have a CSELR register.
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2015-08-06 10:32:19 +00:00
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STM32_DMAn_NUM_CHANNELS - Number of channels in DMA "n".
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2015-07-29 09:57:15 +00:00
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STM32_DMAn_CHx_HANDLER - Vector name for IRQ "x".
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STM32_DMAn_CHxyz_HANDLER - Vector name for shared IRQs "x", "y" and "z".
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STM32_DMAn_CHx_NUMBER - Vector number for IRQ "x".
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STM32_DMAn_CHxyz_NUMBER - Vector number for shared IRQs "x", "y" and "z".
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Currently supported shared combinations are:
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STM32_DMA1_CH23_HANDLER
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STM32_DMA1_CH23_NUMBER
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STM32_DMA1_CH4567_HANDLER
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STM32_DMA1_CH4567_NUMBER
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