257 lines
7.7 KiB
C
257 lines
7.7 KiB
C
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file SPC560Pxx/hal_lld.h
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* @brief SPC560Pxx HAL subsystem low level driver header.
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* @pre This module requires the following macros to be defined in the
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* @p board.h file:
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* - SPC560P_XOSC_CLK.
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* .
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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#include "xpc560p.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Defines the support for realtime counters in the HAL.
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*/
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#define HAL_IMPLEMENTS_COUNTERS FALSE
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/**
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* @name Platform identification
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* @{
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*/
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#define PLATFORM_NAME "SPC560Pxx Chassis and Safety"
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/** @} */
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/**
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* @name Absolute Maximum Ratings
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* @{
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*/
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/**
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* @brief Maximum XOSC clock frequency.
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*/
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#define SPC560P_XOSC_CLK_MAX 40000000
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/**
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* @brief Minimum XOSC clock frequency.
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*/
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#define SPC560P_XOSC_CLK_MIN 4000000
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/**
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* @brief Maximum FMPLLs input clock frequency.
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*/
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#define SPC560P_FMPLLIN_MIN 4000000
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/**
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* @brief Maximum FMPLLs input clock frequency.
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*/
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#define SPC560P_FMPLLIN_MAX 16000000
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/**
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* @brief Maximum FMPLLs VCO clock frequency.
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*/
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#define SPC560P_FMPLLVCO_MAX 512000000
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/**
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* @brief Maximum FMPLLs VCO clock frequency.
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*/
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#define SPC560P_FMPLLVCO_MIN 256000000
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/**
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* @brief Maximum FMPLL0 output clock frequency.
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*/
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#define SPC560P_FMPLL0_CLK_MAX 64000000
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/**
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* @brief Maximum FMPLL1 output clock frequency.
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*/
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#define SPC560P_FMPLL1_CLK_MAX 120000000
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/**
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* @brief Maximum FMPLL1 1D1 output clock frequency.
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*/
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#define SPC560P_FMPLL1_1D1_CLK_MAX 80000000
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/** @} */
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/**
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* @name Internal clock sources
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* @{
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*/
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#define SPC560P_IRC_CLK 16000000 /**< Internal RC oscillator.*/
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/** @} */
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/**
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* @name FMPLL_CR register bits definitions
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* @{
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*/
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#define SPC560P_FMPLL_ODF_DIV2 (0 << 24)
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#define SPC560P_FMPLL_ODF_DIV4 (1 << 24)
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#define SPC560P_FMPLL_ODF_DIV8 (2 << 24)
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#define SPC560P_FMPLL_ODF_DIV16 (3 << 24)
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief Clock bypass.
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* @note If set to @p TRUE then the PLL is not started and initialized, the
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* external clock is used as-is and the other clock-related settings
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* are ignored.
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*/
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#if !defined(SPC560P_CLK_BYPASS) || defined(__DOXYGEN__)
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#define SPC560P_CLK_BYPASS FALSE
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#endif
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/**
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* @brief Disables the overclock checks.
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*/
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#if !defined(SPC560P_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
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#define SPC560P_ALLOW_OVERCLOCK FALSE
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#endif
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/**
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* @brief FMPLL0 IDF divider value.
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* @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
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*/
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#if !defined(SPC560P_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__)
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#define SPC560P_FMPLL0_IDF_VALUE 5
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#endif
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/**
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* @brief FMPLL0 NDIV divider value.
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* @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
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*/
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#if !defined(SPC560P_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__)
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#define SPC560P_FMPLL0_NDIV_VALUE 32
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#endif
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/**
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* @brief FMPLL0 ODF divider value.
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* @note The default value is calculated for XOSC=40MHz and PHI=64MHz.
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*/
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#if !defined(SPC560P_FMPLL0_ODF) || defined(__DOXYGEN__)
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#define SPC560P_FMPLL0_ODF SPC560P_FMPLL_ODF_DIV4
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/* Check on the XOSC frequency.*/
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#if (SPC560P_XOSC_CLK < SPC560P_XOSC_CLK_MIN) || \
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(SPC560P_XOSC_CLK > SPC560P_XOSC_CLK_MAX)
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#error "invalid SPC560P_XOSC_CLK value specified"
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#endif
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/* Check on SPC560P_FMPLL0_IDF_VALUE.*/
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#if (SPC560P_FMPLL0_IDF_VALUE < 1) || (SPC560P_FMPLL0_IDF_VALUE > 15)
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#error "invalid SPC560P_FMPLL0_IDF_VALUE value specified"
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#endif
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/* Check on SPC560P_FMPLL0_NDIV_VALUE.*/
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#if (SPC560P_FMPLL0_NDIV_VALUE < 32) || (SPC560P_FMPLL0_NDIV_VALUE > 96)
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#error "invalid SPC560P_FMPLL0_NDIV_VALUE value specified"
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#endif
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/* Check on SPC560P_FMPLL0_ODF.*/
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#if (SPC560P_FMPLL0_ODF == SPC560P_FMPLL_ODF_DIV2)
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#define SPC560P_FMPLL0_ODF_VALUE 2
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#elif (SPC560P_FMPLL0_ODF == SPC560P_FMPLL_ODF_DIV4)
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#define SPC560P_FMPLL0_ODF_VALUE 4
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#elif (SPC560P_FMPLL0_ODF == SPC560P_FMPLL_ODF_DIV8)
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#define SPC560P_FMPLL0_ODF_VALUE 8
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#elif (SPC560P_FMPLL0_ODF == SPC560P_FMPLL_ODF_DIV16)
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#define SPC560P_FMPLL0_ODF_VALUE 16
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#else
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#error "invalid SPC560P_FMPLL0_ODF value specified"
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#endif
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/**
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* @brief SPC560P_FMPLL0_VCO_CLK clock point.
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*/
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#define SPC560P_FMPLL0_VCO_CLK \
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((SPC560P_XOSC_CLK / SPC560P_FMPLL0_IDF_VALUE) * SPC560P_FMPLL0_NDIV_VALUE)
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/* Check on FMPLL0 VCO output.*/
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#if (SPC560P_FMPLL0_VCO_CLK < SPC560P_FMPLLVCO_MIN) || \
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(SPC560P_FMPLL0_VCO_CLK > SPC560P_FMPLLVCO_MAX)
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#error "SPC560P_FMPLL0_CLK outside acceptable range (SPC560P_FMPLLVCO_MIN...SPC560P_FMPLLVCO_MAX)"
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#endif
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/**
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* @brief SPC560P_XOSC_CLK clock point.
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*/
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#define SPC560P_FMPLL0_CLK \
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(SPC560P_FMPLL0_VCO_CLK / SPC560P_FMPLL0_ODF_VALUE)
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/* Check on SPC560P_FMPLL0_CLK.*/
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#if SPC560P_FMPLL0_CLK > SPC560P_FMPLL0_CLK_MAX
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#error "SPC560P_FMPLL0_CLK outside acceptable range (0...SPC560P_FMPLL0_CLK_MAX)"
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#endif
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/* FMPLL0 activation conditions.*/
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#if 1 || defined(__DOXYGEN__)
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/**
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* @brief FMPLL0 activation flag.
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*/
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#define SPC560P_ACTIVATE_FMPLL0 TRUE
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#else
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#define SPC560P_ACTIVATE_FMPLL0 FALSE
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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void hal_lld_init(void);
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void spc560p_clock_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HAL_LLD_H_ */
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/** @} */
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