2012-06-17 11:40:31 +00:00
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _BOARD_H_
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#define _BOARD_H_
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/*
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* Setup for STMicroelectronics STM32F4-Discovery board.
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*/
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/*
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* Board identifier.
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*/
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#define BOARD_OLIMEX_STM32_E407
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#define BOARD_NAME "Olimex STM32-P407"
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/*
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* Ethernet PHY type.
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*/
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#define BOARD_PHY_ID MII_KS8721_ID
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#define BOARD_PHY_RMII
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/*
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* Board frequencies.
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* NOTE: The LSE crystal is not fitted by default on the board.
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*/
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#define STM32_LSECLK 32768
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#define STM32_HSECLK 12000000
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/*
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* Board voltages.
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* Required for performance limits calculation.
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*/
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#define STM32_VDD 330
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/*
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* MCU type as defined in the ST header file stm32f4xx.h.
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*/
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#define STM32F4XX
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/*
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* IO pins assignments.
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*/
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#define GPIOA_BUTTON_WKUP 0
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#define GPIOA_ETH_RMII_REF_CLK 1
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#define GPIOA_ETH_RMII_MDIO 2
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#define GPIOA_ETH_RMII_MDINT 3
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#define GPIOA_ETH_RMII_CRS_DV 7
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#define GPIOA_USB_HS_BUSON 8
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#define GPIOA_OTG_FS_VBUS 9
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#define GPIOA_OTG_FS_ID 10
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#define GPIOA_OTG_FS_DM 11
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#define GPIOA_OTG_FS_DP 12
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#define GPIOA_JTAG_TMS 13
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#define GPIOA_JTAG_TCK 14
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#define GPIOA_JTAG_TDI 15
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#define GPIOB_USB_FS_BUSON 0
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#define GPIOB_USB_HS_FAULT 1
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#define GPIOB_BOOT1 2
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#define GPIOB_JTAG_TDO 3
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#define GPIOB_JTAG_TRST 4
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#define GPIOB_I2C1_SCL 8
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#define GPIOB_I2C1_SDA 9
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#define GPIOB_SPI2_SCK 10
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#define GPIOB_USART3_TX 10 /* Same as GPIOB_SPI2_SCK. */
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2012-06-17 12:30:06 +00:00
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#define GPIOB_USART3_RX 11
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2012-06-17 11:40:31 +00:00
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#define GPIOB_OTG_HS_ID 12
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#define GPIOB_OTG_FS_VBUS 13
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#define GPIOB_OTG_HS_DM 14
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#define GPIOB_OTG_HS_DP 15
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#define GPIOC_ETH_RMII_MDC 1
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#define GPIOC_SPI2_MISO 2
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#define GPIOC_SPI2_MOSI 3
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#define GPIOC_ETH_RMII_RXD0 4
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#define GPIOC_ETH_RMII_RXD1 5
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#define GPIOC_USART6_TX 6
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#define GPIOC_USART6_RX 7
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#define GPIOC_SD_D0 8
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#define GPIOC_SD_D1 9
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#define GPIOC_SD_D2 10
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#define GPIOC_SD_D3 11
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#define GPIOC_SD_CLK 12
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#define GPIOC_LED 13
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#define GPIOC_OSC32_IN 14
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#define GPIOC_OSC32_OUT 15
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#define GPIOD_SD_CMD 2
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#define GPIOF_USB_FS_FAULT 11
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#define GPIOG_SPI2_CS 10
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#define GPIOG_ETH_RMII_TXEN 11
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#define GPIOG_ETH_RMII_TXD0 13
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#define GPIOG_ETH_RMII_TXD1 14
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#define GPIOH_OSC_IN 0
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#define GPIOH_OSC_OUT 1
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/*
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* I/O ports initial setup, this configuration is established soon after reset
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* in the initialization code.
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* Please refer to the STM32 Reference Manual for details.
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*/
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#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
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#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
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#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
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#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
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#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
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#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
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#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
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#define PIN_OSPEED_25M(n) (1U << ((n) * 2))
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#define PIN_OSPEED_50M(n) (2U << ((n) * 2))
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#define PIN_OSPEED_100M(n) (3U << ((n) * 2))
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#define PIN_PUDR_FLOATING(n) (0U << ((n) * 2))
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#define PIN_PUDR_PULLUP(n) (1U << ((n) * 2))
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#define PIN_PUDR_PULLDOWN(n) (2U << ((n) * 2))
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#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
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/*
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* Port A setup.
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2012-06-17 12:30:06 +00:00
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* All input with pull-up except:
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2012-06-17 11:40:31 +00:00
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* PA0 - GPIOA_BUTTON_WKUP (input floating).
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* PA1 - GPIOA_ETH_RMII_REF_CLK(alternate 11).
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* PA2 - GPIOA_ETH_RMII_MDIO (alternate 11).
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* PA3 - GPIOA_ETH_RMII_MDINT (input floating).
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* PA7 - GPIOA_ETH_RMII_CRS_DV (alternate 11).
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* PA8 - GPIOA_USB_HS_BUSON (output push-pull).
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* PA9 - GPIOA_OTG_FS_VBUS (input pull-down).
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* PA10 - GPIOA_OTG_FS_ID (alternate 10).
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* PA11 - GPIOA_OTG_FS_DM (alternate 10).
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* PA12 - GPIOA_OTG_FS_DP (alternate 10).
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* PA13 - GPIOA_JTAG_TMS (alternate 0).
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* PA14 - GPIOA_JTAG_TCK (alternate 0, pull-down).
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* PA15 - GPIOA_JTAG_TDI (alternate 0).
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*/
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#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON_WKUP) | \
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PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_REF_CLK) | \
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PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_MDIO) | \
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PIN_MODE_INPUT(GPIOA_ETH_RMII_MDINT) | \
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2012-06-17 12:30:06 +00:00
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PIN_MODE_INPUT(4) | \
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PIN_MODE_INPUT(5) | \
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PIN_MODE_INPUT(6) | \
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2012-06-17 11:40:31 +00:00
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PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_CRS_DV) | \
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PIN_MODE_OUTPUT(GPIOA_USB_HS_BUSON) | \
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PIN_MODE_INPUT(GPIOA_OTG_FS_VBUS) | \
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PIN_MODE_ALTERNATE(GPIOA_OTG_FS_ID) | \
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PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \
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PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \
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PIN_MODE_ALTERNATE(GPIOA_JTAG_TMS) | \
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PIN_MODE_ALTERNATE(GPIOA_JTAG_TCK) | \
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PIN_MODE_ALTERNATE(GPIOA_JTAG_TDI))
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#define VAL_GPIOA_OTYPER 0x00000000
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#define VAL_GPIOA_OSPEEDR 0xFFFFFFFF
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2012-06-17 12:30:06 +00:00
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#define VAL_GPIOA_PUPDR (PIN_PUDR_PULLUP(4) | \
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PIN_PUDR_PULLUP(5) | \
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PIN_PUDR_PULLUP(6) | \
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2012-06-17 11:40:31 +00:00
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PIN_PUDR_PULLDOWN(GPIOA_OTG_FS_VBUS) | \
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PIN_PUDR_PULLDOWN(GPIOA_SWCLK))
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#define VAL_GPIOA_ODR 0xFFFFFFFF
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#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ETH_RMII_REF_CLK, 11) | \
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PIN_AFIO_AF(GPIOA_ETH_RMII_MDIO, 11) | \
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PIN_AFIO_AF(GPIOA_ETH_RMII_CRS_DV, 11))
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#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_MCO1, 0) | \
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PIN_AFIO_AF(GPIOA_OTG_FS_ID, 10) | \
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PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \
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PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \
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PIN_AFIO_AF(GPIOA_JTAG_TMS, 0) | \
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PIN_AFIO_AF(GPIOA_JTAG_TCK, 0) | \
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PIN_AFIO_AF(GPIOA_JTAG_TDI, 0))
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/*
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* Port B setup.
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2012-06-17 12:30:06 +00:00
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* All input with pull-up except:
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2012-06-17 11:40:31 +00:00
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* PB0 - GPIOB_USB_FS_BUSON (output push-pull).
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* PB1 - GPIOB_USB_HS_FAULT (input floating).
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* PB2 - GPIOB_BOOT1 (input floating).
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* PB3 - GPIOB_JTAG_TDO (alternate 0).
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* PB4 - GPIOB_JTAG_TRST (alternate 0).
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* PB8 - GPIOB_I2C1_SCL (alternate 4).
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* PB9 - GPIOB_I2C1_SDA (alternate 4).
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* PB10 - GPIOB_SPI2_SCK (alternate 5).
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* PB12 - GPIOB_OTG_HS_ID (alternate 10).
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* PB13 - GPIOB_OTG_FS_VBUS (input pull-down).
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* PB14 - GPIOB_OTG_HS_DM (alternate 10).
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* PB15 - GPIOB_OTG_HS_DP (alternate 10).
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*/
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#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_USB_FS_BUSON) | \
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PIN_MODE_INPUT(GPIOB_USB_HS_FAULT) | \
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PIN_MODE_INPUT(GPIOB_BOOT1) | \
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PIN_MODE_ALTERNATE(GPIOB_JTAG_TDO) | \
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PIN_MODE_INPUT(GPIOB_JTAG_TRST) | \
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2012-06-17 12:30:06 +00:00
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PIN_MODE_INPUT(5) | \
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PIN_MODE_INPUT(6) | \
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PIN_MODE_INPUT(7) | \
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2012-06-17 11:40:31 +00:00
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PIN_MODE_ALTERNATE(GPIOB_I2C1_SCL) | \
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PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \
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PIN_MODE_ALTERNATE(GPIOB_SPI2_SCK) | \
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2012-06-17 12:30:06 +00:00
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PIN_MODE_INPUT(11) | \
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2012-06-17 11:40:31 +00:00
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PIN_MODE_ALTERNATE(GPIOB_OTG_HS_ID) | \
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PIN_MODE_INPUT(GPIOB_OTG_FS_VBUS) | \
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PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) | \
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PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP))
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#define VAL_GPIOB_OTYPER (PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SCL) | \
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PIN_OTYPE_OPENDRAIN(GPIOB_I2C1_SDA))
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#define VAL_GPIOB_OSPEEDR 0xFFFFFFFF
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2012-06-17 12:30:06 +00:00
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#define VAL_GPIOB_PUPDR (PIN_PUDR_PULLUP(5) | \
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PIN_PUDR_PULLUP(6) | \
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PIN_PUDR_PULLUP(7) | \
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PIN_PUDR_PULLUP(11) | \
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2012-06-17 11:40:31 +00:00
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PIN_PUDR_PULLDOWN(GPIOB_OTG_FS_VBUS))
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#define VAL_GPIOB_ODR 0xFFFFFFFD
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#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_JTAG_TDO, 0) | \
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PIN_AFIO_AF(GPIOB_JTAG_TRST, 0))
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#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_I2C1_SDA, 4) | \
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PIN_AFIO_AF(GPIOB_I2C1_SCL, 4) | \
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PIN_AFIO_AF(GPIOB_SPI2_SCK, 5) | \
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PIN_AFIO_AF(GPIOB_OTG_HS_ID, 10) | \
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PIN_AFIO_AF(GPIOB_OTG_HS_DM, 10) | \
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PIN_AFIO_AF(GPIOB_OTG_HS_DP, 10))
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/*
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* Port C setup.
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* All input with pull-up except:
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2012-06-17 12:30:06 +00:00
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* PC0 - GPIOC_P0 (input pull-up).
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* PC1 - GPIOC_ETH_RMII_MDC (alternate 11).
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* PC2 - GPIOC_SPI2_MISO (alternate 5).
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* PC3 - GPIOC_SPI2_MOSI (alternate 5).
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* PC4 - GPIOC_ETH_RMII_RXD0 (alternate 11).
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* PC5 - GPIOC_ETH_RMII_RXD1 (alternate 11).
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* PC6 - GPIOC_USART6_TX (alternate 8).
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* PC7 - GPIOC_USART6_RX (alternate 8).
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* PC8 - GPIOC_SD_D0 (alternate 12).
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* PC9 - GPIOC_SD_D1 (alternate 12).
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* PC10 - GPIOC_SD_D2 (alternate 12).
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* PC11 - GPIOC_SD_D3 (alternate 12).
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* PC12 - GPIOC_SD_CLK (alternate 12).
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* PC13 - GPIOC_LED (output push-pull).
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* PC14 - GPIOC_OSC32_IN (input floating).
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* PC15 - GPIOC_OSC32_OUT (input floating).
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2012-06-17 11:40:31 +00:00
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*/
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2012-06-17 12:30:06 +00:00
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#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_P0) | \
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PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_MDC) | \
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PIN_MODE_ALTERNATE(GPIOC_SPI2_MISO) | \
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PIN_MODE_ALTERNATE(GPIOC_SPI2_MOSI) | \
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PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD0) | \
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PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD1) | \
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PIN_MODE_ALTERNATE(GPIOC_USART6_TX) | \
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PIN_MODE_ALTERNATE(GPIOC_USART6_RX) | \
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PIN_MODE_ALTERNATE(GPIOC_SD_D0) | \
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PIN_MODE_ALTERNATE(GPIOC_SD_D1) | \
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PIN_MODE_ALTERNATE(GPIOC_SD_D2) | \
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PIN_MODE_ALTERNATE(GPIOC_SD_D3) | \
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PIN_MODE_ALTERNATE(GPIOC_SD_CLK) | \
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PIN_MODE_OUTPUT(GPIOC_LED) | \
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PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
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PIN_MODE_INPUT(GPIOC_OSC32_OUT))
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#define VAL_GPIOC_OTYPER 0x00000000
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#define VAL_GPIOC_OSPEEDR 0xFFFFFFFF
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#define VAL_GPIOC_PUPDR (PIN_PUDR_PULLUP(GPIOC_P0))
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#define VAL_GPIOC_ODR 0xFFFFFFFF
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#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ETH_RMII_MDC, 11) | \
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PIN_AFIO_AF(GPIOC_SPI2_MISO, 5) | \
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PIN_AFIO_AF(GPIOC_SPI2_MOSI, 5) | \
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PIN_AFIO_AF(GPIOC_ETH_RMII_RXD0, 11) | \
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PIN_AFIO_AF(GPIOC_ETH_RMII_RXD1, 11) | \
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PIN_AFIO_AF(GPIOC_USART6_TX, 8) | \
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PIN_AFIO_AF(GPIOC_USART6_RX, 8))
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#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SD_D0, 12) | \
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PIN_AFIO_AF(GPIOC_SD_D1, 12) | \
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PIN_AFIO_AF(GPIOC_SD_D2, 12) | \
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PIN_AFIO_AF(GPIOC_SD_D3, 12) | \
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PIN_AFIO_AF(GPIOC_SD_CLK, 12))
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2012-06-17 11:40:31 +00:00
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/*
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* Port D setup.
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* All input with pull-up except:
|
2012-06-17 12:30:06 +00:00
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* PD2 - GPIOD_SD_CMD (alternate 12).
|
2012-06-17 11:40:31 +00:00
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*/
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2012-06-17 12:30:06 +00:00
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#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_SD_CMD))
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#define VAL_GPIOD_OTYPER 0x00000000
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#define VAL_GPIOD_OSPEEDR 0xFFFFFFFF
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#define VAL_GPIOD_PUPDR (PIN_PUDR_PULLUP(0) | \
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PIN_PUDR_PULLUP(1) | \
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PIN_PUDR_FLOATING(GPIOD_SD_CMD) | \
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PIN_PUDR_PULLUP(3) | \
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PIN_PUDR_PULLUP(4) | \
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PIN_PUDR_PULLUP(5) | \
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PIN_PUDR_PULLUP(6) | \
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PIN_PUDR_PULLUP(7) | \
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PIN_PUDR_PULLUP(8) | \
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PIN_PUDR_PULLUP(9) | \
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PIN_PUDR_PULLUP(10) | \
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PIN_PUDR_PULLUP(11) | \
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PIN_PUDR_PULLUP(12) | \
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PIN_PUDR_PULLUP(13) | \
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PIN_PUDR_PULLUP(14) | \
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PIN_PUDR_PULLUP(15))
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#define VAL_GPIOD_ODR 0xFFFFFFFF
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#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_SD_CMD, 12))
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#define VAL_GPIOD_AFRH 0x00000000
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2012-06-17 11:40:31 +00:00
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/*
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* Port E setup.
|
2012-06-17 12:30:06 +00:00
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* All input with pull-up.
|
2012-06-17 11:40:31 +00:00
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*/
|
2012-06-17 12:30:06 +00:00
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#define VAL_GPIOE_MODER 0x00000000
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#define VAL_GPIOE_OTYPER 0x00000000
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#define VAL_GPIOE_OSPEEDR 0xFFFFFFFF
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#define VAL_GPIOE_PUPDR (PIN_PUDR_PULLUP(0) | \
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PIN_PUDR_PULLUP(1) | \
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PIN_PUDR_PULLUP(2) | \
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PIN_PUDR_PULLUP(3) | \
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PIN_PUDR_PULLUP(4) | \
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PIN_PUDR_PULLUP(5) | \
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PIN_PUDR_PULLUP(6) | \
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PIN_PUDR_PULLUP(7) | \
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PIN_PUDR_PULLUP(8) | \
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PIN_PUDR_PULLUP(9) | \
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PIN_PUDR_PULLUP(10) | \
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PIN_PUDR_PULLUP(11) | \
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PIN_PUDR_PULLUP(12) | \
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PIN_PUDR_PULLUP(13) | \
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PIN_PUDR_PULLUP(14) | \
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PIN_PUDR_PULLUP(15))
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#define VAL_GPIOE_ODR 0xFFFFFFFF
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#define VAL_GPIOE_AFRL 0x00000000
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#define VAL_GPIOE_AFRH 0x00000000
|
2012-06-17 11:40:31 +00:00
|
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|
/*
|
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* Port F setup.
|
2012-06-17 12:30:06 +00:00
|
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|
* All input with pull-up except:
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* PF11 - GPIOF_USB_FS_FAULT (input floating).
|
2012-06-17 11:40:31 +00:00
|
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|
*/
|
2012-06-17 12:30:06 +00:00
|
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|
#define VAL_GPIOF_MODER 0x00000000
|
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#define VAL_GPIOF_OTYPER 0x00000000
|
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#define VAL_GPIOF_OSPEEDR 0xFFFFFFFF
|
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#define VAL_GPIOF_PUPDR (PIN_PUDR_PULLUP(0) | \
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PIN_PUDR_PULLUP(1) | \
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PIN_PUDR_PULLUP(2) | \
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PIN_PUDR_PULLUP(3) | \
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PIN_PUDR_PULLUP(4) | \
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PIN_PUDR_PULLUP(5) | \
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PIN_PUDR_PULLUP(6) | \
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PIN_PUDR_PULLUP(7) | \
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PIN_PUDR_PULLUP(8) | \
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PIN_PUDR_PULLUP(9) | \
|
|
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|
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PIN_PUDR_PULLUP(10) | \
|
|
|
|
|
PIN_PUDR_FLOATING(GPIOF_USB_FS_FAULT) | \
|
|
|
|
|
PIN_PUDR_PULLUP(12) | \
|
|
|
|
|
PIN_PUDR_PULLUP(13) | \
|
|
|
|
|
PIN_PUDR_PULLUP(14) | \
|
|
|
|
|
PIN_PUDR_PULLUP(15))
|
|
|
|
|
#define VAL_GPIOF_ODR 0xFFFFFFFF
|
|
|
|
|
#define VAL_GPIOF_AFRL 0x00000000
|
|
|
|
|
#define VAL_GPIOF_AFRH 0x00000000
|
2012-06-17 11:40:31 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Port G setup.
|
|
|
|
|
* All input with pull-up.
|
|
|
|
|
*/
|
2012-06-17 12:30:06 +00:00
|
|
|
#define VAL_GPIOG_MODER 0x00000000
|
|
|
|
|
#define VAL_GPIOG_OTYPER 0x00000000
|
|
|
|
|
#define VAL_GPIOG_OSPEEDR 0xFFFFFFFF
|
|
|
|
|
#define VAL_GPIOG_PUPDR (PIN_PUDR_PULLUP(0) | \
|
|
|
|
|
PIN_PUDR_PULLUP(1) | \
|
|
|
|
|
PIN_PUDR_PULLUP(2) | \
|
|
|
|
|
PIN_PUDR_PULLUP(3) | \
|
|
|
|
|
PIN_PUDR_PULLUP(4) | \
|
|
|
|
|
PIN_PUDR_PULLUP(5) | \
|
|
|
|
|
PIN_PUDR_PULLUP(6) | \
|
|
|
|
|
PIN_PUDR_PULLUP(7) | \
|
|
|
|
|
PIN_PUDR_PULLUP(8) | \
|
|
|
|
|
PIN_PUDR_PULLUP(9) | \
|
|
|
|
|
PIN_PUDR_PULLUP(10) | \
|
|
|
|
|
PIN_PUDR_PULLUP(11) | \
|
|
|
|
|
PIN_PUDR_PULLUP(12) | \
|
|
|
|
|
PIN_PUDR_PULLUP(13) | \
|
|
|
|
|
PIN_PUDR_PULLUP(14) | \
|
|
|
|
|
PIN_PUDR_PULLUP(15))
|
|
|
|
|
#define VAL_GPIOG_ODR 0xFFFFFFFF
|
|
|
|
|
#define VAL_GPIOG_AFRL 0x00000000
|
|
|
|
|
#define VAL_GPIOG_AFRH 0x00000000
|
2012-06-17 11:40:31 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Port H setup.
|
|
|
|
|
* All input with pull-up except:
|
|
|
|
|
* PH0 - GPIOH_OSC_IN (input floating).
|
|
|
|
|
* PH1 - GPIOH_OSC_OUT (input floating).
|
|
|
|
|
*/
|
2012-06-17 12:30:06 +00:00
|
|
|
#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
|
|
|
|
|
PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
|
|
|
|
|
PIN_MODE_INPUT(2) | \
|
|
|
|
|
PIN_MODE_INPUT(3) | \
|
|
|
|
|
PIN_MODE_INPUT(4) | \
|
|
|
|
|
PIN_MODE_INPUT(5) | \
|
|
|
|
|
PIN_MODE_INPUT(6) | \
|
|
|
|
|
PIN_MODE_INPUT(7) | \
|
|
|
|
|
PIN_MODE_INPUT(8) | \
|
|
|
|
|
PIN_MODE_INPUT(9) | \
|
|
|
|
|
PIN_MODE_INPUT(10) | \
|
|
|
|
|
PIN_MODE_INPUT(11) | \
|
|
|
|
|
PIN_MODE_INPUT(12) | \
|
|
|
|
|
PIN_MODE_INPUT(13) | \
|
|
|
|
|
PIN_MODE_INPUT(14) | \
|
|
|
|
|
PIN_MODE_INPUT(15))
|
|
|
|
|
#define VAL_GPIOH_OTYPER 0x00000000
|
|
|
|
|
#define VAL_GPIOH_OSPEEDR 0xFFFFFFFF
|
|
|
|
|
#define VAL_GPIOH_PUPDR (PIN_PUDR_FLOATING(GPIOH_OSC_IN) | \
|
|
|
|
|
PIN_PUDR_FLOATING(GPIOH_OSC_OUT) | \
|
|
|
|
|
PIN_PUDR_PULLUP(2) | \
|
|
|
|
|
PIN_PUDR_PULLUP(3) | \
|
|
|
|
|
PIN_PUDR_PULLUP(4) | \
|
|
|
|
|
PIN_PUDR_PULLUP(5) | \
|
|
|
|
|
PIN_PUDR_PULLUP(6) | \
|
|
|
|
|
PIN_PUDR_PULLUP(7) | \
|
|
|
|
|
PIN_PUDR_PULLUP(8) | \
|
|
|
|
|
PIN_PUDR_PULLUP(9) | \
|
|
|
|
|
PIN_PUDR_PULLUP(10) | \
|
|
|
|
|
PIN_PUDR_PULLUP(11) | \
|
|
|
|
|
PIN_PUDR_PULLUP(12) | \
|
|
|
|
|
PIN_PUDR_PULLUP(13) | \
|
|
|
|
|
PIN_PUDR_PULLUP(14) | \
|
|
|
|
|
PIN_PUDR_PULLUP(15))
|
|
|
|
|
#define VAL_GPIOH_ODR 0xFFFFFFFF
|
|
|
|
|
#define VAL_GPIOH_AFRL 0x00000000
|
|
|
|
|
#define VAL_GPIOH_AFRH 0x00000000
|
2012-06-17 11:40:31 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Port I setup.
|
|
|
|
|
* All input with pull-up.
|
|
|
|
|
*/
|
2012-06-17 12:30:06 +00:00
|
|
|
#define VAL_GPIOI_MODER 0x00000000
|
|
|
|
|
#define VAL_GPIOI_OTYPER 0x00000000
|
|
|
|
|
#define VAL_GPIOI_OSPEEDR 0xFFFFFFFF
|
|
|
|
|
#define VAL_GPIOI_PUPDR (PIN_PUDR_PULLUP(0) | \
|
|
|
|
|
PIN_PUDR_PULLUP(1) | \
|
|
|
|
|
PIN_PUDR_PULLUP(2) | \
|
|
|
|
|
PIN_PUDR_PULLUP(3) | \
|
|
|
|
|
PIN_PUDR_PULLUP(4) | \
|
|
|
|
|
PIN_PUDR_PULLUP(5) | \
|
|
|
|
|
PIN_PUDR_PULLUP(6) | \
|
|
|
|
|
PIN_PUDR_PULLUP(7) | \
|
|
|
|
|
PIN_PUDR_PULLUP(8) | \
|
|
|
|
|
PIN_PUDR_PULLUP(9) | \
|
|
|
|
|
PIN_PUDR_PULLUP(10) | \
|
|
|
|
|
PIN_PUDR_PULLUP(11) | \
|
|
|
|
|
PIN_PUDR_PULLUP(12) | \
|
|
|
|
|
PIN_PUDR_PULLUP(13) | \
|
|
|
|
|
PIN_PUDR_PULLUP(14) | \
|
|
|
|
|
PIN_PUDR_PULLUP(15))
|
|
|
|
|
#define VAL_GPIOI_ODR 0xFFFFFFFF
|
|
|
|
|
#define VAL_GPIOI_AFRL 0x00000000
|
|
|
|
|
#define VAL_GPIOI_AFRH 0x00000000
|
2012-06-17 11:40:31 +00:00
|
|
|
|
|
|
|
|
#if !defined(_FROM_ASM_)
|
|
|
|
|
#ifdef __cplusplus
|
|
|
|
|
extern "C" {
|
|
|
|
|
#endif
|
|
|
|
|
void boardInit(void);
|
|
|
|
|
#ifdef __cplusplus
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
#endif /* _FROM_ASM_ */
|
|
|
|
|
|
|
|
|
|
#endif /* _BOARD_H_ */
|
