2013-02-04 13:38:36 +00:00
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012,2013 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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2013-02-05 11:30:59 +00:00
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* @file SPC56ELxx/hwconf.s
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* @brief SPC56ELxx low level hardware configuration.
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2013-02-04 13:38:36 +00:00
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*
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* @addtogroup PPC_CORE
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* @{
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*/
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2013-02-05 11:18:27 +00:00
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/**
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* @name MASx registers definitions.
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* @{
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*/
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#define MAS0_TBLMAS_TBL 0x10000000
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#define MAS0_ESEL_MASK 0x000F0000
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#define MAS0_ESEL(n) ((n) << 16)
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#define MAS1_VALID 0x80000000
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#define MAS1_IPROT 0x40000000
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#define MAS1_TID_MASK 0x00FF0000
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#define MAS1_TS 0x00001000
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#define MAS1_TSISE_MASK 0x00000F80
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#define MAS1_TSISE_1K 0x00000000
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#define MAS1_TSISE_2K 0x00000080
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#define MAS1_TSISE_4K 0x00000100
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#define MAS1_TSISE_8K 0x00000180
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#define MAS1_TSISE_16K 0x00000200
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#define MAS1_TSISE_32K 0x00000280
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#define MAS1_TSISE_64K 0x00000300
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#define MAS1_TSISE_128K 0x00000380
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#define MAS1_TSISE_256K 0x00000400
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#define MAS1_TSISE_512K 0x00000480
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#define MAS1_TSISE_1M 0x00000500
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#define MAS1_TSISE_2M 0x00000580
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#define MAS1_TSISE_4M 0x00000600
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#define MAS1_TSISE_8M 0x00000680
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#define MAS1_TSISE_16M 0x00000700
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#define MAS1_TSISE_32M 0x00000780
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#define MAS1_TSISE_64M 0x00000800
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#define MAS1_TSISE_128M 0x00000880
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#define MAS1_TSISE_256M 0x00000900
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#define MAS1_TSISE_512M 0x00000980
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#define MAS1_TSISE_1G 0x00000A00
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#define MAS1_TSISE_2G 0x00000A80
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#define MAS1_TSISE_4G 0x00000B00
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#define MAS2_EPN_MASK 0xFFFFFC00
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#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK)
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#define MAS2_EBOOK 0x00000000
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#define MAS2_VLE 0x00000020
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#define MAS2_W 0x00000010
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#define MAS2_I 0x00000008
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#define MAS2_M 0x00000004
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#define MAS2_G 0x00000002
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#define MAS2_E 0x00000001
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#define MAS3_RPN_MASK 0xFFFFFC00
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#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK)
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#define MAS3_U0 0x00000200
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#define MAS3_U1 0x00000100
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#define MAS3_U2 0x00000080
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#define MAS3_U3 0x00000040
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#define MAS3_UX 0x00000020
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#define MAS3_SX 0x00000010
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#define MAS3_UW 0x00000008
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#define MAS3_SW 0x00000004
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#define MAS3_UR 0x00000002
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#define MAS3_SR 0x00000001
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/** @} */
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/**
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* @name TLB default settings
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* @{
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*/
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#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
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#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_2M)
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#define TLB0_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE)
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#define TLB0_MAS3 (MAS3_RPN(0x00000000) | \
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MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
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MAS3_UR | MAS3_SR)
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#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
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#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_16M)
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#define TLB1_MAS2 (MAS2_EPN(0x20000000) | MAS2_VLE)
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#define TLB1_MAS3 (MAS3_RPN(0x20000000) | \
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MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
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MAS3_UR | MAS3_SR)
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#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
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#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_128K)
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#define TLB2_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE | MAS2_I)
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#define TLB2_MAS3 (MAS3_RPN(0x40000000) | \
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MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
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MAS3_UR | MAS3_SR)
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#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
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#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
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#define TLB3_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I)
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#define TLB3_MAS3 (MAS3_RPN(0xC3F00000) | \
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MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
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#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
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#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_2M)
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#define TLB4_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I)
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#define TLB4_MAS3 (MAS3_RPN(0xFFE00000) | \
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MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
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/** @} */
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2013-02-04 14:47:02 +00:00
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#if !defined(__DOXYGEN__)
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2013-02-04 13:38:36 +00:00
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.section .hwinit, "ax"
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.align 2
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2013-02-05 11:30:59 +00:00
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.globl _hwconf
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.type _hwconf, @function
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_hwconf:
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2013-02-05 11:18:27 +00:00
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/* TLB0 allocated to flash.*/
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e_lis r3, TLB0_MAS0@h
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mtspr 624, r3 /* MAS0 */
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e_lis r3, TLB0_MAS1@h
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e_or2i r3, TLB0_MAS1@l
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mtspr 625, r3 /* MAS1 */
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e_lis r3, TLB0_MAS2@h
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e_or2i r3, TLB0_MAS2@l
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mtspr 626, r3 /* MAS2 */
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e_lis r3, TLB0_MAS3@h
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e_or2i r3, TLB0_MAS3@l
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mtspr 627, r3 /* MAS3 */
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tlbwe
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/* TLB1 allocated to external RAM, if any.*/
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e_lis r3, TLB1_MAS0@h
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mtspr 624, r3 /* MAS0 */
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e_lis r3, TLB1_MAS1@h
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e_or2i r3, TLB1_MAS1@l
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mtspr 625, r3 /* MAS1 */
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e_lis r3, TLB1_MAS2@h
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e_or2i r3, TLB1_MAS2@l
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mtspr 626, r3 /* MAS2 */
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e_lis r3, TLB1_MAS3@h
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e_or2i r3, TLB1_MAS3@l
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mtspr 627, r3 /* MAS3 */
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tlbwe
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/* TLB2 allocated to internal RAM.*/
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e_lis r3, TLB2_MAS0@h
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mtspr 624, r3 /* MAS0 */
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e_lis r3, TLB2_MAS1@h
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e_or2i r3, TLB2_MAS1@l
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mtspr 625, r3 /* MAS1 */
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e_lis r3, TLB2_MAS2@h
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e_or2i r3, TLB2_MAS2@l
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mtspr 626, r3 /* MAS2 */
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e_lis r3, TLB2_MAS3@h
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e_or2i r3, TLB2_MAS3@l
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mtspr 627, r3 /* MAS3 */
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tlbwe
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/* TLB3 allocated to internal Peripherals Bridge A.*/
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e_lis r3, TLB3_MAS0@h
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mtspr 624, r3 /* MAS0 */
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e_lis r3, TLB3_MAS1@h
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e_or2i r3, TLB3_MAS1@l
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mtspr 625, r3 /* MAS1 */
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e_lis r3, TLB3_MAS2@h
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e_or2i r3, TLB3_MAS2@l
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mtspr 626, r3 /* MAS2 */
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e_lis r3, TLB3_MAS3@h
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e_or2i r3, TLB3_MAS3@l
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mtspr 627, r3 /* MAS3 */
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tlbwe
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/* TLB4 allocated to internal Peripherals Bridge B.*/
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e_lis r3, TLB4_MAS0@h
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mtspr 624, r3 /* MAS0 */
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e_lis r3, TLB4_MAS1@h
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e_or2i r3, TLB4_MAS1@l
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mtspr 625, r3 /* MAS1 */
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e_lis r3, TLB4_MAS2@h
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e_or2i r3, TLB4_MAS2@l
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mtspr 626, r3 /* MAS2 */
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e_lis r3, TLB4_MAS3@h
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e_or2i r3, TLB4_MAS3@l
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mtspr 627, r3 /* MAS3 */
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tlbwe
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2013-02-04 13:38:36 +00:00
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blr
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2013-02-04 14:47:02 +00:00
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#endif /* !defined(__DOXYGEN__) */
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2013-02-04 13:38:36 +00:00
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/** @} */
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