2012-11-19 08:42:07 +00:00
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/*
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2012-11-27 10:14:29 +00:00
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* Licensed under ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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2012-11-19 08:42:07 +00:00
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/**
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* @file SPC560BCxx/hal_lld.h
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* @brief SPC560B/Cxx HAL subsystem low level driver header.
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* @pre This module requires the following macros to be defined in the
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* @p board.h file:
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* - SPC5_XOSC_CLK.
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* - SPC5_OSC_BYPASS (optionally).
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* .
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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2012-11-19 11:50:14 +00:00
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#include "xpc560bc.h"
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#include "spc560bc_registry.h"
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2012-11-19 08:42:07 +00:00
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Defines the support for realtime counters in the HAL.
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*/
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#define HAL_IMPLEMENTS_COUNTERS FALSE
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/**
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* @name Platform identification
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* @{
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*/
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2012-11-19 11:50:14 +00:00
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#define PLATFORM_NAME "SPC560B/Cxx Car Body and Convenience"
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2012-11-19 08:42:07 +00:00
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/** @} */
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/**
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* @name Absolute Maximum Ratings
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* @{
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*/
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/**
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* @brief Maximum XOSC clock frequency.
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*/
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2012-11-19 11:50:14 +00:00
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#define SPC5_XOSC_CLK_MAX 16000000
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2012-11-19 08:42:07 +00:00
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/**
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* @brief Minimum XOSC clock frequency.
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*/
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#define SPC5_XOSC_CLK_MIN 4000000
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2012-11-19 11:50:14 +00:00
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/**
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* @brief Maximum SXOSC clock frequency.
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*/
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#define SPC5_SXOSC_CLK_MAX 40000
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/**
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* @brief Minimum SXOSC clock frequency.
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*/
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#define SPC5_SXOSC_CLK_MIN 32000
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2012-11-19 08:42:07 +00:00
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/**
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* @brief Maximum FMPLLs input clock frequency.
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*/
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#define SPC5_FMPLLIN_MIN 4000000
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/**
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* @brief Maximum FMPLLs input clock frequency.
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*/
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2012-11-19 11:50:14 +00:00
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#define SPC5_FMPLLIN_MAX 64000000
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2012-11-19 08:42:07 +00:00
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/**
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* @brief Maximum FMPLLs VCO clock frequency.
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*/
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#define SPC5_FMPLLVCO_MAX 512000000
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/**
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* @brief Maximum FMPLLs VCO clock frequency.
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*/
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#define SPC5_FMPLLVCO_MIN 256000000
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/**
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* @brief Maximum FMPLL0 output clock frequency.
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*/
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#define SPC5_FMPLL0_CLK_MAX 64000000
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/** @} */
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/**
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* @name Internal clock sources
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* @{
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*/
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2012-11-19 11:50:14 +00:00
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#define SPC5_IRC_CLK 16000000 /**< Internal fast RC
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oscillator. */
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#define SPC5_SIRC_CLK 128000 /**< Internal RC slow
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oscillator. */
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2012-11-19 08:42:07 +00:00
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/** @} */
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/**
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* @name FMPLL_CR register bits definitions
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* @{
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*/
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#define SPC5_FMPLL_ODF_DIV2 (0U << 24)
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#define SPC5_FMPLL_ODF_DIV4 (1U << 24)
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#define SPC5_FMPLL_ODF_DIV8 (2U << 24)
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#define SPC5_FMPLL_ODF_DIV16 (3U << 24)
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/** @} */
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/**
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* @name ME_GS register bits definitions
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* @{
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*/
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#define SPC5_ME_GS_SYSCLK_MASK (15U << 0)
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#define SPC5_ME_GS_SYSCLK_IRC (0U << 0)
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2012-11-19 11:50:14 +00:00
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#define SPC5_ME_GS_SYSCLK_DIVIRC (1U << 0)
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2012-11-19 08:42:07 +00:00
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#define SPC5_ME_GS_SYSCLK_XOSC (2U << 0)
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#define SPC5_ME_GS_SYSCLK_DIVXOSC (3U << 0)
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2012-11-19 08:42:07 +00:00
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#define SPC5_ME_GS_SYSCLK_FMPLL0 (4U << 0)
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/** @} */
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/**
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* @name ME_ME register bits definitions
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* @{
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*/
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#define SPC5_ME_ME_RESET (1U << 0)
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#define SPC5_ME_ME_TEST (1U << 1)
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#define SPC5_ME_ME_SAFE (1U << 2)
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#define SPC5_ME_ME_DRUN (1U << 3)
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#define SPC5_ME_ME_RUN0 (1U << 4)
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#define SPC5_ME_ME_RUN1 (1U << 5)
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#define SPC5_ME_ME_RUN2 (1U << 6)
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#define SPC5_ME_ME_RUN3 (1U << 7)
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#define SPC5_ME_ME_HALT0 (1U << 8)
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#define SPC5_ME_ME_STOP0 (1U << 10)
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#define SPC5_ME_ME_STANDBY0 (1U << 13)
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2012-11-19 08:42:07 +00:00
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/** @} */
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/**
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* @name ME_xxx_MC registers bits definitions
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* @{
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*/
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#define SPC5_ME_MC_SYSCLK_MASK (15U << 0)
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#define SPC5_ME_MC_SYSCLK(n) ((n) << 0)
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2012-11-19 11:50:14 +00:00
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#define SPC5_ME_MC_SYSCLK_IRC SPC5_ME_MC_SYSCLK(0)
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#define SPC5_ME_MC_SYSCLK_DIVIRC SPC5_ME_MC_SYSCLK(1)
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#define SPC5_ME_MC_SYSCLK_XOSC SPC5_ME_MC_SYSCLK(2)
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#define SPC5_ME_MC_SYSCLK_DIVXOSC SPC5_ME_MC_SYSCLK(3)
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#define SPC5_ME_MC_SYSCLK_FMPLL0 SPC5_ME_MC_SYSCLK(4)
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#define SPC5_ME_MC_SYSCLK_DISABLED SPC5_ME_MC_SYSCLK(15)
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#define SPC5_ME_MC_IRCON (1U << 4)
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#define SPC5_ME_MC_XOSC0ON (1U << 5)
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#define SPC5_ME_MC_PLL0ON (1U << 6)
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#define SPC5_ME_MC_CFLAON_MASK (3U << 16)
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#define SPC5_ME_MC_CFLAON(n) ((n) << 16)
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#define SPC5_ME_MC_CFLAON_PD (1U << 16)
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#define SPC5_ME_MC_CFLAON_LP (2U << 16)
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#define SPC5_ME_MC_CFLAON_NORMAL (3U << 16)
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#define SPC5_ME_MC_DFLAON_MASK (3U << 18)
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#define SPC5_ME_MC_DFLAON(n) ((n) << 18)
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#define SPC5_ME_MC_DFLAON_PD (1U << 18)
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#define SPC5_ME_MC_DFLAON_LP (2U << 18)
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#define SPC5_ME_MC_DFLAON_NORMAL (3U << 18)
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#define SPC5_ME_MC_MVRON (1U << 20)
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#define SPC5_ME_MC_PDO (1U << 23)
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/** @} */
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/**
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* @name ME_MCTL register bits definitions
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* @{
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*/
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#define SPC5_ME_MCTL_KEY 0x5AF0U
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#define SPC5_ME_MCTL_KEY_INV 0xA50FU
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#define SPC5_ME_MCTL_MODE_MASK (15U << 28)
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#define SPC5_ME_MCTL_MODE(n) ((n) << 28)
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/** @} */
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/**
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* @name ME_RUN_PCx registers bits definitions
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* @{
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*/
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#define SPC5_ME_RUN_PC_TEST (1U << 1)
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#define SPC5_ME_RUN_PC_SAFE (1U << 2)
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#define SPC5_ME_RUN_PC_DRUN (1U << 3)
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#define SPC5_ME_RUN_PC_RUN0 (1U << 4)
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#define SPC5_ME_RUN_PC_RUN1 (1U << 5)
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#define SPC5_ME_RUN_PC_RUN2 (1U << 6)
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#define SPC5_ME_RUN_PC_RUN3 (1U << 7)
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/** @} */
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/**
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* @name ME_LP_PCx registers bits definitions
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* @{
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*/
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#define SPC5_ME_LP_PC_HALT0 (1U << 8)
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#define SPC5_ME_LP_PC_STOP0 (1U << 10)
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#define SPC5_ME_LP_PC_STANDBY0 (1U << 10)
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/** @} */
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/**
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* @name ME_PCTL registers bits definitions
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* @{
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*/
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#define SPC5_ME_PCTL_RUN_MASK (7U << 0)
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#define SPC5_ME_PCTL_RUN(n) ((n) << 0)
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#define SPC5_ME_PCTL_LP_MASK (7U << 3)
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#define SPC5_ME_PCTL_LP(n) ((n) << 3)
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#define SPC5_ME_PCTL_DBG (1U << 6)
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief Disables the clocks initialization in the HAL.
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*/
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#if !defined(SPC5_NO_INIT) || defined(__DOXYGEN__)
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#define SPC5_NO_INIT FALSE
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#endif
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/**
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* @brief Disables the overclock checks.
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*/
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#if !defined(SPC5_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
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#define SPC5_ALLOW_OVERCLOCK FALSE
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#endif
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/**
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2012-11-19 11:50:14 +00:00
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* @brief XOSC divider value.
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* @note The allowed range is 1...32.
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*/
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2012-11-19 11:50:14 +00:00
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#if !defined(SPC5_XOSCDIV_VALUE) || defined(__DOXYGEN__)
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#define SPC5_XOSCDIV_VALUE 1
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#endif
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/**
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2012-11-19 11:50:14 +00:00
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* @brief Fast IRC divider value.
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* @note The allowed range is 1...32.
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*/
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2012-11-19 11:50:14 +00:00
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#if !defined(SPC5_IRCDIV_VALUE) || defined(__DOXYGEN__)
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#define SPC5_IRCDIV_VALUE 1
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#endif
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/**
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2012-11-19 11:50:14 +00:00
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* @brief FMPLL0 IDF divider value.
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* @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
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*/
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#if !defined(SPC5_FMPLL0_IDF_VALUE) || defined(__DOXYGEN__)
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#define SPC5_FMPLL0_IDF_VALUE 1
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#endif
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/**
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2012-11-19 11:50:14 +00:00
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* @brief FMPLL0 NDIV divider value.
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* @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
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*/
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2012-11-19 11:50:14 +00:00
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#if !defined(SPC5_FMPLL0_NDIV_VALUE) || defined(__DOXYGEN__)
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#define SPC5_FMPLL0_NDIV_VALUE 32
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#endif
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/**
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2012-11-19 11:50:14 +00:00
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* @brief FMPLL0 ODF divider value.
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* @note The default value is calculated for XOSC=8MHz and PHI=64MHz.
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*/
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2012-11-19 11:50:14 +00:00
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#if !defined(SPC5_FMPLL0_ODF) || defined(__DOXYGEN__)
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#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
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#endif
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/**
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* @brief Active run modes in ME_ME register.
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* @note Modes RESET, SAFE, DRUN, and RUN0 modes are always enabled, there
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* is no need to specify them.
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*/
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#if !defined(SPC5_ME_ME_BITS) || defined(__DOXYGEN__)
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#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \
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SPC5_ME_ME_RUN2 | \
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SPC5_ME_ME_RUN3 | \
|
|
|
|
|
SPC5_ME_ME_HALT0 | \
|
2012-11-19 11:50:14 +00:00
|
|
|
SPC5_ME_ME_STOP0 | \
|
|
|
|
|
SPC5_ME_ME_STANDBY0)
|
2012-11-19 08:42:07 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief TEST mode settings.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_TEST_MC_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \
|
|
|
|
|
SPC5_ME_MC_IRCON | \
|
|
|
|
|
SPC5_ME_MC_XOSC0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL0ON | \
|
|
|
|
|
SPC5_ME_MC_CFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_DFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_MVRON)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief SAFE mode settings.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_SAFE_MC_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief DRUN mode settings.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_DRUN_MC_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
|
|
|
|
|
SPC5_ME_MC_IRCON | \
|
|
|
|
|
SPC5_ME_MC_XOSC0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL0ON | \
|
|
|
|
|
SPC5_ME_MC_CFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_DFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_MVRON)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief RUN0 mode settings.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_RUN0_MC_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
|
|
|
|
|
SPC5_ME_MC_IRCON | \
|
|
|
|
|
SPC5_ME_MC_XOSC0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL0ON | \
|
|
|
|
|
SPC5_ME_MC_CFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_DFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_MVRON)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief RUN1 mode settings.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_RUN1_MC_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
|
|
|
|
|
SPC5_ME_MC_IRCON | \
|
|
|
|
|
SPC5_ME_MC_XOSC0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL0ON | \
|
|
|
|
|
SPC5_ME_MC_CFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_DFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_MVRON)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief RUN2 mode settings.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_RUN2_MC_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
|
|
|
|
|
SPC5_ME_MC_IRCON | \
|
|
|
|
|
SPC5_ME_MC_XOSC0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL0ON | \
|
|
|
|
|
SPC5_ME_MC_CFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_DFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_MVRON)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief RUN3 mode settings.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_RUN3_MC_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
|
|
|
|
|
SPC5_ME_MC_IRCON | \
|
|
|
|
|
SPC5_ME_MC_XOSC0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL0ON | \
|
|
|
|
|
SPC5_ME_MC_CFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_DFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_MVRON)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief HALT0 mode settings.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_HALT0_MC_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
|
|
|
|
|
SPC5_ME_MC_IRCON | \
|
|
|
|
|
SPC5_ME_MC_XOSC0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL0ON | \
|
|
|
|
|
SPC5_ME_MC_CFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_DFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_MVRON)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief STOP0 mode settings.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_STOP0_MC_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
|
|
|
|
|
SPC5_ME_MC_IRCON | \
|
2012-11-19 11:55:16 +00:00
|
|
|
SPC5_ME_MC_XOSC0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL0ON | \
|
|
|
|
|
SPC5_ME_MC_CFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_DFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_MVRON)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief STANDBY0 mode settings.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_STANDBY0_MC_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_STANDBY0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
|
|
|
|
|
SPC5_ME_MC_IRCON | \
|
2012-11-19 08:42:07 +00:00
|
|
|
SPC5_ME_MC_XOSC0ON | \
|
|
|
|
|
SPC5_ME_MC_PLL0ON | \
|
|
|
|
|
SPC5_ME_MC_CFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_DFLAON_NORMAL | \
|
|
|
|
|
SPC5_ME_MC_MVRON)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Peripheral mode 0 (run mode).
|
|
|
|
|
* @note Do not change this setting, it is expected to be the "never run"
|
|
|
|
|
* mode.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_RUN_PC0_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_RUN_PC0_BITS 0
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Peripheral mode 1 (run mode).
|
|
|
|
|
* @note Do not change this setting, it is expected to be the "always run"
|
|
|
|
|
* mode.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_RUN_PC1_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_RUN_PC1_BITS (SPC5_ME_RUN_PC_TEST | \
|
|
|
|
|
SPC5_ME_RUN_PC_SAFE | \
|
|
|
|
|
SPC5_ME_RUN_PC_DRUN | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN0 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN1 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN2 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN3)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Peripheral mode 2 (run mode).
|
|
|
|
|
* @note Do not change this setting, it is expected to be the "only during
|
|
|
|
|
* normal run" mode.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_RUN_PC2_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_RUN_PC2_BITS (SPC5_ME_RUN_PC_DRUN | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN0 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN1 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN2 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN3)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Peripheral mode 3 (run mode).
|
|
|
|
|
* @note Not defined, available to application-specific modes.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_RUN_PC3_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN1 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN2 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN3)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Peripheral mode 4 (run mode).
|
|
|
|
|
* @note Not defined, available to application-specific modes.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_RUN_PC4_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN1 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN2 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN3)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Peripheral mode 5 (run mode).
|
|
|
|
|
* @note Not defined, available to application-specific modes.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_RUN_PC5_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN1 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN2 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN3)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Peripheral mode 6 (run mode).
|
|
|
|
|
* @note Not defined, available to application-specific modes.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_RUN_PC6_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN1 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN2 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN3)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Peripheral mode 7 (run mode).
|
|
|
|
|
* @note Not defined, available to application-specific modes.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_RUN_PC7_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN1 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN2 | \
|
|
|
|
|
SPC5_ME_RUN_PC_RUN3)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Peripheral mode 0 (low power mode).
|
|
|
|
|
* @note Do not change this setting, it is expected to be the "never run"
|
|
|
|
|
* mode.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_LP_PC0_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_LP_PC0_BITS 0
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Peripheral mode 1 (low power mode).
|
|
|
|
|
* @note Do not change this setting, it is expected to be the "always run"
|
|
|
|
|
* mode.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_LP_PC1_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_LP_PC1_BITS (SPC5_ME_LP_PC_HALT0 | \
|
2012-11-19 11:50:14 +00:00
|
|
|
SPC5_ME_LP_PC_STOP0 | \
|
|
|
|
|
SPC5_ME_LP_PC_STANDBY0)
|
2012-11-19 08:42:07 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Peripheral mode 2 (low power mode).
|
|
|
|
|
* @note Do not change this setting, it is expected to be the "halt only"
|
|
|
|
|
* mode.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_LP_PC2_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_LP_PC2_BITS (SPC5_ME_LP_PC_HALT0)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Peripheral mode 3 (low power mode).
|
|
|
|
|
* @note Do not change this setting, it is expected to be the "stop only"
|
|
|
|
|
* mode.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_LP_PC3_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_LP_PC3_BITS (SPC5_ME_LP_PC_STOP0)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Peripheral mode 4 (low power mode).
|
|
|
|
|
* @note Not defined, available to application-specific modes.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_LP_PC4_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
|
|
|
|
|
SPC5_ME_LP_PC_STOP0)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Peripheral mode 5 (low power mode).
|
|
|
|
|
* @note Not defined, available to application-specific modes.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_LP_PC5_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
|
|
|
|
|
SPC5_ME_LP_PC_STOP0)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Peripheral mode 6 (low power mode).
|
|
|
|
|
* @note Not defined, available to application-specific modes.
|
|
|
|
|
*/
|
|
|
|
|
#if !defined(SPC5_ME_LP_PC6_BITS) || defined(__DOXYGEN__)
|
|
|
|
|
#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \
|
|
|
|
|
SPC5_ME_LP_PC_STOP0)
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief Peripheral mode 7 (low power mode).
|
|
|
|
|
* @note Not defined, available to application-specific modes.
|
|
|
|
|
*/
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#if !defined(SPC5_ME_LP_PC7_BITS) || defined(__DOXYGEN__)
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#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
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SPC5_ME_LP_PC_STOP0)
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#endif
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/**
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2012-11-19 11:50:14 +00:00
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* @brief PIT channel 0 IRQ priority.
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2012-11-19 08:42:07 +00:00
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* @note This PIT channel is allocated permanently for system tick
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* generation.
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*/
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2012-11-19 11:50:14 +00:00
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#if !defined(SPC5_PIT0_IRQ_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_PIT0_IRQ_PRIORITY 4
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2012-11-19 08:42:07 +00:00
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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2012-12-11 10:27:10 +00:00
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/*
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* Configuration-related checks.
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*/
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#if !defined(SPC560BCxx_MCUCONF)
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#error "Using a wrong mcuconf.h file, SPC560BCxx_MCUCONF not defined"
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#endif
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2012-11-19 08:42:07 +00:00
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/* Check on the XOSC frequency.*/
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#if (SPC5_XOSC_CLK < SPC5_XOSC_CLK_MIN) || \
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(SPC5_XOSC_CLK > SPC5_XOSC_CLK_MAX)
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#error "invalid SPC5_XOSC_CLK value specified"
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#endif
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2012-11-19 11:50:14 +00:00
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/* Check on the XOSC divider.*/
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#if (SPC5_XOSCDIV_VALUE < 1) || (SPC5_XOSCDIV_VALUE > 32)
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#error "invalid SPC5_XOSCDIV_VALUE value specified"
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#endif
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/* Check on the IRC divider.*/
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#if (SPC5_IRCDIV_VALUE < 1) || (SPC5_IRCDIV_VALUE > 32)
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#error "invalid SPC5_IRCDIV_VALUE value specified"
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#endif
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2012-11-19 08:42:07 +00:00
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/* Check on SPC5_FMPLL0_IDF_VALUE.*/
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#if (SPC5_FMPLL0_IDF_VALUE < 1) || (SPC5_FMPLL0_IDF_VALUE > 15)
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#error "invalid SPC5_FMPLL0_IDF_VALUE value specified"
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#endif
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/* Check on SPC5_FMPLL0_NDIV_VALUE.*/
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#if (SPC5_FMPLL0_NDIV_VALUE < 32) || (SPC5_FMPLL0_NDIV_VALUE > 96)
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#error "invalid SPC5_FMPLL0_NDIV_VALUE value specified"
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#endif
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/* Check on SPC5_FMPLL0_ODF.*/
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#if (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV2)
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#define SPC5_FMPLL0_ODF_VALUE 2
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#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV4)
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#define SPC5_FMPLL0_ODF_VALUE 4
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#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV8)
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#define SPC5_FMPLL0_ODF_VALUE 8
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#elif (SPC5_FMPLL0_ODF == SPC5_FMPLL_ODF_DIV16)
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#define SPC5_FMPLL0_ODF_VALUE 16
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#else
|
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#error "invalid SPC5_FMPLL0_ODF value specified"
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#endif
|
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/**
|
|
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|
* @brief SPC5_FMPLL0_VCO_CLK clock point.
|
|
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|
*/
|
|
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|
#define SPC5_FMPLL0_VCO_CLK \
|
|
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|
|
((SPC5_XOSC_CLK / SPC5_FMPLL0_IDF_VALUE) * SPC5_FMPLL0_NDIV_VALUE)
|
|
|
|
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|
|
/* Check on FMPLL0 VCO output.*/
|
|
|
|
|
#if (SPC5_FMPLL0_VCO_CLK < SPC5_FMPLLVCO_MIN) || \
|
|
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|
|
(SPC5_FMPLL0_VCO_CLK > SPC5_FMPLLVCO_MAX)
|
|
|
|
|
#error "SPC5_FMPLL0_CLK outside acceptable range (SPC5_FMPLLVCO_MIN...SPC5_FMPLLVCO_MAX)"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* @brief SPC5_FMPLL0_CLK clock point.
|
|
|
|
|
*/
|
|
|
|
|
#define SPC5_FMPLL0_CLK \
|
|
|
|
|
(SPC5_FMPLL0_VCO_CLK / SPC5_FMPLL0_ODF_VALUE)
|
|
|
|
|
|
|
|
|
|
/* Check on SPC5_FMPLL0_CLK.*/
|
|
|
|
|
#if (SPC5_FMPLL0_CLK > SPC5_FMPLL0_CLK_MAX) && !SPC5_ALLOW_OVERCLOCK
|
|
|
|
|
#error "SPC5_FMPLL0_CLK outside acceptable range (0...SPC5_FMPLL0_CLK_MAX)"
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/*===========================================================================*/
|
|
|
|
|
/* Driver data structures and types. */
|
|
|
|
|
/*===========================================================================*/
|
|
|
|
|
|
|
|
|
|
typedef enum {
|
|
|
|
|
SPC5_RUNMODE_TEST = 1,
|
|
|
|
|
SPC5_RUNMODE_SAFE = 2,
|
|
|
|
|
SPC5_RUNMODE_DRUN = 3,
|
|
|
|
|
SPC5_RUNMODE_RUN0 = 4,
|
|
|
|
|
SPC5_RUNMODE_RUN1 = 5,
|
|
|
|
|
SPC5_RUNMODE_RUN2 = 6,
|
|
|
|
|
SPC5_RUNMODE_RUN3 = 7,
|
|
|
|
|
SPC5_RUNMODE_HALT0 = 8,
|
|
|
|
|
SPC5_RUNMODE_STOP0 = 10
|
2012-12-19 08:55:47 +00:00
|
|
|
} spc5_runmode_t;
|
2012-11-19 08:42:07 +00:00
|
|
|
|
|
|
|
|
/*===========================================================================*/
|
|
|
|
|
/* Driver macros. */
|
|
|
|
|
/*===========================================================================*/
|
|
|
|
|
|
|
|
|
|
/*===========================================================================*/
|
|
|
|
|
/* External declarations. */
|
|
|
|
|
/*===========================================================================*/
|
|
|
|
|
|
|
|
|
|
#ifdef __cplusplus
|
|
|
|
|
extern "C" {
|
|
|
|
|
#endif
|
|
|
|
|
void hal_lld_init(void);
|
2012-11-19 11:50:14 +00:00
|
|
|
void spc_clock_init(void);
|
2012-12-19 08:55:47 +00:00
|
|
|
bool_t halSPCSetRunMode(spc5_runmode_t mode);
|
2012-11-19 11:50:14 +00:00
|
|
|
void halSPCSetPeripheralClockMode(uint32_t n, uint32_t pctl);
|
2012-11-19 08:42:07 +00:00
|
|
|
#if !SPC5_NO_INIT
|
2012-11-19 11:50:14 +00:00
|
|
|
uint32_t halSPCGetSystemClock(void);
|
2012-11-19 08:42:07 +00:00
|
|
|
#endif
|
|
|
|
|
#ifdef __cplusplus
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#endif /* _HAL_LLD_H_ */
|
|
|
|
|
|
|
|
|
|
/** @} */
|
