2013-08-20 10:18:03 +00:00
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/*
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2014-07-26 09:24:53 +00:00
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ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
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2013-08-20 10:18:03 +00:00
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32F0xx/stm32_registry.h
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* @brief STM32F0xx capabilities registry.
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*
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* @addtogroup HAL
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* @{
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*/
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#ifndef _STM32_REGISTRY_H_
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#define _STM32_REGISTRY_H_
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2014-09-28 16:49:01 +00:00
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#if defined(STM32F051x8) || defined(STM32F058xx) || \
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defined(STM32F071xB) || defined(STM32F072xB) || \
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defined(STM32F078xx)
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#define STM32F0XX_MD
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#elif defined(STM32F031x6) || defined(STM32F038xx) || \
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defined(STM32F042x6) || defined(STM32F048xx)
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#define STM32F0XX_LD
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#elif defined(STM32F030x6) || defined(STM32F030x8)
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#define STM32F030
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#else
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#error "STM32F0xx device not specified"
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#endif
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#if !defined(STM32F0XX) || defined(__DOXYGEN__)
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#define STM32F0XX
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#endif
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2013-08-20 10:18:03 +00:00
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/*===========================================================================*/
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/* Platform capabilities. */
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/*===========================================================================*/
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/**
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* @name STM32F0xx capabilities
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* @{
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*/
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2014-01-02 15:11:59 +00:00
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#if defined(STM32F0XX_MD) || defined(__DOXYGEN__)
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2013-08-20 10:18:03 +00:00
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/* ADC attributes.*/
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2013-08-20 12:33:49 +00:00
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 FALSE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC4 FALSE
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2013-08-20 10:18:03 +00:00
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/* CAN attributes.*/
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2013-08-20 12:33:49 +00:00
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN2 FALSE
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2013-08-20 10:18:03 +00:00
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/* DAC attributes.*/
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2013-08-20 12:33:49 +00:00
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#define STM32_HAS_DAC TRUE
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2013-08-20 10:18:03 +00:00
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/* DMA attributes.*/
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2013-08-20 12:33:49 +00:00
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#define STM32_ADVANCED_DMA FALSE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_HAS_DMA2 FALSE
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2013-08-20 10:18:03 +00:00
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/* ETH attributes.*/
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2013-08-20 12:33:49 +00:00
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#define STM32_HAS_ETH FALSE
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2013-08-20 10:18:03 +00:00
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/* EXTI attributes.*/
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2013-08-20 12:33:49 +00:00
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#define STM32_EXTI_NUM_CHANNELS 28
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2013-08-20 10:18:03 +00:00
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/* GPIO attributes.*/
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2013-08-20 12:33:49 +00:00
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE FALSE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_GPIOI FALSE
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2014-10-02 12:06:56 +00:00
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#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
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RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | \
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RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOFEN)
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2013-08-20 10:18:03 +00:00
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/* I2C attributes.*/
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2013-08-20 12:33:49 +00:00
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_HAS_I2C2 TRUE
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_HAS_I2C3 FALSE
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2013-08-20 10:18:03 +00:00
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/* RTC attributes.*/
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2013-08-20 12:33:49 +00:00
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#define STM32_HAS_RTC TRUE
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2014-07-07 13:00:34 +00:00
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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2014-09-01 09:32:56 +00:00
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#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
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2014-07-07 13:00:34 +00:00
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#define STM32_RTC_NUM_ALARMS 1
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#define STM32_RTC_HAS_INTERRUPTS FALSE
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2013-08-20 10:18:03 +00:00
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/* SDIO attributes.*/
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2013-08-20 12:33:49 +00:00
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#define STM32_HAS_SDIO FALSE
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2013-08-20 10:18:03 +00:00
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/* SPI attributes.*/
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2013-08-20 12:33:49 +00:00
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_HAS_SPI3 FALSE
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2013-12-03 15:17:11 +00:00
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#define STM32_HAS_SPI4 FALSE
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#define STM32_HAS_SPI5 FALSE
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#define STM32_HAS_SPI6 FALSE
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2013-08-20 10:18:03 +00:00
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/* TIM attributes.*/
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2014-08-30 13:54:04 +00:00
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#define STM32_TIM_MAX_CHANNELS 4
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2013-08-20 12:33:49 +00:00
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#define STM32_HAS_TIM1 TRUE
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2013-08-20 14:49:49 +00:00
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 4
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2013-08-20 12:33:49 +00:00
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#define STM32_HAS_TIM2 TRUE
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2013-08-20 14:49:49 +00:00
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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2013-08-20 12:33:49 +00:00
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#define STM32_HAS_TIM3 TRUE
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2013-08-20 14:49:49 +00:00
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#define STM32_TIM3_IS_32BITS FALSE
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#define STM32_TIM3_CHANNELS 4
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#define STM32_HAS_TIM6 TRUE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_CHANNELS 0
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#define STM32_HAS_TIM14 TRUE
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#define STM32_TIM14_IS_32BITS FALSE
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#define STM32_TIM14_CHANNELS 1
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#define STM32_HAS_TIM15 TRUE
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#define STM32_TIM15_IS_32BITS FALSE
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#define STM32_TIM15_CHANNELS 2
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#define STM32_HAS_TIM16 TRUE
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#define STM32_TIM16_IS_32BITS FALSE
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#define STM32_TIM16_CHANNELS 2
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#define STM32_HAS_TIM17 TRUE
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#define STM32_TIM17_IS_32BITS FALSE
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#define STM32_TIM17_CHANNELS 2
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2013-08-20 12:33:49 +00:00
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#define STM32_HAS_TIM4 FALSE
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM7 FALSE
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#define STM32_HAS_TIM8 FALSE
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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2013-08-20 10:18:03 +00:00
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/* USART attributes.*/
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2013-08-20 12:33:49 +00:00
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#define STM32_HAS_USART1 TRUE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_HAS_USART2 TRUE
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_HAS_USART3 FALSE
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#define STM32_HAS_UART4 FALSE
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#define STM32_HAS_UART5 FALSE
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#define STM32_HAS_USART6 FALSE
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2013-08-20 10:18:03 +00:00
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/* USB attributes.*/
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2014-11-16 10:30:27 +00:00
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#define STM32_HAS_USB FALSE
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2013-08-20 12:33:49 +00:00
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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2014-01-02 15:11:59 +00:00
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#elif defined(STM32F0XX_LD)
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 FALSE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC4 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN2 FALSE
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/* DAC attributes.*/
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#define STM32_HAS_DAC FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA FALSE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_HAS_DMA2 FALSE
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_NUM_CHANNELS 28
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD FALSE
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#define STM32_HAS_GPIOE FALSE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_GPIOI FALSE
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2014-10-02 12:06:56 +00:00
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#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
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RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | \
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RCC_AHBENR_GPIOFEN)
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2014-01-02 15:11:59 +00:00
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_HAS_I2C2 FALSE
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#define STM32_HAS_I2C3 FALSE
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
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2014-07-07 13:00:34 +00:00
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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2014-09-01 12:15:23 +00:00
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#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
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2014-07-07 13:00:34 +00:00
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#define STM32_RTC_NUM_ALARMS 1
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#define STM32_RTC_HAS_INTERRUPTS FALSE
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2014-01-02 15:11:59 +00:00
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/* SDIO attributes.*/
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#define STM32_HAS_SDIO FALSE
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_HAS_SPI2 FALSE
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#define STM32_HAS_SPI3 FALSE
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#define STM32_HAS_SPI4 FALSE
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#define STM32_HAS_SPI5 FALSE
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#define STM32_HAS_SPI6 FALSE
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/* TIM attributes.*/
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2014-08-30 13:54:04 +00:00
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#define STM32_TIM_MAX_CHANNELS 4
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2014-01-02 15:11:59 +00:00
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 4
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#define STM32_HAS_TIM2 TRUE
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#define STM32_TIM2_IS_32BITS TRUE
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#define STM32_TIM2_CHANNELS 4
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#define STM32_HAS_TIM3 TRUE
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#define STM32_TIM3_IS_32BITS FALSE
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#define STM32_TIM3_CHANNELS 4
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#define STM32_HAS_TIM14 TRUE
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#define STM32_TIM14_IS_32BITS FALSE
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#define STM32_TIM14_CHANNELS 1
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#define STM32_HAS_TIM16 TRUE
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#define STM32_TIM16_IS_32BITS FALSE
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#define STM32_TIM16_CHANNELS 2
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#define STM32_HAS_TIM17 TRUE
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#define STM32_TIM17_IS_32BITS FALSE
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#define STM32_TIM17_CHANNELS 2
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#define STM32_HAS_TIM4 FALSE
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM6 FALSE
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#define STM32_HAS_TIM7 FALSE
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#define STM32_HAS_TIM8 FALSE
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM15 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_HAS_USART2 FALSE
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#define STM32_HAS_USART3 FALSE
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#define STM32_HAS_UART4 FALSE
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#define STM32_HAS_UART5 FALSE
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#define STM32_HAS_USART6 FALSE
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/* USB attributes.*/
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#define STM32_HAS_USB FALSE
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#define STM32_HAS_OTG1 FALSE
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#define STM32_HAS_OTG2 FALSE
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#else /* STM32F030 */
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/* ADC attributes.*/
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#define STM32_HAS_ADC1 TRUE
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#define STM32_HAS_ADC2 FALSE
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#define STM32_HAS_ADC3 FALSE
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#define STM32_HAS_ADC4 FALSE
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/* CAN attributes.*/
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#define STM32_HAS_CAN1 FALSE
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#define STM32_HAS_CAN2 FALSE
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/* DAC attributes.*/
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#define STM32_HAS_DAC FALSE
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/* DMA attributes.*/
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#define STM32_ADVANCED_DMA FALSE
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#define STM32_HAS_DMA1 TRUE
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#define STM32_HAS_DMA2 FALSE
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/* ETH attributes.*/
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#define STM32_HAS_ETH FALSE
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/* EXTI attributes.*/
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#define STM32_EXTI_NUM_CHANNELS 28
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/* GPIO attributes.*/
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#define STM32_HAS_GPIOA TRUE
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#define STM32_HAS_GPIOB TRUE
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#define STM32_HAS_GPIOC TRUE
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#define STM32_HAS_GPIOD TRUE
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#define STM32_HAS_GPIOE FALSE
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#define STM32_HAS_GPIOF TRUE
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#define STM32_HAS_GPIOG FALSE
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#define STM32_HAS_GPIOH FALSE
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#define STM32_HAS_GPIOI FALSE
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2014-10-02 12:06:56 +00:00
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#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \
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RCC_AHBENR_GPIOBEN | \
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RCC_AHBENR_GPIOCEN | \
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RCC_AHBENR_GPIODEN | \
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RCC_AHBENR_GPIOFEN)
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2014-01-02 15:11:59 +00:00
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/* I2C attributes.*/
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#define STM32_HAS_I2C1 TRUE
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#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_HAS_I2C2 TRUE
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#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_HAS_I2C3 FALSE
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/* RTC attributes.*/
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#define STM32_HAS_RTC TRUE
|
2014-07-07 13:00:34 +00:00
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#define STM32_RTC_HAS_SUBSECONDS TRUE
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#define STM32_RTC_HAS_PERIODIC_WAKEUPS FALSE
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#define STM32_RTC_NUM_ALARMS 1
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#define STM32_RTC_HAS_INTERRUPTS FALSE
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2014-01-02 15:11:59 +00:00
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/* SDIO attributes.*/
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#define STM32_HAS_SDIO FALSE
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/* SPI attributes.*/
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#define STM32_HAS_SPI1 TRUE
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#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_HAS_SPI2 TRUE
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#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_HAS_SPI3 FALSE
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#define STM32_HAS_SPI4 FALSE
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#define STM32_HAS_SPI5 FALSE
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#define STM32_HAS_SPI6 FALSE
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/* TIM attributes.*/
|
2014-08-30 13:54:04 +00:00
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#define STM32_TIM_MAX_CHANNELS 4
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2014-01-02 15:11:59 +00:00
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#define STM32_HAS_TIM1 TRUE
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#define STM32_TIM1_IS_32BITS FALSE
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#define STM32_TIM1_CHANNELS 4
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#define STM32_HAS_TIM3 TRUE
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#define STM32_TIM3_IS_32BITS FALSE
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#define STM32_TIM3_CHANNELS 4
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#define STM32_HAS_TIM6 TRUE
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#define STM32_TIM6_IS_32BITS FALSE
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#define STM32_TIM6_CHANNELS 0
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#define STM32_HAS_TIM14 TRUE
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#define STM32_TIM14_IS_32BITS FALSE
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#define STM32_TIM14_CHANNELS 1
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#define STM32_HAS_TIM15 TRUE
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#define STM32_TIM15_IS_32BITS FALSE
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#define STM32_TIM15_CHANNELS 2
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#define STM32_HAS_TIM16 TRUE
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#define STM32_TIM16_IS_32BITS FALSE
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#define STM32_TIM16_CHANNELS 2
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#define STM32_HAS_TIM17 TRUE
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#define STM32_TIM17_IS_32BITS FALSE
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#define STM32_TIM17_CHANNELS 2
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#define STM32_HAS_TIM2 FALSE
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#define STM32_HAS_TIM4 FALSE
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#define STM32_HAS_TIM5 FALSE
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#define STM32_HAS_TIM7 FALSE
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#define STM32_HAS_TIM8 FALSE
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#define STM32_HAS_TIM9 FALSE
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#define STM32_HAS_TIM10 FALSE
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#define STM32_HAS_TIM11 FALSE
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#define STM32_HAS_TIM12 FALSE
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#define STM32_HAS_TIM13 FALSE
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#define STM32_HAS_TIM18 FALSE
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#define STM32_HAS_TIM19 FALSE
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/* USART attributes.*/
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#define STM32_HAS_USART1 TRUE
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#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
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#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
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#define STM32_HAS_USART2 TRUE
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#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
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#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
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#define STM32_HAS_USART3 FALSE
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#define STM32_HAS_UART4 FALSE
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#define STM32_HAS_UART5 FALSE
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#define STM32_HAS_USART6 FALSE
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/* USB attributes.*/
|
|
|
|
#define STM32_HAS_USB FALSE
|
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|
|
#define STM32_HAS_OTG1 FALSE
|
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|
|
#define STM32_HAS_OTG2 FALSE
|
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#endif /* STM32F030 */
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|
2013-08-20 10:18:03 +00:00
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/** @} */
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#endif /* _STM32_REGISTRY_H_ */
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/** @} */
|