462 lines
18 KiB
C
462 lines
18 KiB
C
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32F4xx/stm32_dma.h
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* @brief Enhanced-DMA helper driver header.
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* @note This file requires definitions from the ST STM32F4xx header file
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* stm32f4xx.h.
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*
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* @addtogroup STM32F4xx_DMA
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* @{
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*/
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#ifndef _STM32_DMA_H_
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#define _STM32_DMA_H_
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Total number of DMA streams.
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* @note This is the total number of streams among all the DMA units.
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*/
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#define STM32_DMA_STREAMS 16
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/**
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* @brief Mask of the ISR bits passed to the DMA callback functions.
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*/
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#define STM32_DMA_ISR_MASK 0x3D
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/**
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* @brief Returns the channel associated to the specified stream.
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*
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* @param[in] id the unique numeric stream identifier
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* @param[in] c a stream/channel association word, one channel per
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* nibble
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* @return Returns the channel associated to the stream.
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*/
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#define STM32_DMA_GETCHANNEL(id, c) (((c) >> (((id) & 7) * 4)) & 7)
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/**
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* @brief Checks if a DMA priority is within the valid range.
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* @param[in] prio DMA priority
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*
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* @retval The check result.
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* @retval FALSE invalid DMA priority.
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* @retval TRUE correct DMA priority.
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*/
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#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
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/**
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* @brief Returns an unique numeric identifier for a DMA stream.
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*
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* @param[in] dma the DMA unit number
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* @param[in] stream the stream number
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* @return An unique numeric stream identifier.
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*/
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#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 8) + (stream))
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/**
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* @brief Returns a DMA stream identifier mask.
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*
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*
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* @param[in] dma the DMA unit number
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* @param[in] stream the stream number
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* @return A DMA stream identifier mask.
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*/
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#define STM32_DMA_STREAM_ID_MSK(dma, stream) \
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(1 << STM32_DMA_STREAM_ID(dma, stream))
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/**
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* @brief Checks if a DMA stream unique identifier belongs to a mask.
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* @param[in] id the stream numeric identifier
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* @param[in] mask the stream numeric identifiers mask
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*
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* @retval The check result.
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* @retval FALSE id does not belong to the mask.
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* @retval TRUE id belongs to the mask.
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*/
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#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
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/**
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* @name DMA streams identifiers
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* @{
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*/
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/**
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* @brief Returns a pointer to a stm32_dma_stream_t structure.
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*
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* @param[in] id the stream numeric identifier
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* @return A pointer to the stm32_dma_stream_t constant structure
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* associated to the DMA stream.
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*/
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#define STM32_DMA_STREAM(id) (&_stm32_dma_streams[id])
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#define STM32_DMA1_STREAM0 STM32_DMA_STREAM(0)
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#define STM32_DMA1_STREAM1 STM32_DMA_STREAM(1)
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#define STM32_DMA1_STREAM2 STM32_DMA_STREAM(2)
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#define STM32_DMA1_STREAM3 STM32_DMA_STREAM(3)
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#define STM32_DMA1_STREAM4 STM32_DMA_STREAM(4)
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#define STM32_DMA1_STREAM5 STM32_DMA_STREAM(5)
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#define STM32_DMA1_STREAM6 STM32_DMA_STREAM(6)
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#define STM32_DMA1_STREAM7 STM32_DMA_STREAM(7)
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#define STM32_DMA2_STREAM0 STM32_DMA_STREAM(8)
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#define STM32_DMA2_STREAM1 STM32_DMA_STREAM(9)
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#define STM32_DMA2_STREAM2 STM32_DMA_STREAM(10)
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#define STM32_DMA2_STREAM3 STM32_DMA_STREAM(11)
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#define STM32_DMA2_STREAM4 STM32_DMA_STREAM(12)
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#define STM32_DMA2_STREAM5 STM32_DMA_STREAM(13)
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#define STM32_DMA2_STREAM6 STM32_DMA_STREAM(14)
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#define STM32_DMA2_STREAM7 STM32_DMA_STREAM(15)
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/** @} */
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/**
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* @name CR register constants common to all DMA types
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* @{
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*/
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#define STM32_DMA_CR_EN DMA_SxCR_EN
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#define STM32_DMA_CR_TEIE DMA_SxCR_TEIE
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#define STM32_DMA_CR_HTIE DMA_SxCR_HTIE
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#define STM32_DMA_CR_TCIE DMA_SxCR_TCIE
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#define STM32_DMA_CR_DIR_MASK DMA_SxCR_DIR
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#define STM32_DMA_CR_DIR_P2M 0
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#define STM32_DMA_CR_DIR_M2P DMA_SxCR_DIR_0
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#define STM32_DMA_CR_DIR_M2M DMA_SxCR_DIR_1
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#define STM32_DMA_CR_CIRC DMA_SxCR_CIRC
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#define STM32_DMA_CR_PINC DMA_SxCR_PINC
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#define STM32_DMA_CR_MINC DMA_SxCR_MINC
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#define STM32_DMA_CR_PSIZE_MASK DMA_SxCR_PSIZE
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#define STM32_DMA_CR_PSIZE_BYTE 0
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#define STM32_DMA_CR_PSIZE_HWORD DMA_SxCR_PSIZE_0
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#define STM32_DMA_CR_PSIZE_WORD DMA_SxCR_PSIZE_1
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#define STM32_DMA_CR_MSIZE_MASK DMA_SxCR_MSIZE
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#define STM32_DMA_CR_MSIZE_BYTE 0
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#define STM32_DMA_CR_MSIZE_HWORD DMA_SxCR_MSIZE_0
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#define STM32_DMA_CR_MSIZE_WORD DMA_SxCR_MSIZE_1
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#define STM32_DMA_CR_SIZE_MASK (STM32_DMA_CR_PSIZE_MASK | \
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STM32_DMA_CR_MSIZE_MASK)
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#define STM32_DMA_CR_PL_MASK DMA_SxCR_PL
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#define STM32_DMA_CR_PL(n) ((n) << 16)
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/** @} */
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/**
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* @name CR register constants only found in STM32F2xx/STM32F4xx
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* @{
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*/
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#define STM32_DMA_CR_DMEIE DMA_SxCR_DMEIE
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#define STM32_DMA_CR_PFCTRL DMA_SxCR_PFCTRL
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#define STM32_DMA_CR_PINCOS DMA_SxCR_PINCOS
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#define STM32_DMA_CR_DBM DMA_SxCR_DBM
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#define STM32_DMA_CR_CT DMA_SxCR_CT
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#define STM32_DMA_CR_PBURST_MASK DMA_SxCR_PBURST
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#define STM32_DMA_CR_PBURST_SINGLE 0
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#define STM32_DMA_CR_PBURST_INCR4 DMA_SxCR_PBURST_0
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#define STM32_DMA_CR_PBURST_INCR8 DMA_SxCR_PBURST_1
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#define STM32_DMA_CR_PBURST_INCR16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1)
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#define STM32_DMA_CR_MBURST_MASK DMA_SxCR_MBURST
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#define STM32_DMA_CR_MBURST_SINGLE 0
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#define STM32_DMA_CR_MBURST_INCR4 DMA_SxCR_MBURST_0
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#define STM32_DMA_CR_MBURST_INCR8 DMA_SxCR_MBURST_1
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#define STM32_DMA_CR_MBURST_INCR16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1)
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#define STM32_DMA_CR_CHSEL_MASK DMA_SxCR_CHSEL
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#define STM32_DMA_CR_CHSEL(n) ((n) << 25)
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/** @} */
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/**
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* @name FCR register constants only found in STM32F2xx/STM32F4xx
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* @{
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*/
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#define STM32_DMA_FCR_FEIE DMA_SxFCR_FEIE
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#define STM32_DMA_FCR_FS_MASK DMA_SxFCR_FS
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#define STM32_DMA_FCR_DMDIS DMA_SxFCR_DMDIS
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#define STM32_DMA_FCR_FTH_MASK DMA_SxFCR_FTH
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#define STM32_DMA_FCR_FTH_1Q 0
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#define STM32_DMA_FCR_FTH_HALF DMA_SxFCR_FTH_0
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#define STM32_DMA_FCR_FTH_3Q DMA_SxFCR_FTH_1
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#define STM32_DMA_FCR_FTH_FULL (DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1)
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/** @} */
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/**
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* @name Status flags passed to the ISR callbacks
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*/
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#define STM32_DMA_ISR_FEIF DMA_LISR_FEIF0
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#define STM32_DMA_ISR_DMEIF DMA_LISR_DMEIF0
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#define STM32_DMA_ISR_TEIF DMA_LISR_TEIF0
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#define STM32_DMA_ISR_HTIF DMA_LISR_HTIF0
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#define STM32_DMA_ISR_TCIF DMA_LISR_TCIF0
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/** @} */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief STM32 DMA stream descriptor structure.
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*/
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typedef struct {
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DMA_Stream_TypeDef *stream; /**< @brief Associated DMA stream. */
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volatile uint32_t *ifcr; /**< @brief Associated IFCR reg. */
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uint8_t ishift; /**< @brief Bits offset in xIFCR
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register. */
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uint8_t selfindex; /**< @brief Index to self in array. */
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uint8_t vector; /**< @brief Associated IRQ vector. */
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} stm32_dma_stream_t;
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/**
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* @brief STM32 DMA ISR function type.
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*
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* @param[in] p parameter for the registered function
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* @param[in] flags pre-shifted content of the xISR register, the bits
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* are aligned to bit zero
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*/
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typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/**
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* @name Macro Functions
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* @{
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*/
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/**
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* @brief Associates a peripheral data register to a DMA stream.
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* @note This function can be invoked in both ISR or thread context.
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* @pre The stream must have been allocated using @p dmaStreamAllocate().
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* @post After use the stream can be released using @p dmaStreamRelease().
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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* @param[in] addr value to be written in the PAR register
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*
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* @special
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*/
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#define dmaStreamSetPeripheral(dmastp, addr) { \
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(dmastp)->stream->PAR = (uint32_t)(addr); \
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}
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/**
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* @brief Associates a memory destination to a DMA stream.
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* @note This function can be invoked in both ISR or thread context.
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* @pre The stream must have been allocated using @p dmaStreamAllocate().
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* @post After use the stream can be released using @p dmaStreamRelease().
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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* @param[in] addr value to be written in the M0AR register
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*
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* @special
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*/
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#define dmaStreamSetMemory0(dmastp, addr) { \
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(dmastp)->stream->M0AR = (uint32_t)(addr); \
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}
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/**
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* @brief Associates an alternate memory destination to a DMA stream.
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* @note This function can be invoked in both ISR or thread context.
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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* @param[in] addr value to be written in the M1AR register
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*
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* @special
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*/
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#define dmaStreamSetMemory1(dmastp, addr) { \
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(dmastp)->stream->M1AR = (uint32_t)(addr); \
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}
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/**
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* @brief Sets the number of transfers to be performed.
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* @note This function can be invoked in both ISR or thread context.
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* @pre The stream must have been allocated using @p dmaStreamAllocate().
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* @post After use the stream can be released using @p dmaStreamRelease().
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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* @param[in] size value to be written in the CNDTR register
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*
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* @special
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*/
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#define dmaStreamSetTransactionSize(dmastp, size) { \
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(dmastp)->stream->NDTR = (uint32_t)(size); \
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}
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/**
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* @brief Returns the number of transfers to be performed.
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* @note This function can be invoked in both ISR or thread context.
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* @pre The stream must have been allocated using @p dmaStreamAllocate().
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* @post After use the stream can be released using @p dmaStreamRelease().
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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* @return The number of transfers to be performed.
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*
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* @special
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*/
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#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->stream->NDTR))
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/**
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* @brief Programs the stream mode settings.
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* @note This function can be invoked in both ISR or thread context.
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* @pre The stream must have been allocated using @p dmaStreamAllocate().
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* @post After use the stream can be released using @p dmaStreamRelease().
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
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* @param[in] mode value to be written in the CR register
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*
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* @special
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*/
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#define dmaStreamSetMode(dmastp, mode) { \
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(dmastp)->stream->CR = (uint32_t)(mode); \
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}
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/**
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* @brief Programs the stream FIFO settings.
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* @note This function can be invoked in both ISR or thread context.
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* @pre The stream must have been allocated using @p dmaStreamAllocate().
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* @post After use the stream can be released using @p dmaStreamRelease().
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*
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* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||
|
|
* @param[in] mode value to be written in the FCR register
|
||
|
|
*
|
||
|
|
* @special
|
||
|
|
*/
|
||
|
|
#define dmaStreamSetFIFO(dmastp, mode) { \
|
||
|
|
(dmastp)->stream->FCR = (uint32_t)(mode); \
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief DMA stream enable.
|
||
|
|
* @note This function can be invoked in both ISR or thread context.
|
||
|
|
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||
|
|
* @post After use the stream can be released using @p dmaStreamRelease().
|
||
|
|
*
|
||
|
|
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||
|
|
*
|
||
|
|
* @special
|
||
|
|
*/
|
||
|
|
#define dmaStreamEnable(dmastp) { \
|
||
|
|
(dmastp)->stream->CR |= STM32_DMA_CR_EN; \
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief DMA stream disable.
|
||
|
|
* @details The function disables the specified stream, waits for the disable
|
||
|
|
* operation to complete and then clears any pending interrupt.
|
||
|
|
* @note This function can be invoked in both ISR or thread context.
|
||
|
|
* @note Interrupts enabling flags are set to zero after this call, see
|
||
|
|
* bug 3607518.
|
||
|
|
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||
|
|
* @post After use the stream can be released using @p dmaStreamRelease().
|
||
|
|
*
|
||
|
|
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||
|
|
*
|
||
|
|
* @special
|
||
|
|
*/
|
||
|
|
#define dmaStreamDisable(dmastp) { \
|
||
|
|
(dmastp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \
|
||
|
|
STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE | \
|
||
|
|
STM32_DMA_CR_EN); \
|
||
|
|
while (((dmastp)->stream->CR & STM32_DMA_CR_EN) != 0) \
|
||
|
|
; \
|
||
|
|
dmaStreamClearInterrupt(dmastp); \
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief DMA stream interrupt sources clear.
|
||
|
|
* @note This function can be invoked in both ISR or thread context.
|
||
|
|
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||
|
|
* @post After use the stream can be released using @p dmaStreamRelease().
|
||
|
|
*
|
||
|
|
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||
|
|
*
|
||
|
|
* @special
|
||
|
|
*/
|
||
|
|
#define dmaStreamClearInterrupt(dmastp) { \
|
||
|
|
*(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift; \
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Starts a memory to memory operation using the specified stream.
|
||
|
|
* @note The default transfer data mode is "byte to byte" but it can be
|
||
|
|
* changed by specifying extra options in the @p mode parameter.
|
||
|
|
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||
|
|
* @post After use the stream can be released using @p dmaStreamRelease().
|
||
|
|
*
|
||
|
|
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||
|
|
* @param[in] mode value to be written in the CCR register, this value
|
||
|
|
* is implicitly ORed with:
|
||
|
|
* - @p STM32_DMA_CR_MINC
|
||
|
|
* - @p STM32_DMA_CR_PINC
|
||
|
|
* - @p STM32_DMA_CR_DIR_M2M
|
||
|
|
* - @p STM32_DMA_CR_EN
|
||
|
|
* .
|
||
|
|
* @param[in] src source address
|
||
|
|
* @param[in] dst destination address
|
||
|
|
* @param[in] n number of data units to copy
|
||
|
|
*/
|
||
|
|
#define dmaStartMemCopy(dmastp, mode, src, dst, n) { \
|
||
|
|
dmaStreamSetPeripheral(dmastp, src); \
|
||
|
|
dmaStreamSetMemory0(dmastp, dst); \
|
||
|
|
dmaStreamSetTransactionSize(dmastp, n); \
|
||
|
|
dmaStreamSetMode(dmastp, (mode) | \
|
||
|
|
STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \
|
||
|
|
STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Polled wait for DMA transfer end.
|
||
|
|
* @pre The stream must have been allocated using @p dmaStreamAllocate().
|
||
|
|
* @post After use the stream can be released using @p dmaStreamRelease().
|
||
|
|
*
|
||
|
|
* @param[in] dmastp pointer to a stm32_dma_stream_t structure
|
||
|
|
*/
|
||
|
|
#define dmaWaitCompletion(dmastp) { \
|
||
|
|
while ((dmastp)->stream->NDTR > 0) \
|
||
|
|
; \
|
||
|
|
dmaStreamDisable(dmastp); \
|
||
|
|
}
|
||
|
|
/** @} */
|
||
|
|
|
||
|
|
/*===========================================================================*/
|
||
|
|
/* External declarations. */
|
||
|
|
/*===========================================================================*/
|
||
|
|
|
||
|
|
#if !defined(__DOXYGEN__)
|
||
|
|
extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
extern "C" {
|
||
|
|
#endif
|
||
|
|
void dmaInit(void);
|
||
|
|
bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
|
||
|
|
uint32_t priority,
|
||
|
|
stm32_dmaisr_t func,
|
||
|
|
void *param);
|
||
|
|
void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* _STM32_DMA_H_ */
|
||
|
|
|
||
|
|
/** @} */
|