668 lines
21 KiB
C
668 lines
21 KiB
C
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
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2011,2012,2013 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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Concepts and parts of this file have been contributed by Uladzimir Pylinsky
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aka barthess.
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*/
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/**
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* @file STM32/I2Cv2/i2c_lld.c
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* @brief STM32 I2C subsystem low level driver source.
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*
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* @addtogroup I2C
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#if HAL_USE_I2C || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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#define I2C1_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_RX_DMA_STREAM, \
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STM32_I2C1_RX_DMA_CHN)
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#define I2C1_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_I2C_I2C1_TX_DMA_STREAM, \
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STM32_I2C1_TX_DMA_CHN)
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#define I2C2_RX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_RX_DMA_STREAM, \
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STM32_I2C2_RX_DMA_CHN)
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#define I2C2_TX_DMA_CHANNEL \
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STM32_DMA_GETCHANNEL(STM32_I2C_I2C2_TX_DMA_STREAM, \
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STM32_I2C2_TX_DMA_CHN)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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#define I2C_MASTER_TC \
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((uint32_t)(I2C_ISR_BUSY|I2C_ISR_TC))
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#define I2C_ERROR_MASK \
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((uint32_t)(I2C_ISR_BERR|I2C_ISR_ARLO|I2C_ISR_OVR|I2C_ISR_PECERR| \
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I2C_ISR_TIMEOUT|I2C_ISR_ALERT))
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#define I2C_INT_MASK \
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((uint32_t)(I2C_ISR_TCR|I2C_ISR_TC|I2C_ISR_STOPF|I2C_ISR_NACKF| \
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I2C_ISR_ADDR|I2C_ISR_RXNE|I2C_ISR_TXIS))
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief I2C1 driver identifier.*/
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#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
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I2CDriver I2CD1;
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#endif
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/** @brief I2C2 driver identifier.*/
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#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
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I2CDriver I2CD2;
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#endif
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/*===========================================================================*/
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/* Driver local variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief Wakes up the waiting thread.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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* @param[in] msg wakeup message
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*
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* @notapi
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*/
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#define wakeup_isr(i2cp, msg) { \
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chSysLockFromIsr(); \
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if ((i2cp)->thread != NULL) { \
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Thread *tp = (i2cp)->thread; \
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(i2cp)->thread = NULL; \
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tp->p_u.rdymsg = (msg); \
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chSchReadyI(tp); \
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} \
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chSysUnlockFromIsr(); \
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}
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/**
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* @brief Aborts an I2C transaction.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*
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* @notapi
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*/
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static void i2c_lld_abort_operation(I2CDriver *i2cp) {
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I2C_TypeDef *dp = i2cp->i2c;
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if (dp->CR1 & I2C_CR1_PE) {
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/* Stops the I2C peripheral.*/
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dp->CR1 &= ~I2C_CR1_PE;
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while (dp->CR1 & I2C_CR1_PE)
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dp->CR1 &= ~I2C_CR1_PE;
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dp->CR1 |= I2C_CR1_PE;
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}
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/* Stops the associated DMA streams.*/
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dmaStreamDisable(i2cp->dmatx);
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dmaStreamDisable(i2cp->dmarx);
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}
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/**
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* @brief Handling of stalled I2C transactions.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*
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* @notapi
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*/
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static void i2c_lld_safety_timeout(void *p) {
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I2CDriver *i2cp = (I2CDriver *)p;
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chSysLockFromIsr();
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if (i2cp->thread) {
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Thread *tp = i2cp->thread;
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i2c_lld_abort_operation(i2cp);
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i2cp->thread = NULL;
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tp->p_u.rdymsg = RDY_TIMEOUT;
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chSchReadyI(tp);
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}
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chSysUnlockFromIsr();
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}
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/**
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* @brief I2C shared ISR code.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*
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* @notapi
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*/
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static void i2c_lld_serve_interrupt(I2CDriver *i2cp, uint32_t status) {
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I2C_TypeDef *dp = i2cp->i2c;
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if (status & I2C_MASTER_TC) {
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uint8_t rxbytes = dmaStreamGetTransactionSize(i2cp->dmarx);
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if (rxbytes > 0) {
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/* Enable RX DMA */
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dmaStreamEnable(i2cp->dmarx);
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dp->CR2 &= ~I2C_CR2_NBYTES;
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dp->CR2 |= (uint8_t)rxbytes << 16;
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/* Starts the read operation.*/
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dp->CR2 |= I2C_CR2_RD_WRN;
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dp->CR2 |= I2C_CR2_START;
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}
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else {
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dp->CR2 |= I2C_CR2_STOP;
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wakeup_isr(i2cp, RDY_OK);
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}
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}
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}
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/**
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* @brief DMA RX end IRQ handler.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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* @param[in] flags pre-shifted content of the ISR register
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*
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* @notapi
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*/
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static void i2c_lld_serve_rx_end_irq(I2CDriver *i2cp, uint32_t flags) {
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I2C_TypeDef *dp = i2cp->i2c;
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/* DMA errors handling.*/
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#if defined(STM32_I2C_DMA_ERROR_HOOK)
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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STM32_I2C_DMA_ERROR_HOOK(i2cp);
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}
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#else
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(void)flags;
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#endif
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dmaStreamDisable(i2cp->dmarx);
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dp->CR2 |= I2C_CR2_STOP;
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wakeup_isr(i2cp, RDY_OK);
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}
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/**
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* @brief DMA TX end IRQ handler.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*
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* @notapi
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*/
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static void i2c_lld_serve_tx_end_irq(I2CDriver *i2cp, uint32_t flags) {
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/* DMA errors handling.*/
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#if defined(STM32_I2C_DMA_ERROR_HOOK)
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if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
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STM32_I2C_DMA_ERROR_HOOK(i2cp);
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}
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#else
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(void)flags;
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#endif
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dmaStreamDisable(i2cp->dmatx);
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}
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/**
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* @brief I2C error handler.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*
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* @notapi
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*/
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static void i2c_lld_serve_error_interrupt(I2CDriver *i2cp, uint32_t status) {
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i2cflags_t errors;
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/* Clears interrupt flags just to be safe.*/
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chSysLockFromIsr();
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dmaStreamDisable(i2cp->dmatx);
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dmaStreamDisable(i2cp->dmarx);
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chSysUnlockFromIsr();
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errors = I2CD_NO_ERROR;
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if (status & I2C_ISR_BERR) { /* Bus error. */
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status &= ~I2C_ISR_BERR;
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errors |= I2CD_BUS_ERROR;
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}
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if (status & I2C_ISR_ARLO) { /* Arbitration lost. */
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status &= ~I2C_ISR_ARLO;
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errors |= I2CD_ARBITRATION_LOST;
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}
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if (status & I2C_ISR_OVR) { /* Overrun. */
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status &= ~I2C_ISR_OVR;
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errors |= I2CD_OVERRUN;
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}
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if (status & I2C_ISR_PECERR) { /* PEC error. */
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status &= ~I2C_ISR_PECERR;
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errors |= I2CD_PEC_ERROR;
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}
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if (status & I2C_ISR_TIMEOUT) { /* SMBus Timeout. */
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status &= ~I2C_ISR_TIMEOUT;
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errors |= I2CD_TIMEOUT;
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}
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if (status & I2C_ISR_ALERT) { /* SMBus alert. */
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status &= ~I2C_ISR_ALERT;
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errors |= I2CD_SMB_ALERT;
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}
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/* If some error has been identified then sends wakes the waiting thread.*/
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if (errors != I2CD_NO_ERROR) {
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i2cp->errors = errors;
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wakeup_isr(i2cp, RDY_RESET);
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}
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
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/**
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* @brief I2C1 event interrupt handler.
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*
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* @notapi
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*/
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CH_IRQ_HANDLER(I2C1_IRQHandler) {
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volatile I2C_TypeDef *dp = I2CD1.i2c;
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uint32_t status = dp->ISR;
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CH_IRQ_PROLOGUE();
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if (status & I2C_ERROR_MASK)
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i2c_lld_serve_error_interrupt(&I2CD1, status);
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else if (status & I2C_INT_MASK)
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i2c_lld_serve_interrupt(&I2CD1, status);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_I2C_USE_I2C1 */
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#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
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/**
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* @brief I2C2 event interrupt handler.
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*
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* @notapi
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*/
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CH_IRQ_HANDLER(I2C2_IRQHandler) {
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volatile I2C_TypeDef *dp = I2CD2.i2c;
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uint32_t status = dp->ISR;
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CH_IRQ_PROLOGUE();
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if (status & I2C_ERROR_MASK)
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i2c_lld_serve_error_interrupt(&I2CD2, status);
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else if (status & I2C_INT_MASK)
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i2c_lld_serve_interrupt(&I2CD2, status);
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CH_IRQ_EPILOGUE();
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}
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#endif /* STM32_I2C_USE_I2C2 */
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level I2C driver initialization.
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*
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* @notapi
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*/
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void i2c_lld_init(void) {
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#if STM32_I2C_USE_I2C1
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i2cObjectInit(&I2CD1);
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I2CD1.thread = NULL;
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I2CD1.i2c = I2C1;
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I2CD1.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C1_RX_DMA_STREAM);
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I2CD1.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C1_TX_DMA_STREAM);
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#endif /* STM32_I2C_USE_I2C1 */
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#if STM32_I2C_USE_I2C2
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i2cObjectInit(&I2CD2);
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I2CD2.thread = NULL;
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I2CD2.i2c = I2C2;
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I2CD2.dmarx = STM32_DMA_STREAM(STM32_I2C_I2C2_RX_DMA_STREAM);
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I2CD2.dmatx = STM32_DMA_STREAM(STM32_I2C_I2C2_TX_DMA_STREAM);
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#endif /* STM32_I2C_USE_I2C2 */
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}
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/**
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* @brief Configures and activates the I2C peripheral.
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*
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* @param[in] i2cp pointer to the @p I2CDriver object
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*
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* @notapi
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*/
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|
|
void i2c_lld_start(I2CDriver *i2cp) {
|
||
|
|
I2C_TypeDef *dp = i2cp->i2c;
|
||
|
|
|
||
|
|
i2cp->dmamode = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE |
|
||
|
|
STM32_DMA_CR_MINC | STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE |
|
||
|
|
STM32_DMA_CR_TCIE;
|
||
|
|
|
||
|
|
/* Make sure I2C peripheral is disabled */
|
||
|
|
dp->CR1 &= ~I2C_CR1_PE;
|
||
|
|
|
||
|
|
/* If in stopped state then enables the I2C and DMA clocks.*/
|
||
|
|
if (i2cp->state == I2C_STOP) {
|
||
|
|
|
||
|
|
#if STM32_I2C_USE_I2C1
|
||
|
|
if (&I2CD1 == i2cp) {
|
||
|
|
bool_t b;
|
||
|
|
|
||
|
|
rccResetI2C1();
|
||
|
|
b = dmaStreamAllocate(i2cp->dmarx,
|
||
|
|
STM32_I2C_I2C1_IRQ_PRIORITY,
|
||
|
|
(stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
|
||
|
|
(void *)i2cp);
|
||
|
|
chDbgAssert(!b, "i2c_lld_start(), #1", "stream already allocated");
|
||
|
|
b = dmaStreamAllocate(i2cp->dmatx,
|
||
|
|
STM32_I2C_I2C1_IRQ_PRIORITY,
|
||
|
|
(stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
|
||
|
|
(void *)i2cp);
|
||
|
|
chDbgAssert(!b, "i2c_lld_start(), #2", "stream already allocated");
|
||
|
|
rccEnableI2C1(FALSE);
|
||
|
|
nvicEnableVector(I2C1_IRQn,
|
||
|
|
CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY));
|
||
|
|
|
||
|
|
i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C1_RX_DMA_CHANNEL) |
|
||
|
|
STM32_DMA_CR_PL(STM32_I2C_I2C1_DMA_PRIORITY);
|
||
|
|
}
|
||
|
|
#endif /* STM32_I2C_USE_I2C1 */
|
||
|
|
|
||
|
|
#if STM32_I2C_USE_I2C2
|
||
|
|
if (&I2CD2 == i2cp) {
|
||
|
|
bool_t b;
|
||
|
|
|
||
|
|
rccResetI2C2();
|
||
|
|
b = dmaStreamAllocate(i2cp->dmarx,
|
||
|
|
STM32_I2C_I2C2_IRQ_PRIORITY,
|
||
|
|
(stm32_dmaisr_t)i2c_lld_serve_rx_end_irq,
|
||
|
|
(void *)i2cp);
|
||
|
|
chDbgAssert(!b, "i2c_lld_start(), #3", "stream already allocated");
|
||
|
|
b = dmaStreamAllocate(i2cp->dmatx,
|
||
|
|
STM32_I2C_I2C2_IRQ_PRIORITY,
|
||
|
|
(stm32_dmaisr_t)i2c_lld_serve_tx_end_irq,
|
||
|
|
(void *)i2cp);
|
||
|
|
chDbgAssert(!b, "i2c_lld_start(), #4", "stream already allocated");
|
||
|
|
rccEnableI2C2(FALSE);
|
||
|
|
nvicEnableVector(I2C2_IRQn,
|
||
|
|
CORTEX_PRIORITY_MASK(STM32_I2C_I2C2_IRQ_PRIORITY));
|
||
|
|
|
||
|
|
i2cp->dmamode |= STM32_DMA_CR_CHSEL(I2C2_RX_DMA_CHANNEL) |
|
||
|
|
STM32_DMA_CR_PL(STM32_I2C_I2C2_DMA_PRIORITY);
|
||
|
|
}
|
||
|
|
#endif /* STM32_I2C_USE_I2C2 */
|
||
|
|
}
|
||
|
|
|
||
|
|
/* DMA streams mode preparation in advance.*/
|
||
|
|
dmaStreamSetMode(i2cp->dmatx, i2cp->dmamode | STM32_DMA_CR_DIR_M2P);
|
||
|
|
dmaStreamSetMode(i2cp->dmarx, i2cp->dmamode | STM32_DMA_CR_DIR_P2M);
|
||
|
|
|
||
|
|
/* I2C registers pointed by the DMA.*/
|
||
|
|
dmaStreamSetPeripheral(i2cp->dmarx, &dp->RXDR);
|
||
|
|
dmaStreamSetPeripheral(i2cp->dmatx, &dp->TXDR);
|
||
|
|
|
||
|
|
/* Reset i2c peripheral.*/
|
||
|
|
dp->CR1 = i2cp->config->cr1 | I2C_CR1_ERRIE | I2C_CR1_TCIE | I2C_CR1_TXDMAEN | I2C_CR1_RXDMAEN;
|
||
|
|
|
||
|
|
/* Set slave address field (master mode) */
|
||
|
|
//dp->CR2 = (i2cp->config->cr2 & ~I2C_CR2_SADD) | I2C_CR2_AUTOEND;
|
||
|
|
dp->CR2 = (i2cp->config->cr2 & ~I2C_CR2_SADD);
|
||
|
|
|
||
|
|
/* Setup I2C parameters.*/
|
||
|
|
dp->TIMINGR = i2cp->config->clock_timing;
|
||
|
|
|
||
|
|
/* Ready to go.*/
|
||
|
|
dp->CR1 |= I2C_CR1_PE;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Deactivates the I2C peripheral.
|
||
|
|
*
|
||
|
|
* @param[in] i2cp pointer to the @p I2CDriver object
|
||
|
|
*
|
||
|
|
* @notapi
|
||
|
|
*/
|
||
|
|
void i2c_lld_stop(I2CDriver *i2cp) {
|
||
|
|
|
||
|
|
/* If not in stopped state then disables the I2C clock.*/
|
||
|
|
if (i2cp->state != I2C_STOP) {
|
||
|
|
|
||
|
|
/* I2C disable.*/
|
||
|
|
i2c_lld_abort_operation(i2cp);
|
||
|
|
dmaStreamRelease(i2cp->dmatx);
|
||
|
|
dmaStreamRelease(i2cp->dmarx);
|
||
|
|
|
||
|
|
#if STM32_I2C_USE_I2C1
|
||
|
|
if (&I2CD1 == i2cp) {
|
||
|
|
nvicDisableVector(I2C1_IRQn);
|
||
|
|
rccDisableI2C1(FALSE);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if STM32_I2C_USE_I2C2
|
||
|
|
if (&I2CD2 == i2cp) {
|
||
|
|
nvicDisableVector(I2C2_IRQn);
|
||
|
|
rccDisableI2C2(FALSE);
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Receives data via the I2C bus as master.
|
||
|
|
* @details Number of receiving bytes must be more than 1 on STM32F1x. This is
|
||
|
|
* hardware restriction.
|
||
|
|
*
|
||
|
|
* @param[in] i2cp pointer to the @p I2CDriver object
|
||
|
|
* @param[in] addr slave device address
|
||
|
|
* @param[out] rxbuf pointer to the receive buffer
|
||
|
|
* @param[in] rxbytes number of bytes to be received
|
||
|
|
* @param[in] timeout the number of ticks before the operation timeouts,
|
||
|
|
* the following special values are allowed:
|
||
|
|
* - @a TIME_INFINITE no timeout.
|
||
|
|
* .
|
||
|
|
* @return The operation status.
|
||
|
|
* @retval RDY_OK if the function succeeded.
|
||
|
|
* @retval RDY_RESET if one or more I2C errors occurred, the errors can
|
||
|
|
* be retrieved using @p i2cGetErrors().
|
||
|
|
* @retval RDY_TIMEOUT if a timeout occurred before operation end. <b>After a
|
||
|
|
* timeout the driver must be stopped and restarted
|
||
|
|
* because the bus is in an uncertain state</b>.
|
||
|
|
*
|
||
|
|
* @notapi
|
||
|
|
*/
|
||
|
|
msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
|
||
|
|
uint8_t *rxbuf, size_t rxbytes,
|
||
|
|
systime_t timeout) {
|
||
|
|
I2C_TypeDef *dp = i2cp->i2c;
|
||
|
|
VirtualTimer vt;
|
||
|
|
uint32_t addr_cr2 = addr & I2C_CR2_SADD;
|
||
|
|
|
||
|
|
#if defined(STM32F0XX_I2C)
|
||
|
|
chDbgCheck((rxbytes > 1), "i2c_lld_master_receive_timeout");
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Global timeout for the whole operation.*/
|
||
|
|
if (timeout != TIME_INFINITE)
|
||
|
|
chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp);
|
||
|
|
|
||
|
|
/* Releases the lock from high level driver.*/
|
||
|
|
chSysUnlock();
|
||
|
|
|
||
|
|
/* Adjust slave address (master mode) for 7-bit address mode */
|
||
|
|
if ((i2cp->config->cr2 & I2C_CR2_ADD10) == 0)
|
||
|
|
addr_cr2 = (addr_cr2 & 0x7f) << 1;
|
||
|
|
|
||
|
|
/* Set slave address field (master mode) */
|
||
|
|
dp->CR2 &= ~(I2C_CR2_SADD | I2C_CR2_NBYTES);
|
||
|
|
dp->CR2 |= ((uint8_t)rxbytes << 16) | addr_cr2;
|
||
|
|
|
||
|
|
/* Initializes driver fields */
|
||
|
|
i2cp->errors = 0;
|
||
|
|
|
||
|
|
/* RX DMA setup.*/
|
||
|
|
dmaStreamSetMemory0(i2cp->dmarx, rxbuf);
|
||
|
|
dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes);
|
||
|
|
|
||
|
|
/* Enable RX DMA */
|
||
|
|
dmaStreamEnable(i2cp->dmarx);
|
||
|
|
|
||
|
|
/* Waits until BUSY flag is reset and the STOP from the previous operation
|
||
|
|
is completed, alternatively for a timeout condition.*/
|
||
|
|
while (dp->ISR & I2C_ISR_BUSY) {
|
||
|
|
chSysLock();
|
||
|
|
if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
|
||
|
|
return RDY_TIMEOUT;
|
||
|
|
chSysUnlock();
|
||
|
|
}
|
||
|
|
|
||
|
|
/* This lock will be released in high level driver.*/
|
||
|
|
chSysLock();
|
||
|
|
|
||
|
|
/* Atomic check on the timer in order to make sure that a timeout didn't
|
||
|
|
happen outside the critical zone.*/
|
||
|
|
if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
|
||
|
|
return RDY_TIMEOUT;
|
||
|
|
|
||
|
|
/* Starts the operation.*/
|
||
|
|
dp->CR2 |= I2C_CR2_RD_WRN;
|
||
|
|
dp->CR2 |= I2C_CR2_START;
|
||
|
|
|
||
|
|
/* Waits for the operation completion or a timeout.*/
|
||
|
|
i2cp->thread = chThdSelf();
|
||
|
|
chSchGoSleepS(THD_STATE_SUSPENDED);
|
||
|
|
if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt))
|
||
|
|
chVTResetI(&vt);
|
||
|
|
|
||
|
|
return chThdSelf()->p_u.rdymsg;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Transmits data via the I2C bus as master.
|
||
|
|
* @details Number of receiving bytes must be 0 or more than 1 on STM32F1x.
|
||
|
|
* This is hardware restriction.
|
||
|
|
*
|
||
|
|
* @param[in] i2cp pointer to the @p I2CDriver object
|
||
|
|
* @param[in] addr slave device address
|
||
|
|
* @param[in] txbuf pointer to the transmit buffer
|
||
|
|
* @param[in] txbytes number of bytes to be transmitted
|
||
|
|
* @param[out] rxbuf pointer to the receive buffer
|
||
|
|
* @param[in] rxbytes number of bytes to be received
|
||
|
|
* @param[in] timeout the number of ticks before the operation timeouts,
|
||
|
|
* the following special values are allowed:
|
||
|
|
* - @a TIME_INFINITE no timeout.
|
||
|
|
* .
|
||
|
|
* @return The operation status.
|
||
|
|
* @retval RDY_OK if the function succeeded.
|
||
|
|
* @retval RDY_RESET if one or more I2C errors occurred, the errors can
|
||
|
|
* be retrieved using @p i2cGetErrors().
|
||
|
|
* @retval RDY_TIMEOUT if a timeout occurred before operation end. <b>After a
|
||
|
|
* timeout the driver must be stopped and restarted
|
||
|
|
* because the bus is in an uncertain state</b>.
|
||
|
|
*
|
||
|
|
* @notapi
|
||
|
|
*/
|
||
|
|
msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
|
||
|
|
const uint8_t *txbuf, size_t txbytes,
|
||
|
|
uint8_t *rxbuf, size_t rxbytes,
|
||
|
|
systime_t timeout) {
|
||
|
|
I2C_TypeDef *dp = i2cp->i2c;
|
||
|
|
VirtualTimer vt;
|
||
|
|
uint32_t addr_cr2 = addr & I2C_CR2_SADD;
|
||
|
|
|
||
|
|
#if defined(STM32F0XX_I2C)
|
||
|
|
chDbgCheck(((rxbytes == 0) || ((rxbytes > 1) && (rxbuf != NULL))),
|
||
|
|
"i2c_lld_master_transmit_timeout");
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Global timeout for the whole operation.*/
|
||
|
|
if (timeout != TIME_INFINITE)
|
||
|
|
chVTSetI(&vt, timeout, i2c_lld_safety_timeout, (void *)i2cp);
|
||
|
|
|
||
|
|
/* Releases the lock from high level driver.*/
|
||
|
|
chSysUnlock();
|
||
|
|
|
||
|
|
/* Adjust slave address (master mode) for 7-bit address mode */
|
||
|
|
if ((i2cp->config->cr2 & I2C_CR2_ADD10) == 0)
|
||
|
|
addr_cr2 = (addr_cr2 & 0x7f) << 1;
|
||
|
|
|
||
|
|
/* Set slave address field (master mode) */
|
||
|
|
dp->CR2 &= ~(I2C_CR2_SADD | I2C_CR2_NBYTES);
|
||
|
|
dp->CR2 |= ((uint8_t)txbytes << 16) | addr_cr2;
|
||
|
|
|
||
|
|
/* Initializes driver fields */
|
||
|
|
i2cp->errors = 0;
|
||
|
|
|
||
|
|
/* TX DMA setup.*/
|
||
|
|
dmaStreamSetMemory0(i2cp->dmatx, txbuf);
|
||
|
|
dmaStreamSetTransactionSize(i2cp->dmatx, txbytes);
|
||
|
|
|
||
|
|
/* RX DMA setup.*/
|
||
|
|
dmaStreamSetMemory0(i2cp->dmarx, rxbuf);
|
||
|
|
dmaStreamSetTransactionSize(i2cp->dmarx, rxbytes);
|
||
|
|
|
||
|
|
/* Enable TX DMA */
|
||
|
|
dmaStreamEnable(i2cp->dmatx);
|
||
|
|
|
||
|
|
/* Waits until BUSY flag is reset and the STOP from the previous operation
|
||
|
|
is completed, alternatively for a timeout condition.*/
|
||
|
|
while (dp->ISR & I2C_ISR_BUSY) {
|
||
|
|
chSysLock();
|
||
|
|
if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
|
||
|
|
return RDY_TIMEOUT;
|
||
|
|
chSysUnlock();
|
||
|
|
}
|
||
|
|
|
||
|
|
/* This lock will be released in high level driver.*/
|
||
|
|
chSysLock();
|
||
|
|
|
||
|
|
/* Atomic check on the timer in order to make sure that a timeout didn't
|
||
|
|
happen outside the critical zone.*/
|
||
|
|
if ((timeout != TIME_INFINITE) && !chVTIsArmedI(&vt))
|
||
|
|
return RDY_TIMEOUT;
|
||
|
|
|
||
|
|
/* Starts the operation.*/
|
||
|
|
dp->CR2 &= ~I2C_CR2_RD_WRN;
|
||
|
|
dp->CR2 |= I2C_CR2_START;
|
||
|
|
|
||
|
|
/* Waits for the operation completion or a timeout.*/
|
||
|
|
i2cp->thread = chThdSelf();
|
||
|
|
chSchGoSleepS(THD_STATE_SUSPENDED);
|
||
|
|
if ((timeout != TIME_INFINITE) && chVTIsArmedI(&vt))
|
||
|
|
chVTResetI(&vt);
|
||
|
|
|
||
|
|
return chThdSelf()->p_u.rdymsg;
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* HAL_USE_I2C */
|
||
|
|
|
||
|
|
/** @} */
|