421 lines
12 KiB
C
421 lines
12 KiB
C
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/*
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SPC5 HAL - Copyright (C) 2013 STMicroelectronics
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file eMIOS_v1/pwm_lld.h
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* @brief SPC5xx low level PWM driver header.
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*
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* @addtogroup PWM
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* @{
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*/
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#ifndef _PWM_LLD_H_
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#define _PWM_LLD_H_
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#if HAL_USE_PWM || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Number of PWM channels per PWM driver.
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*/
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#define PWM_CHANNELS 7
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/**
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* @brief Edge-Aligned PWM functional mode.
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* @note This is an SPC5-specific setting.
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*/
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#define PWM_ALIGN_EDGE 0x00
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/**
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* @brief Center-Aligned PWM functional mode.
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* @note This is an SPC5-specific setting.
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*/
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#define PWM_ALIGN_CENTER 0x01
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @name Configuration options
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* @{
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*/
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#if SPC5_HAS_EMIOS0 || defined(__DOXYGEN__)
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/**
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* @brief PWMD1 driver enable switch.
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* @details If set to @p TRUE the support for PWMD1 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(SPC5_PWM_USE_EMIOS0_GROUP0) || defined(__DOXYGEN__)
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#define SPC5_PWM_USE_EMIOS0__GROUP0 FALSE
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#endif
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/**
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* @brief PWMD2 driver enable switch.
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* @details If set to @p TRUE the support for PWMD2 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(SPC5_PWM_USE_EMIOS0_GROUP1) || defined(__DOXYGEN__)
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#define SPC5_PWM_USE_EMIOS0_GROUP1 FALSE
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#endif
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/**
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* @brief PWMD1 interrupt priority level setting.
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*/
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#if !defined(SPC5_EMIOS0_GFR_F8F9_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_EMIOS0_GFR_F8F9_PRIORITY 7
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#endif
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/**
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* @brief PWMD1 interrupt priority level setting.
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*/
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#if !defined(SPC5_EMIOS0_GFR_F10F11_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_EMIOS0_GFR_F10F11_PRIORITY 7
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#endif
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/**
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* @brief PWMD1 interrupt priority level setting.
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*/
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#if !defined(SPC5_EMIOS0_GFR_F12F13_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_EMIOS0_GFR_F12F13_PRIORITY 7
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#endif
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/**
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* @brief PWMD1 interrupt priority level setting.
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*/
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#if !defined(SPC5_EMIOS0_GFR_F14F15_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_EMIOS0_GFR_F14F15_PRIORITY 7
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#endif
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/**
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* @brief PWMD2 interrupt priority level setting.
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*/
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#if !defined(SPC5_EMIOS0_GFR_F16F17_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_EMIOS0_GFR_F16F17_PRIORITY 7
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#endif
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/**
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* @brief PWMD2 interrupt priority level setting.
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*/
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#if !defined(SPC5_EMIOS0_GFR_F18F19_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_EMIOS0_GFR_F18F19_PRIORITY 7
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#endif
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/**
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* @brief PWMD2 interrupt priority level setting.
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*/
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#if !defined(SPC5_EMIOS0_GFR_F20F21_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_EMIOS0_GFR_F20F21_PRIORITY 7
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#endif
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/**
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* @brief PWMD2 interrupt priority level setting.
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*/
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#if !defined(SPC5_EMIOS0_GFR_F22F23_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_EMIOS0_GFR_F22F23_PRIORITY 7
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#endif
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#endif
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#if SPC5_HAS_EMIOS1 || defined(__DOXYGEN__)
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/**
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* @brief PWMD3 driver enable switch.
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* @details If set to @p TRUE the support for PWMD3 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(SPC5_PWM_USE_EMIOS1_GROUP0) || defined(__DOXYGEN__)
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#define SPC5_PWM_USE_EMIOS1_GROUP0 FALSE
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#endif
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/**
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* @brief PWMD4 driver enable switch.
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* @details If set to @p TRUE the support for PWMD4 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(SPC5_PWM_USE_EMIOS1_GROUP1) || defined(__DOXYGEN__)
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#define SPC5_PWM_USE_EMIOS1_GROUP1 FALSE
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#endif
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/**
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* @brief PWMD5 driver enable switch.
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* @details If set to @p TRUE the support for PWMD5 is included.
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* @note The default is @p FALSE.
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*/
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#if !defined(SPC5_PWM_USE_EMIOS1_GROUP2) || defined(__DOXYGEN__)
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#define SPC5_PWM_USE_EMIOS1_GROUP2 FALSE
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#endif
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/**
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* @brief PWMD3 interrupt priority level setting.
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*/
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#if !defined(SPC5_EMIOS1_GFR_F0F1_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_EMIOS1_GFR_F0F1_PRIORITY 7
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#endif
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/**
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* @brief PWMD3 interrupt priority level setting.
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*/
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#if !defined(SPC5_EMIOS1_GFR_F2F3_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_EMIOS1_GFR_F2F3_PRIORITY 7
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#endif
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/**
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* @brief PWMD3 interrupt priority level setting.
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*/
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#if !defined(SPC5_EMIOS1_GFR_F4F5_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_EMIOS1_GFR_F4F5_PRIORITY 7
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#endif
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/**
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* @brief PWMD3 interrupt priority level setting.
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*/
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#if !defined(SPC5_EMIOS1_GFR_F6F7_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_EMIOS1_GFR_F6F7_PRIORITY 7
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#endif
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/**
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* @brief PWMD4 interrupt priority level setting.
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*/
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#if !defined(SPC5_EMIOS1_GFR_F8F9_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_EMIOS1_GFR_F8F9_PRIORITY 7
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#endif
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/**
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* @brief PWMD4 interrupt priority level setting.
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*/
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#if !defined(SPC5_EMIOS1_GFR_F10F11_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_EMIOS1_GFR_F10F11_PRIORITY 7
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#endif
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/**
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* @brief PWMD4 interrupt priority level setting.
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*/
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#if !defined(SPC5_EMIOS1_GFR_F12F13_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_EMIOS1_GFR_F12F13_PRIORITY 7
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#endif
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/**
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* @brief PWMD4 interrupt priority level setting.
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*/
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#if !defined(SPC5_EMIOS1_GFR_F14F15_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_EMIOS1_GFR_F14F15_PRIORITY 7
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#endif
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/**
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* @brief PWMD5 interrupt priority level setting.
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*/
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#if !defined(SPC5_EMIOS1_GFR_F16F17_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_EMIOS1_GFR_F16F17_PRIORITY 7
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#endif
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/**
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* @brief PWMD5 interrupt priority level setting.
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*/
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#if !defined(SPC5_EMIOS1_GFR_F18F19_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_EMIOS1_GFR_F18F19_PRIORITY 7
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#endif
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/**
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* @brief PWMD5 interrupt priority level setting.
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*/
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#if !defined(SPC5_EMIOS1_GFR_F20F21_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_EMIOS1_GFR_F20F21_PRIORITY 7
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#endif
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/**
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* @brief PWMD5 interrupt priority level setting.
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*/
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#if !defined(SPC5_EMIOS1_GFR_F22F23_PRIORITY) || defined(__DOXYGEN__)
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#define SPC5_EMIOS1_GFR_F22F23_PRIORITY 7
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#endif
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#endif
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/** @} */
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if !SPC5_HAS_EMIOS0
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#error "EMIOS0 not present in the selected device"
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#endif
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#if !SPC5_HAS_EMIOS1
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#error "EMIOS1 not present in the selected device"
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#endif
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#define SPC5_PWM_USE_EMIOS0 (SPC5_PWM_USE_EMIOS0_GROUP0 || \
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SPC5_PWM_USE_EMIOS0_GROUP1)
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#define SPC5_PWM_USE_EMIOS1 (SPC5_PWM_USE_EMIOS1_GROUP0 || \
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SPC5_PWM_USE_EMIOS1_GROUP1 || \
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SPC5_PWM_USE_EMIOS1_GROUP2)
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#if !SPC5_PWM_USE_EMIOS0 && !SPC5_PWM_USE_EMIOS1
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#error "PWM driver activated but no Channels assigned"
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief PWM mode type.
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*/
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typedef uint32_t pwmmode_t;
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/**
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* @brief PWM channel type.
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*/
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typedef uint8_t pwmchannel_t;
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/**
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* @brief PWM counter type.
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*/
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typedef uint32_t pwmcnt_t;
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/**
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* @brief PWM driver channel configuration structure.
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* @note Some architectures may not be able to support the channel mode
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* or the callback, in this case the fields are ignored.
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*/
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typedef struct {
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/**
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* @brief Channel active logic level.
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*/
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pwmmode_t mode;
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/**
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* @brief Channel callback pointer.
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* @note This callback is invoked on the channel compare event. If set to
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* @p NULL then the callback is disabled.
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*/
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pwmcallback_t callback;
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/* End of the mandatory fields.*/
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} PWMChannelConfig;
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/**
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* @brief Driver configuration structure.
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* @note Implementations may extend this structure to contain more,
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* architecture dependent, fields.
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*/
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typedef struct {
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/**
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* @brief Timer clock in Hz.
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* @note The low level can use assertions in order to catch invalid
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* frequency specifications.
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*/
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uint32_t frequency;
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/**
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* @brief PWM period in ticks.
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* @note The low level can use assertions in order to catch invalid
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* period specifications.
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*/
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pwmcnt_t period;
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/**
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* @brief Periodic callback pointer.
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* @note This callback is invoked on PWM counter reset. If set to
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* @p NULL then the callback is disabled.
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*/
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pwmcallback_t callback;
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/**
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* @brief Channels configurations.
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*/
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PWMChannelConfig channels[PWM_CHANNELS];
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/* End of the mandatory fields.*/
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/**
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* @brief PWM functional mode.
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*/
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pwmmode_t mode;
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} PWMConfig;
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/**
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* @brief Structure representing an PWM driver.
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* @note Implementations may extend this structure to contain more,
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* architecture dependent, fields.
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*/
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struct PWMDriver {
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/**
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* @brief Driver state.
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*/
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pwmstate_t state;
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/**
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* @brief Current configuration data.
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*/
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const PWMConfig *config;
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/**
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* @brief Current PWM period in ticks.
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*/
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pwmcnt_t period;
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#if defined(PWM_DRIVER_EXT_FIELDS)
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PWM_DRIVER_EXT_FIELDS
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#endif
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/* End of the mandatory fields.*/
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/**
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* @brief Pointer to the eMIOSx registers block.
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*/
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volatile struct EMIOS_tag *emiosp;
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};
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#if SPC5_PWM_USE_EMIOS0_GROUP0 && !defined(__DOXYGEN__)
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extern PWMDriver PWMD1;
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#endif
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#if SPC5_PWM_USE_EMIOS0_GROUP1 && !defined(__DOXYGEN__)
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extern PWMDriver PWMD2;
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#endif
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#if SPC5_PWM_USE_EMIOS1_GROUP0 && !defined(__DOXYGEN__)
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extern PWMDriver PWMD3;
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#endif
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#if SPC5_PWM_USE_EMIOS1_GROUP1 && !defined(__DOXYGEN__)
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extern PWMDriver PWMD4;
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#endif
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#if SPC5_PWM_USE_EMIOS1_GROUP2 && !defined(__DOXYGEN__)
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extern PWMDriver PWMD5;
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#endif
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#ifdef __cplusplus
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extern "C" {
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#endif
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void pwm_lld_init(void);
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void pwm_lld_start(PWMDriver *pwmp);
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void pwm_lld_stop(PWMDriver *pwmp);
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void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period);
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void pwm_lld_enable_channel(PWMDriver *pwmp,
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pwmchannel_t channel,
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pwmcnt_t width);
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void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
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#ifdef __cplusplus
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}
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#endif
|
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#endif /* HAL_USE_PWM */
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#endif /* _PWM_LLD_H_ */
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/** @} */
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