2013-03-25 10:54:02 +00:00
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/*
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2013-04-11 12:23:05 +00:00
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SPC5 HAL - Copyright (C) 2013 STMicroelectronics
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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2013-03-25 10:54:02 +00:00
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/**
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* @file templates/spi_lld.c
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* @brief SPI Driver subsystem low level driver source template.
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*
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* @addtogroup SPI
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#if HAL_USE_SPI || defined(__DOXYGEN__)
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2013-03-26 15:02:45 +00:00
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/* Some forward declarations.*/
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static void spi_serve_rx_irq(edma_channel_t channel, void *p);
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static void spi_serve_dma_error_irq(edma_channel_t channel,
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void *p,
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uint32_t esr);
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2013-03-25 10:54:02 +00:00
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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2013-03-26 15:02:45 +00:00
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/* Enforced MCR bits.*/
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#define DSPI_MCR_ENFORCED_BITS (SPC5_MCR_MSTR)
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/* Excluded MCR bits.*/
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#define DSPI_MCR_EXCLUDED_BITS (SPC5_MCR_CONT_SCKE | \
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SPC5_MCR_DCONF_MASK | \
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SPC5_MCR_ROOE | \
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SPC5_MCR_MDIS | \
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SPC5_MCR_DIS_TXF | \
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SPC5_MCR_DIS_RXF | \
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SPC5_MCR_CLR_TXF | \
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SPC5_MCR_CLR_RXF | \
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SPC5_MCR_HALT)
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/* Excluded PUSHR bits.*/
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#define DSPI_PUSHR_EXCLUDED_BITS (SPC5_PUSHR_CTAS_MASK | \
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SPC5_PUSHR_EOQ | \
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SPC5_PUSHR_TXDATA_MASK)
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#define DSPI_PUSHR8_ADDRESS(spip) (((uint32_t)&(spip)->dspi->PUSHR.R) + 3)
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#define DSPI_PUSHR16_ADDRESS(spip) (((uint32_t)&(spip)->dspi->PUSHR.R) + 2)
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#define DSPI_POPR8_ADDRESS(spip) (((uint32_t)&(spip)->dspi->POPR.R) + 3)
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#define DSPI_POPR16_ADDRESS(spip) (((uint32_t)&(spip)->dspi->POPR.R) + 2)
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2013-03-25 10:54:02 +00:00
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/**
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2013-03-25 11:11:08 +00:00
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* @brief SPID1 driver identifier.
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2013-03-25 10:54:02 +00:00
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*/
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2013-03-26 15:02:45 +00:00
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#if SPC5_SPI_USE_DSPI0 || defined(__DOXYGEN__)
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2013-03-25 10:54:02 +00:00
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SPIDriver SPID1;
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#endif
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2013-03-26 15:02:45 +00:00
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/**
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* @brief SPID2 driver identifier.
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*/
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#if SPC5_SPI_USE_DSPI1 || defined(__DOXYGEN__)
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SPIDriver SPID2;
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#endif
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/**
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* @brief SPID3 driver identifier.
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*/
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#if SPC5_SPI_USE_DSPI2 || defined(__DOXYGEN__)
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SPIDriver SPID3;
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#endif
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/**
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* @brief SPID4 driver identifier.
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*/
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#if SPC5_SPI_USE_DSPI3 || defined(__DOXYGEN__)
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SPIDriver SPID4;
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#endif
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2013-03-25 10:54:02 +00:00
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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2013-03-26 15:02:45 +00:00
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#if SPC5_SPI_USE_DSPI0 || defined(__DOXYGEN__)
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/**
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* @brief DMA configuration for DSPI0 TX.
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*/
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static const edma_channel_config_t spi_dspi0_tx_dma_config = {
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SPC5_DSPI0_TX_DMA_DEV_ID, SPC5_SPI_DSPI0_DMA_PRIO, SPC5_SPI_DSPI0_DMA_PRIO,
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NULL, spi_serve_dma_error_irq, &SPID1
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};
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/**
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* @brief DMA configuration for DSPI0 RX.
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*/
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static const edma_channel_config_t spi_dspi0_rx_dma_config = {
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2013-03-28 12:09:21 +00:00
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SPC5_DSPI0_RX_DMA_DEV_ID, SPC5_SPI_DSPI0_DMA_PRIO, SPC5_SPI_DSPI0_DMA_PRIO,
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2013-03-26 15:02:45 +00:00
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spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID1
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};
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#endif /* SPC5_SPI_USE_DSPI0 */
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#if SPC5_SPI_USE_DSPI1 || defined(__DOXYGEN__)
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/**
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* @brief DMA configuration for DSPI1 TX.
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*/
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static const edma_channel_config_t spi_dspi1_tx_dma_config = {
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SPC5_DSPI1_TX_DMA_DEV_ID, SPC5_SPI_DSPI1_DMA_PRIO, SPC5_SPI_DSPI1_DMA_PRIO,
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NULL, spi_serve_dma_error_irq, &SPID2
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};
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/**
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* @brief DMA configuration for DSPI1 RX.
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*/
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static const edma_channel_config_t spi_dspi1_rx_dma_config = {
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2013-03-28 12:09:21 +00:00
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SPC5_DSPI1_RX_DMA_DEV_ID, SPC5_SPI_DSPI1_DMA_PRIO, SPC5_SPI_DSPI1_DMA_PRIO,
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2013-03-26 15:02:45 +00:00
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spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID2
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};
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#endif /* SPC5_SPI_USE_DSPI1 */
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#if SPC5_SPI_USE_DSPI2 || defined(__DOXYGEN__)
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/**
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* @brief DMA configuration for DSPI2 TX.
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*/
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static const edma_channel_config_t spi_dspi2_tx_dma_config = {
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SPC5_DSPI2_TX_DMA_DEV_ID, SPC5_SPI_DSPI2_DMA_PRIO, SPC5_SPI_DSPI2_DMA_PRIO,
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NULL, spi_serve_dma_error_irq, &SPID3
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};
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/**
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* @brief DMA configuration for DSPI2 RX.
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*/
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static const edma_channel_config_t spi_dspi2_rx_dma_config = {
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2013-03-28 12:09:21 +00:00
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SPC5_DSPI2_RX_DMA_DEV_ID, SPC5_SPI_DSPI2_DMA_PRIO, SPC5_SPI_DSPI2_DMA_PRIO,
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2013-03-26 15:02:45 +00:00
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spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID3
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};
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#endif /* SPC5_SPI_USE_DSPI2 */
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#if SPC5_SPI_USE_DSPI3 || defined(__DOXYGEN__)
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/**
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* @brief DMA configuration for DSPI3 TX.
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*/
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static const edma_channel_config_t spi_dspi3_tx_dma_config = {
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SPC5_DSPI3_TX_DMA_DEV_ID, SPC5_SPI_DSPI3_DMA_PRIO, SPC5_SPI_DSPI3_DMA_PRIO,
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NULL, spi_serve_dma_error_irq, &SPID4
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};
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/**
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* @brief DMA configuration for DSPI3 RX.
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*/
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static const edma_channel_config_t spi_dspi3_rx_dma_config = {
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2013-03-28 12:09:21 +00:00
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SPC5_DSPI3_RX_DMA_DEV_ID, SPC5_SPI_DSPI3_DMA_PRIO, SPC5_SPI_DSPI3_DMA_PRIO,
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2013-03-26 15:02:45 +00:00
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spi_serve_rx_irq, spi_serve_dma_error_irq, &SPID4
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};
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#endif /* SPC5_SPI_USE_DSPI3 */
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2013-03-25 10:54:02 +00:00
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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2013-03-27 11:54:40 +00:00
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/**
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2013-04-26 12:42:56 +00:00
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* @brief Starts reception using DMA for frames up to 8 bits.
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2013-03-27 11:54:40 +00:00
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*
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* @param[in] spip pointer to the @p SPIDriver object
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* @param[in] n number of words to be exchanged
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* @param[out] rxbuf the pointer to the receive buffer
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*
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* @notapi
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*/
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2013-03-26 15:02:45 +00:00
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static void spi_start_dma_rx8(SPIDriver *spip,
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size_t n,
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uint8_t *rxbuf) {
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edmaChannelSetup(spip->rx_channel, /* channel. */
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DSPI_POPR8_ADDRESS(spip), /* src. */
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rxbuf, /* dst. */
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0, /* soff, do not advance. */
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1, /* doff, advance by one. */
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0, /* ssize, 8 bits transfers. */
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0, /* dsize, 8 bits transfers. */
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1, /* nbytes, always one. */
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n, /* iter. */
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0, /* slast. */
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0, /* dlast. */
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EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode.*/
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2013-03-27 11:54:40 +00:00
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2013-03-26 15:02:45 +00:00
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edmaChannelStart(spip->rx_channel);
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}
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2013-03-27 11:54:40 +00:00
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/**
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* @brief Starts reception using DMA for frames up to 16 bits.
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*
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* @param[in] spip pointer to the @p SPIDriver object
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* @param[in] n number of words to be exchanged
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* @param[out] rxbuf the pointer to the receive buffer
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*
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* @notapi
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*/
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2013-03-26 15:02:45 +00:00
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static void spi_start_dma_rx16(SPIDriver *spip,
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size_t n,
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uint16_t *rxbuf) {
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edmaChannelSetup(spip->rx_channel, /* channel. */
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DSPI_POPR16_ADDRESS(spip), /* src. */
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rxbuf, /* dst. */
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0, /* soff, do not advance. */
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2, /* doff, advance by two. */
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1, /* ssize, 16 bits transfers.*/
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1, /* dsize, 16 bits transfers.*/
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2, /* nbytes, always two. */
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n, /* iter. */
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0, /* slast, no source adjust. */
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0, /* dlast. */
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EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END); /* mode.*/
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2013-03-27 11:54:40 +00:00
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2013-03-26 15:02:45 +00:00
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edmaChannelStart(spip->rx_channel);
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}
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2013-03-27 11:54:40 +00:00
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/**
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* @brief Starts transmission using DMA for frames up to 8 bits.
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*
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* @param[in] spip pointer to the @p SPIDriver object
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* @param[in] n number of words to be exchanged
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* @param[in] txbuf the pointer to the transmit buffer
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*
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* @notapi
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*/
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2013-03-26 15:02:45 +00:00
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static void spi_start_dma_tx8(SPIDriver *spip,
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size_t n,
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const uint8_t *txbuf) {
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2013-03-27 11:54:40 +00:00
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uint32_t cmd = spip->config->pushr & ~DSPI_PUSHR_EXCLUDED_BITS;
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2013-03-29 10:18:38 +00:00
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uint8_t *cp = (uint8_t *)DSPI_PUSHR8_ADDRESS(spip);
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2013-03-27 11:54:40 +00:00
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/* The first frame is pushed by the CPU, then the DMA is activated to
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send the following frames.*/
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spip->dspi->PUSHR.R = cmd | (uint32_t)*txbuf++;
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2013-03-29 10:18:38 +00:00
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*cp = 0x55;
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2013-03-27 11:54:40 +00:00
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/* Setting up TX DMA TCD parameters for 8 bits transfers.*/
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edmaChannelSetup(spip->tx_channel, /* channel. */
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txbuf, /* src. */
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DSPI_PUSHR8_ADDRESS(spip), /* dst. */
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1, /* soff, advance by 1. */
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0, /* doff, do not advance. */
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0, /* ssize, 8 bits transfers. */
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0, /* dsize, 8 bits transfers. */
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1, /* nbytes, always one. */
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n - 1, /* iter. */
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0, /* slast, no source adjust. */
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0, /* dlast, no dest.adjust. */
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EDMA_TCD_MODE_DREQ); /* mode. */
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2013-03-26 15:02:45 +00:00
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edmaChannelStart(spip->tx_channel);
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}
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2013-03-27 11:54:40 +00:00
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/**
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* @brief Starts transmission using DMA for frames up to 16 bits.
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*
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* @param[in] spip pointer to the @p SPIDriver object
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* @param[in] n number of words to be exchanged
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* @param[in] txbuf the pointer to the transmit buffer
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*
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* @notapi
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*/
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2013-03-26 15:02:45 +00:00
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static void spi_start_dma_tx16(SPIDriver *spip,
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size_t n,
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const uint16_t *txbuf) {
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2013-03-27 11:54:40 +00:00
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uint32_t cmd = spip->config->pushr & ~DSPI_PUSHR_EXCLUDED_BITS;
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/* The first frame is pushed by the CPU, then the DMA is activated to
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send the following frames.*/
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spip->dspi->PUSHR.R = cmd | (uint32_t)*txbuf++;
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/* Setting up TX DMA TCD parameters for 16 bits transfers.*/
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edmaChannelSetup(spip->tx_channel, /* channel. */
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txbuf, /* src. */
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DSPI_PUSHR16_ADDRESS(spip), /* dst. */
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2, /* soff, advance by 2. */
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0, /* doff, do not advance. */
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1, /* ssize, 16 bits transfers.*/
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1, /* dsize, 16 bits transfers.*/
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2, /* nbytes, always two. */
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n - 1, /* iter. */
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0, /* slast, no source adjust. */
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0, /* dlast, no dest.adjust. */
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EDMA_TCD_MODE_DREQ); /* mode. */
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2013-03-26 15:02:45 +00:00
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edmaChannelStart(spip->tx_channel);
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}
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2013-03-27 11:54:40 +00:00
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/**
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* @brief Starts transmission using FIFO pre-filling for frames up to 8 bits.
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*
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* @param[in] spip pointer to the @p SPIDriver object
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* @param[in] n number of words to be exchanged
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* @param[in] txbuf the pointer to the transmit buffer
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*
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* @notapi
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*/
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2013-03-26 15:02:45 +00:00
|
|
|
static void spi_tx_prefill8(SPIDriver *spip,
|
|
|
|
size_t n,
|
|
|
|
const uint8_t *txbuf) {
|
|
|
|
uint32_t cmd = spip->config->pushr & ~DSPI_PUSHR_EXCLUDED_BITS;
|
|
|
|
|
|
|
|
do {
|
|
|
|
if (--n == 0) {
|
|
|
|
spip->dspi->PUSHR.R = SPC5_PUSHR_EOQ | cmd | (uint32_t)*txbuf;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
spip->dspi->PUSHR.R = cmd | (uint32_t)*txbuf;
|
|
|
|
txbuf++;
|
|
|
|
} while (TRUE);
|
|
|
|
}
|
|
|
|
|
2013-03-27 11:54:40 +00:00
|
|
|
/**
|
|
|
|
* @brief Starts transmission using FIFO pre-filling for frames up to 16 bits.
|
|
|
|
*
|
|
|
|
* @param[in] spip pointer to the @p SPIDriver object
|
|
|
|
* @param[in] n number of words to be exchanged
|
|
|
|
* @param[in] txbuf the pointer to the transmit buffer
|
|
|
|
*
|
|
|
|
* @notapi
|
|
|
|
*/
|
2013-03-26 15:02:45 +00:00
|
|
|
static void spi_tx_prefill16(SPIDriver *spip,
|
|
|
|
size_t n,
|
|
|
|
const uint16_t *txbuf) {
|
|
|
|
uint32_t cmd = spip->config->pushr & ~DSPI_PUSHR_EXCLUDED_BITS;
|
|
|
|
|
|
|
|
do {
|
|
|
|
if (--n == 0) {
|
|
|
|
spip->dspi->PUSHR.R = SPC5_PUSHR_EOQ | cmd | (uint32_t)*txbuf;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
spip->dspi->PUSHR.R = cmd | (uint32_t)*txbuf;
|
|
|
|
txbuf++;
|
|
|
|
} while (TRUE);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void spi_serve_rx_irq(edma_channel_t channel, void *p) {
|
2013-03-27 11:54:40 +00:00
|
|
|
SPIDriver *spip = (SPIDriver *)p;
|
|
|
|
|
|
|
|
(void)channel;
|
|
|
|
|
|
|
|
/* Stops the DSPI and clears the queues.*/
|
|
|
|
spip->dspi->MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT |
|
|
|
|
SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF;
|
2013-03-26 15:02:45 +00:00
|
|
|
|
2013-03-27 11:54:40 +00:00
|
|
|
/* Portable SPI ISR code defined in the high level driver, note, it is
|
|
|
|
a macro.*/
|
|
|
|
_spi_isr_code(spip);
|
2013-03-26 15:02:45 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void spi_serve_dma_error_irq(edma_channel_t channel,
|
|
|
|
void *p,
|
|
|
|
uint32_t esr) {
|
2013-03-27 11:54:40 +00:00
|
|
|
SPIDriver *spip = (SPIDriver *)p;
|
2013-03-26 15:02:45 +00:00
|
|
|
|
2013-03-27 11:54:40 +00:00
|
|
|
(void)channel;
|
|
|
|
(void)esr;
|
|
|
|
|
|
|
|
/* Stops the DSPI and clears the queues.*/
|
|
|
|
spip->dspi->MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT |
|
|
|
|
SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF;
|
|
|
|
|
|
|
|
SPC5_SPI_DMA_ERROR_HOOK(spip);
|
2013-03-26 15:02:45 +00:00
|
|
|
}
|
|
|
|
|
2013-03-25 10:54:02 +00:00
|
|
|
/*===========================================================================*/
|
|
|
|
/* Driver interrupt handlers. */
|
|
|
|
/*===========================================================================*/
|
|
|
|
|
|
|
|
/*===========================================================================*/
|
|
|
|
/* Driver exported functions. */
|
|
|
|
/*===========================================================================*/
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Low level SPI driver initialization.
|
|
|
|
*
|
|
|
|
* @notapi
|
|
|
|
*/
|
|
|
|
void spi_lld_init(void) {
|
|
|
|
|
2013-03-26 15:02:45 +00:00
|
|
|
#if SPC5_SPI_USE_DSPI0
|
2013-03-25 10:54:02 +00:00
|
|
|
/* Driver initialization.*/
|
|
|
|
spiObjectInit(&SPID1);
|
2013-03-26 15:02:45 +00:00
|
|
|
SPID1.dspi = &SPC5_DSPI0;
|
|
|
|
SPID1.tx_channel = EDMA_ERROR;
|
|
|
|
SPID1.rx_channel = EDMA_ERROR;
|
|
|
|
#endif /* SPC5_SPI_USE_DSPI0 */
|
|
|
|
|
|
|
|
#if SPC5_SPI_USE_DSPI1
|
|
|
|
/* Driver initialization.*/
|
|
|
|
spiObjectInit(&SPID2);
|
|
|
|
SPID2.dspi = &SPC5_DSPI1;
|
|
|
|
SPID2.tx_channel = EDMA_ERROR;
|
|
|
|
SPID2.rx_channel = EDMA_ERROR;
|
|
|
|
#endif /* SPC5_SPI_USE_DSPI1 */
|
|
|
|
|
|
|
|
#if SPC5_SPI_USE_DSPI2
|
|
|
|
/* Driver initialization.*/
|
|
|
|
spiObjectInit(&SPID3);
|
|
|
|
SPID3.dspi = &SPC5_DSPI2;
|
|
|
|
SPID3.tx_channel = EDMA_ERROR;
|
|
|
|
SPID3.rx_channel = EDMA_ERROR;
|
|
|
|
#endif /* SPC5_SPI_USE_DSPI2 */
|
|
|
|
|
|
|
|
#if SPC5_SPI_USE_DSPI03
|
|
|
|
/* Driver initialization.*/
|
|
|
|
spiObjectInit(&SPID4);
|
|
|
|
SPID4.dspi = &SPC5_DSPI3;
|
|
|
|
SPID4.tx_channel = EDMA_ERROR;
|
|
|
|
SPID4.rx_channel = EDMA_ERROR;
|
|
|
|
#endif /* SPC5_SPI_USE_DSPI3 */
|
2013-03-25 10:54:02 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Configures and activates the SPI peripheral.
|
|
|
|
*
|
|
|
|
* @param[in] spip pointer to the @p SPIDriver object
|
|
|
|
*
|
|
|
|
* @notapi
|
|
|
|
*/
|
|
|
|
void spi_lld_start(SPIDriver *spip) {
|
|
|
|
|
|
|
|
if (spip->state == SPI_STOP) {
|
|
|
|
/* Enables the peripheral.*/
|
2013-03-26 15:02:45 +00:00
|
|
|
|
|
|
|
#if SPC5_SPI_USE_DSPI0
|
2013-03-25 10:54:02 +00:00
|
|
|
if (&SPID1 == spip) {
|
2013-03-26 15:02:45 +00:00
|
|
|
SPC5_DSPI0_ENABLE_CLOCK();
|
|
|
|
spip->tx_channel = edmaChannelAllocate(&spi_dspi0_tx_dma_config);
|
|
|
|
spip->rx_channel = edmaChannelAllocate(&spi_dspi0_rx_dma_config);
|
|
|
|
}
|
|
|
|
#endif /* SPC5_SPI_USE_DSPI0 */
|
|
|
|
|
|
|
|
#if SPC5_SPI_USE_DSPI1
|
|
|
|
if (&SPID2 == spip) {
|
|
|
|
SPC5_DSPI1_ENABLE_CLOCK();
|
|
|
|
spip->tx_channel = edmaChannelAllocate(&spi_dspi1_tx_dma_config);
|
|
|
|
spip->rx_channel = edmaChannelAllocate(&spi_dspi1_rx_dma_config);
|
|
|
|
}
|
|
|
|
#endif /* SPC5_SPI_USE_DSPI1 */
|
|
|
|
|
|
|
|
#if SPC5_SPI_USE_DSPI2
|
|
|
|
if (&SPID3 == spip) {
|
|
|
|
SPC5_DSPI2_ENABLE_CLOCK();
|
|
|
|
spip->tx_channel = edmaChannelAllocate(&spi_dspi2_tx_dma_config);
|
|
|
|
spip->rx_channel = edmaChannelAllocate(&spi_dspi2_rx_dma_config);
|
|
|
|
}
|
|
|
|
#endif /* SPC5_SPI_USE_DSPI2 */
|
2013-03-25 10:54:02 +00:00
|
|
|
|
2013-03-26 15:02:45 +00:00
|
|
|
#if SPC5_SPI_USE_DSPI3
|
|
|
|
if (&SPID4 == spip) {
|
|
|
|
SPC5_DSPI3_ENABLE_CLOCK();
|
|
|
|
spip->tx_channel = edmaChannelAllocate(&spi_dspi3_tx_dma_config);
|
|
|
|
spip->rx_channel = edmaChannelAllocate(&spi_dspi3_rx_dma_config);
|
2013-03-25 10:54:02 +00:00
|
|
|
}
|
2013-03-26 15:02:45 +00:00
|
|
|
#endif /* SPC5_SPI_USE_DSPI3 */
|
2013-03-28 12:09:21 +00:00
|
|
|
|
|
|
|
chDbgAssert((spip->tx_channel != EDMA_ERROR) &&
|
|
|
|
(spip->rx_channel != EDMA_ERROR),
|
|
|
|
"spi_lld_start(), #1", "channel cannot be allocated");
|
2013-03-25 10:54:02 +00:00
|
|
|
}
|
2013-03-27 11:54:40 +00:00
|
|
|
|
2013-03-25 10:54:02 +00:00
|
|
|
/* Configures the peripheral.*/
|
2013-03-27 11:54:40 +00:00
|
|
|
spip->dspi->MCR.R = SPC5_MCR_MSTR | SPC5_MCR_HALT | spip->config->mcr;
|
2013-03-26 15:02:45 +00:00
|
|
|
spip->dspi->CTAR[0].R = spip->config->ctar0;
|
2013-03-29 10:18:38 +00:00
|
|
|
spip->dspi->RSER.R = SPC5_RSER_TFFF_RE | SPC5_RSER_TFFF_DIRS |
|
|
|
|
SPC5_RSER_RFDF_RE | SPC5_RSER_RFDF_DIRS;
|
2013-03-26 15:02:45 +00:00
|
|
|
spip->dspi->SR.R = spip->dspi->SR.R;
|
2013-03-25 10:54:02 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Deactivates the SPI peripheral.
|
|
|
|
*
|
|
|
|
* @param[in] spip pointer to the @p SPIDriver object
|
|
|
|
*
|
|
|
|
* @notapi
|
|
|
|
*/
|
|
|
|
void spi_lld_stop(SPIDriver *spip) {
|
|
|
|
|
|
|
|
if (spip->state == SPI_READY) {
|
2013-03-26 15:02:45 +00:00
|
|
|
/* Releases the allocated EDMA channels.*/
|
|
|
|
edmaChannelRelease(spip->tx_channel);
|
|
|
|
edmaChannelRelease(spip->rx_channel);
|
|
|
|
|
2013-03-25 10:54:02 +00:00
|
|
|
/* Resets the peripheral.*/
|
2013-03-26 15:02:45 +00:00
|
|
|
spip->dspi->CTAR[0].R = 0;
|
|
|
|
spip->dspi->RSER.R = 0;
|
|
|
|
spip->dspi->SR.R = spip->dspi->SR.R;
|
|
|
|
spip->dspi->MCR.R = SPC5_MCR_MSTR | SPC5_MCR_MDIS |
|
2013-03-27 11:54:40 +00:00
|
|
|
SPC5_MCR_CLR_TXF | SPC5_MCR_CLR_RXF |
|
|
|
|
SPC5_MCR_HALT;
|
2013-03-25 10:54:02 +00:00
|
|
|
|
2013-03-26 15:02:45 +00:00
|
|
|
#if SPC5_SPI_USE_DSPI0
|
2013-03-25 10:54:02 +00:00
|
|
|
if (&SPID1 == spip) {
|
2013-03-26 15:02:45 +00:00
|
|
|
SPC5_DSPI0_DISABLE_CLOCK();
|
|
|
|
}
|
|
|
|
#endif /* SPC5_SPI_USE_DSPI0 */
|
|
|
|
|
|
|
|
#if SPC5_SPI_USE_DSPI1
|
|
|
|
if (&SPID2 == spip) {
|
|
|
|
SPC5_DSPI1_DISABLE_CLOCK();
|
|
|
|
}
|
|
|
|
#endif /* SPC5_SPI_USE_DSPI1 */
|
2013-03-25 10:54:02 +00:00
|
|
|
|
2013-03-26 15:02:45 +00:00
|
|
|
#if SPC5_SPI_USE_DSPI2
|
|
|
|
if (&SPID3 == spip) {
|
|
|
|
SPC5_DSPI2_DISABLE_CLOCK();
|
2013-03-25 10:54:02 +00:00
|
|
|
}
|
2013-03-26 15:02:45 +00:00
|
|
|
#endif /* SPC5_SPI_USE_DSPI2 */
|
|
|
|
|
|
|
|
#if SPC5_SPI_USE_DSPI3
|
|
|
|
if (&SPID4 == spip) {
|
|
|
|
SPC5_DSPI3_DISABLE_CLOCK();
|
|
|
|
}
|
|
|
|
#endif /* SPC5_SPI_USE_DSPI3 */
|
2013-03-25 10:54:02 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Asserts the slave select signal and prepares for transfers.
|
|
|
|
*
|
|
|
|
* @param[in] spip pointer to the @p SPIDriver object
|
|
|
|
*
|
|
|
|
* @notapi
|
|
|
|
*/
|
|
|
|
void spi_lld_select(SPIDriver *spip) {
|
|
|
|
|
|
|
|
(void)spip;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Deasserts the slave select signal.
|
|
|
|
* @details The previously selected peripheral is unselected.
|
|
|
|
*
|
|
|
|
* @param[in] spip pointer to the @p SPIDriver object
|
|
|
|
*
|
|
|
|
* @notapi
|
|
|
|
*/
|
|
|
|
void spi_lld_unselect(SPIDriver *spip) {
|
|
|
|
|
|
|
|
(void)spip;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Ignores data on the SPI bus.
|
|
|
|
* @details This asynchronous function starts the transmission of a series of
|
|
|
|
* idle words on the SPI bus and ignores the received data.
|
|
|
|
* @post At the end of the operation the configured callback is invoked.
|
|
|
|
*
|
|
|
|
* @param[in] spip pointer to the @p SPIDriver object
|
|
|
|
* @param[in] n number of words to be ignored
|
|
|
|
*
|
|
|
|
* @notapi
|
|
|
|
*/
|
|
|
|
void spi_lld_ignore(SPIDriver *spip, size_t n) {
|
|
|
|
|
|
|
|
(void)spip;
|
|
|
|
(void)n;
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Exchanges data on the SPI bus.
|
|
|
|
* @details This asynchronous function starts a simultaneous transmit/receive
|
|
|
|
* operation.
|
|
|
|
* @post At the end of the operation the configured callback is invoked.
|
|
|
|
* @note The buffers are organized as uint8_t arrays for data sizes below or
|
|
|
|
* equal to 8 bits else it is organized as uint16_t arrays.
|
|
|
|
*
|
|
|
|
* @param[in] spip pointer to the @p SPIDriver object
|
|
|
|
* @param[in] n number of words to be exchanged
|
|
|
|
* @param[in] txbuf the pointer to the transmit buffer
|
|
|
|
* @param[out] rxbuf the pointer to the receive buffer
|
|
|
|
*
|
|
|
|
* @notapi
|
|
|
|
*/
|
|
|
|
void spi_lld_exchange(SPIDriver *spip, size_t n,
|
|
|
|
const void *txbuf, void *rxbuf) {
|
|
|
|
|
2013-03-28 12:09:21 +00:00
|
|
|
/* Starting transfer.*/
|
|
|
|
spip->dspi->MCR.B.HALT = 0;
|
|
|
|
|
2013-03-26 15:02:45 +00:00
|
|
|
/* DMAs require a different setup depending on the frame size.*/
|
|
|
|
if (spip->dspi->CTAR[0].B.FMSZ < 8) {
|
|
|
|
/* Setting up the RX DMA channel.*/
|
|
|
|
spi_start_dma_rx8(spip, n, rxbuf);
|
|
|
|
|
|
|
|
if (n <= SPC5_DSPI_FIFO_DEPTH) {
|
|
|
|
/* If the total transfer size is smaller than the TX FIFO size then
|
|
|
|
the whole transmitted data is pushed here and the TX DMA is not
|
|
|
|
activated.*/
|
|
|
|
spi_tx_prefill8(spip, n, txbuf);
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
spi_start_dma_tx8(spip, n, txbuf);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
/* Setting up the RX DMA channel.*/
|
|
|
|
spi_start_dma_rx16(spip, n, rxbuf);
|
|
|
|
|
|
|
|
if (n <= SPC5_DSPI_FIFO_DEPTH) {
|
|
|
|
/* If the total transfer size is smaller than the TX FIFO size then
|
|
|
|
the whole transmitted data is pushed here and the TX DMA is not
|
|
|
|
activated.*/
|
|
|
|
spi_tx_prefill16(spip, n, txbuf);
|
|
|
|
}
|
|
|
|
else {
|
|
|
|
spi_start_dma_tx16(spip, n, txbuf);
|
|
|
|
}
|
|
|
|
}
|
2013-03-25 10:54:02 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Sends data over the SPI bus.
|
|
|
|
* @details This asynchronous function starts a transmit operation.
|
|
|
|
* @post At the end of the operation the configured callback is invoked.
|
|
|
|
* @note The buffers are organized as uint8_t arrays for data sizes below or
|
|
|
|
* equal to 8 bits else it is organized as uint16_t arrays.
|
|
|
|
*
|
|
|
|
* @param[in] spip pointer to the @p SPIDriver object
|
|
|
|
* @param[in] n number of words to send
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* @param[in] txbuf the pointer to the transmit buffer
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*
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* @notapi
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*/
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void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
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(void)spip;
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(void)n;
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(void)txbuf;
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}
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/**
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* @brief Receives data from the SPI bus.
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* @details This asynchronous function starts a receive operation.
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* @post At the end of the operation the configured callback is invoked.
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* @note The buffers are organized as uint8_t arrays for data sizes below or
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* equal to 8 bits else it is organized as uint16_t arrays.
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*
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* @param[in] spip pointer to the @p SPIDriver object
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* @param[in] n number of words to receive
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|
* @param[out] rxbuf the pointer to the receive buffer
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*
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|
* @notapi
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|
*/
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void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
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(void)spip;
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(void)n;
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(void)rxbuf;
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}
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/**
|
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|
* @brief Exchanges one frame using a polled wait.
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|
|
* @details This synchronous function exchanges one frame using a polled
|
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|
|
* synchronization method. This function is useful when exchanging
|
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|
|
* small amount of data on high speed channels, usually in this
|
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|
|
* situation is much more efficient just wait for completion using
|
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|
|
* polling than suspending the thread waiting for an interrupt.
|
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|
|
*
|
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|
|
* @param[in] spip pointer to the @p SPIDriver object
|
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|
|
* @param[in] frame the data frame to send over the SPI bus
|
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|
|
* @return The received data frame from the SPI bus.
|
|
|
|
*/
|
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|
|
uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
|
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|
|
(void)spip;
|
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|
|
(void)frame;
|
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|
return 0;
|
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|
|
}
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|
#endif /* HAL_USE_SPI */
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|
/** @} */
|