225 lines
9.5 KiB
C
225 lines
9.5 KiB
C
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file SPC563/hal_lld.h
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* @brief SPC563 HAL subsystem low level driver header.
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*
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* @addtogroup SPC563_HAL
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* @{
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*/
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#ifndef _HAL_LLD_H_
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#define _HAL_LLD_H_
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#include "mpc563m.h"
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/**
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* @brief Platform name.
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*/
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#define PLATFORM_NAME "SPC563M64"
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#define RFD_DIV2 0 /**< Divide VCO frequency by 2. */
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#define RFD_DIV4 1 /**< Divide VCO frequency by 4. */
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#define RFD_DIV8 2 /**< Divide VCO frequency by 8. */
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#define RFD_DIV16 3 /**< Divide VCO frequency by 16.*/
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/* The following settings are related to the FLASH controller, performance
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and stability depends on them, be careful.*/
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#define BIUCR_BANK1_TOO 0x01000000 /**< Use settings for bank1 too.*/
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#define BIUCR_MASTER7_PREFETCH 0x00800000 /**< Enable master 7 prefetch. */
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#define BIUCR_MASTER6_PREFETCH 0x00400000 /**< Enable master 6 prefetch. */
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#define BIUCR_MASTER5_PREFETCH 0x00200000 /**< Enable master 5 prefetch. */
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#define BIUCR_MASTER4_PREFETCH 0x00100000 /**< Enable master 4 prefetch. */
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#define BIUCR_MASTER3_PREFETCH 0x00080000 /**< Enable master 3 prefetch. */
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#define BIUCR_MASTER2_PREFETCH 0x00040000 /**< Enable master 2 prefetch. */
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#define BIUCR_MASTER1_PREFETCH 0x00020000 /**< Enable master 1 prefetch. */
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#define BIUCR_MASTER0_PREFETCH 0x00010000 /**< Enable master 0 prefetch. */
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#define BIUCR_APC_MASK 0x0000E000 /**< APC field mask. */
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#define BIUCR_APC_0 (0 << 13) /**< No additional hold cycles. */
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#define BIUCR_APC_1 (1 << 13) /**< 1 additional hold cycle. */
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#define BIUCR_APC_2 (2 << 13) /**< 2 additional hold cycles. */
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#define BIUCR_APC_3 (3 << 13) /**< 3 additional hold cycles. */
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#define BIUCR_APC_4 (4 << 13) /**< 4 additional hold cycles. */
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#define BIUCR_APC_5 (5 << 13) /**< 5 additional hold cycles. */
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#define BIUCR_APC_6 (6 << 13) /**< 6 additional hold cycles. */
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#define BIUCR_WWSC_MASK 0x00001800 /**< WWSC field mask. */
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#define BIUCR_WWSC_0 (0 << 11) /**< No write wait states. */
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#define BIUCR_WWSC_1 (1 << 11) /**< 1 write wait state. */
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#define BIUCR_WWSC_2 (2 << 11) /**< 2 write wait states. */
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#define BIUCR_WWSC_3 (3 << 11) /**< 3 write wait states. */
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#define BIUCR_RWSC_MASK 0x00001800 /**< RWSC field mask. */
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#define BIUCR_RWSC_0 (0 << 8) /**< No read wait states. */
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#define BIUCR_RWSC_1 (1 << 8) /**< 1 read wait state. */
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#define BIUCR_RWSC_2 (2 << 8) /**< 2 read wait states. */
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#define BIUCR_RWSC_3 (3 << 8) /**< 3 read wait states. */
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#define BIUCR_RWSC_4 (4 << 8) /**< 4 read wait states. */
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#define BIUCR_RWSC_5 (5 << 8) /**< 5 read wait states. */
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#define BIUCR_RWSC_6 (6 << 8) /**< 6 read wait states. */
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#define BIUCR_RWSC_7 (7 << 8) /**< 7 read wait states. */
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#define BIUCR_DPFEN 0x00000040 /**< Data prefetch enable. */
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#define BIUCR_IPFEN 0x00000010 /**< Instr. prefetch enable. */
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#define BIUCR_PFLIM_MASK 0x00000060 /**< PFLIM field mask. */
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#define BIUCR_PFLIM_NO (0 << 1) /**< No prefetching. */
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#define BIUCR_PFLIM_ON_MISS (1 << 1) /**< Prefetch on miss. */
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#define BIUCR_PFLIM_ON_HITMISS (2 << 1) /**< Prefetch on hit and miss. */
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#define BIUCR_BFEN 0x00000001 /**< Flash buffering enable. */
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/**
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* @brief Clock bypass.
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* @note If set to @p TRUE then the PLL is not started and initialized, the
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* external clock is used as-is and the other clock-related settings
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* are ignored.
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*/
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#if !defined(SPC563_CLK_BYPASS) || defined(__DOXYGEN__)
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#define SPC563_CLK_BYPASS FALSE
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#endif
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/**
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* @brief Disables the overclock checks.
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*/
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#if !defined(SPC563_ALLOW_OVERCLOCK) || defined(__DOXYGEN__)
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#define SPC563_ALLOW_OVERCLOCK FALSE
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#endif
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/**
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* @brief External clock pre-divider.
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* @note Must be in range 0...14.
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* @note The effective divider factor is this value plus one.
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*/
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#if !defined(SPC563_CLK_PREDIV) || defined(__DOXYGEN__)
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#define SPC563_CLK_PREDIV 0
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#endif
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/**
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* @brief Multiplication factor divider.
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* @note Must be in range 32...96.
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*/
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#if !defined(SPC563_CLK_MFD) || defined(__DOXYGEN__)
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#define SPC563_CLK_MFD 40
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#endif
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/**
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* @brief Reduced frequency divider.
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*/
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#if !defined(SPC563_CLK_RFD) || defined(__DOXYGEN__)
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#define SPC563_CLK_RFD RFD_DIV4
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#endif
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/**
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* @brief Flash buffer and prefetching settings.
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* @note Please refer to the SPC563M64 reference manual about the meaning
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* of the following bits, if in doubt DO NOT MODIFY IT.
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* @note Do not specify the APC, WWSC, RWSC bits in this value because
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* those are calculated from the system clock and ORed with this
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* value.
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*/
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#if !defined(SPC563_FLASH_BIUCR) || defined(__DOXYGEN__)
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#define SPC563_FLASH_BIUCR (BIUCR_BANK1_TOO | \
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BIUCR_MASTER4_PREFETCH | \
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BIUCR_MASTER0_PREFETCH | \
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BIUCR_DPFEN | \
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BIUCR_IPFEN | \
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BIUCR_PFLIM_ON_MISS | \
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BIUCR_BFEN)
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#endif
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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#if (SPC563_CLK_PREDIV < 0) || (SPC563_CLK_PREDIV > 14)
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#error "invalid SPC563_CLK_PREDIV value specified"
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#endif
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#if (SPC563_CLK_MFD < 32) || (SPC563_CLK_MFD > 96)
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#error "invalid SPC563_CLK_MFD value specified"
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#endif
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#if (SPC563_CLK_RFD != RFD_DIV2) && (SPC563_CLK_RFD != RFD_DIV4) && \
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(SPC563_CLK_RFD != RFD_DIV8) && (SPC563_CLK_RFD != RFD_DIV16)
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#error "invalid SPC563_CLK_RFD value specified"
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#endif
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/**
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* @brief PLL output clock.
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*/
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#define SPC563_PLLCLK ((EXTCLK / (SPC563_CLK_PREDIV + 1)) * SPC563_CLK_MFD)
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#if (SPC563_PLLCLK < 256000000) || (SPC563_PLLCLK > 512000000)
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#error "VCO frequency out of the acceptable range (256...512)"
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#endif
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/**
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* @brief PLL output clock.
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*/
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#if !SPC563_CLK_BYPASS || defined(__DOXYGEN__)
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#define SPC563_SYSCLK (SPC563_PLLCLK / (1 << (SPC563_CLK_RFD + 1)))
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#else
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#define SPC563_SYSCLK EXTCLK
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#endif
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#if (SPC563_SYSCLK > 80000000) && !SPC563_ALLOW_OVERCLOCK
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#error "System clock above maximum rated frequency (80MHz)"
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#endif
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/**
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* @brief Flash wait states are a function of the system clock.
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*/
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#if (SPC563_SYSCLK <= 30000000) || defined(__DOXYGEN__)
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#define SPC563_FLASH_WS (BIUCR_APC_0 | BIUCR_RWSC_0 | BIUCR_WWSC_1)
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#elif SPC563_SYSCLK <= 60000000
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#define SPC563_FLASH_WS (BIUCR_APC_1 | BIUCR_RWSC_1 | BIUCR_WWSC_1)
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#else
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#define SPC563_FLASH_WS (BIUCR_APC_2 | BIUCR_RWSC_2 | BIUCR_WWSC_1)
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#endif
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver macros. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* External declarations. */
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/*===========================================================================*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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void hal_lld_init(void);
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void spc563_clock_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _HAL_LLD_H_ */
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/** @} */
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