491 lines
11 KiB
C
491 lines
11 KiB
C
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/*
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* Licensed under ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file FlexPWM_v1/flexpwm.h
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* @brief SPC5xx FlexPWM header file.
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*
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* @addtogroup PWM
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* @{
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*/
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#ifndef _FLEXPWM_H_
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#define _FLEXPWM_H_
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/*===========================================================================*/
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/* Driver constants. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver pre-compile time settings. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Derived constants and error checks. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver data structures and types. */
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/*===========================================================================*/
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/**
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* @brief SPC5 FlexPWM registers block.
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* @note Redefined from the SPC5 headers because the non uniform
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* declaration of the SubModules registers among the various
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* sub-families.
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*/
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struct spc5_flexpwm_submodule {
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union {
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vuint16_t R;
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} CNT; /* Counter Register */
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union {
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vuint16_t R;
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} INIT; /* Initial Count Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t DBGEN :1;
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vuint16_t WAITEN :1;
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vuint16_t INDEP :1;
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vuint16_t PWMA_INIT :1;
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vuint16_t PWMB_INIT :1;
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vuint16_t PWMX_INIT :1;
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vuint16_t INIT_SEL :2;
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vuint16_t FRCEN :1;
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vuint16_t FORCE :1;
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vuint16_t FORCE_SEL :3;
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vuint16_t RELOAD_SEL :1;
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vuint16_t CLK_SEL :2;
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} B;
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} CTRL2; /* Control 2 Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t LDFQ :4;
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vuint16_t HALF :1;
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vuint16_t FULL :1;
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vuint16_t DT :2;
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vuint16_t :1;
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vuint16_t PRSC :3;
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vuint16_t :3;
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vuint16_t DBLEN :1;
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} B;
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} CTRL; /* Control Register */
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union {
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vuint16_t R;
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} VAL[6]; /* Value Register 0->5 */
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union {
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vuint16_t R;
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struct {
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vuint16_t FRACAEN :1;
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vuint16_t :10;
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vuint16_t FRACADLY :5;
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} B;
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} FRACA; /* Fractional Delay Register A */
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union {
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vuint16_t R;
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struct {
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vuint16_t FRACBEN :1;
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vuint16_t :10;
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vuint16_t FRACBDLY :5;
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} B;
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} FRACB; /* Fractional Delay Register B */
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union {
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vuint16_t R;
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struct {
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vuint16_t PWMA_IN :1;
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vuint16_t PWMB_IN :1;
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vuint16_t PWMX_IN :1;
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vuint16_t :2;
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vuint16_t POLA :1;
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vuint16_t POLB :1;
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vuint16_t POLX :1;
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vuint16_t :2;
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vuint16_t PWMAFS :2;
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vuint16_t PWMBFS :2;
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vuint16_t PWMXFS :2;
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} B;
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} OCTRL; /* Output Control Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t :1;
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vuint16_t RUF :1;
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vuint16_t REF :1;
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vuint16_t RF :1;
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vuint16_t CFA1 :1;
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vuint16_t CFA0 :1;
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vuint16_t CFB1 :1;
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vuint16_t CFB0 :1;
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vuint16_t CFX1 :1;
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vuint16_t CFX0 :1;
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vuint16_t CMPF :6;
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} B;
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} STS; /* Status Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t :2;
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vuint16_t REIE :1;
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vuint16_t RIE :1;
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vuint16_t :4;
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vuint16_t CX1IE :1;
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vuint16_t CX0IE :1;
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vuint16_t CMPIE :6;
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} B;
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} INTEN; /* Interrupt Enable Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t :6;
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vuint16_t VALDE :1;
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vuint16_t FAND :1;
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vuint16_t CAPTDE :2;
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vuint16_t CA1DE :1;
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vuint16_t CA0DE :1;
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vuint16_t CB1DE :1;
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vuint16_t CB0DE :1;
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vuint16_t CX1DE :1;
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vuint16_t CX0DE :1;
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} B;
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} DMAEN; /* DMA Enable Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t :10;
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vuint16_t OUT_TRIG_EN :6;
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} B;
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} TCTRL; /* Output Trigger Control Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t :4;
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vuint16_t DISX :4;
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vuint16_t DISB :4;
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vuint16_t DISA :4;
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} B;
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} DISMAP; /* Fault Disable Mapping Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t :5;
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vuint16_t DTCNT0 :11;
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} B;
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} DTCNT0; /* Deadtime Count Register 0 */
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union {
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vuint16_t R;
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struct {
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vuint16_t :5;
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vuint16_t DTCNT1 :11;
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} B;
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} DTCNT1; /* Deadtime Count Register 1 */
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union {
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vuint16_t R;
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struct {
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vuint16_t CA1CNT :3;
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vuint16_t CA0CNT :3;
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vuint16_t CFAWM :2;
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vuint16_t EDGCNTAEN :1;
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vuint16_t INPSELA :1;
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vuint16_t EDGA1 :2;
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vuint16_t EDGA0 :2;
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vuint16_t ONESHOTA :1;
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vuint16_t ARMA :1;
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} B;
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} CAPTCTRLA; /* Capture Control Register A */
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union {
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vuint16_t R;
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struct {
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vuint16_t EDGCNTA :8;
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vuint16_t EDGCMPA :8;
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} B;
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} CAPTCOMPA; /* Capture Compare Register A */
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union {
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vuint16_t R;
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struct {
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vuint16_t CB1CNT :3;
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vuint16_t CB0CNT :3;
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vuint16_t CFBWM :2;
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vuint16_t EDGCNTBEN :1;
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vuint16_t INPSELB :1;
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vuint16_t EDGB1 :2;
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vuint16_t EDGB0 :2;
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vuint16_t ONESHOTB :1;
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vuint16_t ARMB :1;
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} B;
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} CAPTCTRLB; /* Capture Control Register B */
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union {
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vuint16_t R;
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struct {
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vuint16_t EDGCNTB :8;
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vuint16_t EDGCMPB :8;
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} B;
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} CAPTCOMPB; /* Capture Compare Register B */
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union {
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vuint16_t R;
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struct {
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vuint16_t CX1CNT :3;
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vuint16_t CX0CNT :3;
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vuint16_t CFXWM :2;
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vuint16_t EDGCNTX_EN :1;
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vuint16_t INP_SELX :1;
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vuint16_t EDGX1 :2;
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vuint16_t EDGX0 :2;
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vuint16_t ONESHOTX :1;
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vuint16_t ARMX :1;
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} B;
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} CAPTCTRLX; /* Capture Control Register B */
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union {
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vuint16_t R;
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struct {
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vuint16_t EDGCNTX :8;
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vuint16_t EDGCMPX :8;
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} B;
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} CAPTCOMPX; /* Capture Compare Register X */
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union {
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vuint16_t R;
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struct {
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vuint16_t CAPTVAL0 :16;
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} B;
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} CVAL0; /* Capture Value 0 Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t :12;
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vuint16_t CVAL0CYC :4;
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} B;
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} CVAL0C; /* Capture Value 0 Cycle Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t CAPTVAL1 :16;
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} B;
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} CVAL1; /* Capture Value 1 Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t :12;
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vuint16_t CVAL1CYC :4;
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} B;
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} CVAL1C; /* Capture Value 1 Cycle Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t CAPTVAL2 :16;
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} B;
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} CVAL2; /* Capture Value 2 Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t :12;
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vuint16_t CVAL2CYC :4;
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} B;
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} CVAL2C; /* Capture Value 2 Cycle Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t CAPTVAL3 :16;
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} B;
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} CVAL3; /* Capture Value 3 Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t :12;
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vuint16_t CVAL3CYC :4;
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} B;
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} CVAL3C; /* Capture Value 3 Cycle Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t CAPTVAL4 :16;
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} B;
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} CVAL4; /* Capture Value 4 Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t :12;
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vuint16_t CVAL4CYC :4;
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} B;
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} CVAL4C; /* Capture Value 4 Cycle Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t CAPTVAL5 :16;
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} B;
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} CVAL5; /* Capture Value 5 Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t :12;
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vuint16_t CVAL5CYC :4;
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} B;
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} CVAL5C; /* Capture Value 5 Cycle Register */
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uint32_t FLEXPWM_SUB_reserved0; /* (0x04A - 0x050)/4 = 0x01 */
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};
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/* end of FLEXPWM_SUB_tag */
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struct spc5_flexpwm {
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struct spc5_flexpwm_submodule SUB[4];
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union {
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vuint16_t R;
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struct {
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vuint16_t :4;
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vuint16_t PWMA_EN :4;
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vuint16_t PWMB_EN :4;
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vuint16_t PWMX_EN :4;
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} B;
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} OUTEN; /* Output Enable Register */
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union {
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vuint16_t R;
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struct {
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vuint16_t :4;
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vuint16_t MASKA :4;
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vuint16_t MASKB :4;
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vuint16_t MASKX :4;
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} B;
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} MASK; /* Output Mask Register */
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union {
|
||
|
|
vuint16_t R;
|
||
|
|
struct {
|
||
|
|
vuint16_t :8;
|
||
|
|
vuint16_t OUTA_3 :1;
|
||
|
|
vuint16_t OUTB_3 :1;
|
||
|
|
vuint16_t OUTA_2 :1;
|
||
|
|
vuint16_t OUTB_2 :1;
|
||
|
|
vuint16_t OUTA_1 :1;
|
||
|
|
vuint16_t OUTB_1 :1;
|
||
|
|
vuint16_t OUTA_0 :1;
|
||
|
|
vuint16_t OUTB_0 :1;
|
||
|
|
} B;
|
||
|
|
} SWCOUT; /* Software Controlled Output Register */
|
||
|
|
|
||
|
|
union {
|
||
|
|
vuint16_t R;
|
||
|
|
struct {
|
||
|
|
vuint16_t SELA_3 :2;
|
||
|
|
vuint16_t SELB_3 :2;
|
||
|
|
vuint16_t SELA_2 :2;
|
||
|
|
vuint16_t SELB_2 :2;
|
||
|
|
vuint16_t SELA_1 :2;
|
||
|
|
vuint16_t SELB_1 :2;
|
||
|
|
vuint16_t SELA_0 :2;
|
||
|
|
vuint16_t SELB_0 :2;
|
||
|
|
} B;
|
||
|
|
} DTSRCSEL; /* Deadtime Source Select Register */
|
||
|
|
|
||
|
|
union {
|
||
|
|
vuint16_t R;
|
||
|
|
struct {
|
||
|
|
vuint16_t IPOL :4;
|
||
|
|
vuint16_t RUN :4;
|
||
|
|
vuint16_t CLDOK :4;
|
||
|
|
vuint16_t LDOK :4;
|
||
|
|
} B;
|
||
|
|
} MCTRL; /* Master Control Register */
|
||
|
|
|
||
|
|
int16_t FLEXPWM_reserved1;
|
||
|
|
|
||
|
|
union {
|
||
|
|
vuint16_t R;
|
||
|
|
struct {
|
||
|
|
vuint16_t FLVL :4;
|
||
|
|
vuint16_t FAUTO :4;
|
||
|
|
vuint16_t FSAFE :4;
|
||
|
|
vuint16_t FIE :4;
|
||
|
|
} B;
|
||
|
|
} FCTRL; /* Fault Control Register */
|
||
|
|
|
||
|
|
union {
|
||
|
|
vuint16_t R;
|
||
|
|
struct {
|
||
|
|
vuint16_t :3;
|
||
|
|
vuint16_t FTEST :1;
|
||
|
|
vuint16_t FFPIN :4;
|
||
|
|
vuint16_t :4;
|
||
|
|
vuint16_t FFLAG :4;
|
||
|
|
} B;
|
||
|
|
} FSTS; /* Fault Status Register */
|
||
|
|
|
||
|
|
union {
|
||
|
|
vuint16_t R;
|
||
|
|
struct {
|
||
|
|
vuint16_t :5;
|
||
|
|
vuint16_t FILT_CNT :3;
|
||
|
|
vuint16_t FILT_PER :8;
|
||
|
|
} B;
|
||
|
|
} FFILT; /* Fault FilterRegister */
|
||
|
|
|
||
|
|
};
|
||
|
|
/* end of FLEXPWM_tag */
|
||
|
|
|
||
|
|
/*===========================================================================*/
|
||
|
|
/* Driver macros. */
|
||
|
|
/*===========================================================================*/
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @name FlexPWM units references
|
||
|
|
* @{
|
||
|
|
*/
|
||
|
|
#if SPC5_HAS_FLEXPWM0
|
||
|
|
#define SPC5_FLEXPWM_0 (*(volatile struct spc5_flexpwm *)0xFFE24000UL)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#if SPC5_HAS_FLEXPWM1
|
||
|
|
#define SPC5_FLEXPWM_1 (*(volatile struct spc5_flexpwm *)0xFFE28000UL)
|
||
|
|
#endif
|
||
|
|
/** @} */
|
||
|
|
|
||
|
|
#endif /* _FLEXPWM_H_ */
|
||
|
|
|
||
|
|
/** @} */
|