575 lines
19 KiB
C
575 lines
19 KiB
C
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/*
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ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
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This file is part of ChibiOS/RT.
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ChibiOS/RT is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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ChibiOS/RT is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**
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* @file STM32/i2c_lld.c
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* @brief STM32 I2C subsystem low level driver source. Slave mode not implemented.
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* @addtogroup STM32_I2C
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#if HAL_USE_I2C || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief I2C1 driver identifier.*/
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#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
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I2CDriver I2CD1;
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#endif
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/** @brief I2C2 driver identifier.*/
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#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
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I2CDriver I2CD2;
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#endif
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static uint32_t i2c_get_event(I2CDriver *i2cp){
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uint32_t regSR1 = i2cp->i2c_register->SR1;
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uint32_t regSR2 = i2cp->i2c_register->SR2;
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/* return the last event value from I2C status registers */
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return (I2C_EV_MASK & (regSR1 | (regSR2 << 16)));
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}
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static void i2c_serve_event_interrupt(I2CDriver *i2cp) {
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static __IO uint8_t *txBuffp, *rxBuffp, *datap;
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I2C_TypeDef *dp = i2cp->i2c_register;
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switch(i2c_get_event(i2cp)) {
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case I2C_EV5_MASTER_MODE_SELECT:
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i2cp->flags &= ~I2C_FLG_HEADER_SENT;
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dp->DR = i2cp->slave_addr1;
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break;
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case I2C_EV9_MASTER_ADDR_10BIT:
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if(i2cp->flags & I2C_FLG_MASTER_RECEIVER) {
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i2cp->slave_addr1 |= 0x01;
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i2cp->flags |= I2C_FLG_HEADER_SENT;
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}
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dp->DR = i2cp->slave_addr2;
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break;
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//------------------------------------------------------------------------
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// Master Transmitter ----------------------------------------------------
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//------------------------------------------------------------------------
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case I2C_EV6_MASTER_TRA_MODE_SELECTED:
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if(i2cp->flags & I2C_FLG_HEADER_SENT){
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dp->CR1 |= I2C_CR1_START; // re-send the start in 10-Bit address mode
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break;
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}
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//Initialize the transmit buffer pointer
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txBuffp = (uint8_t*)i2cp->txbuf;
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datap = txBuffp;
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txBuffp++;
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i2cp->remaining_bytes--;
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/* If no further data to be sent, disable the I2C ITBUF in order to not have a TxE interrupt */
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if(i2cp->remaining_bytes == 0) {
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dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
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}
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//EV8_1 write the first data
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dp->DR = *datap;
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break;
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case I2C_EV8_MASTER_BYTE_TRANSMITTING:
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if(i2cp->remaining_bytes > 0) {
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datap = txBuffp;
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txBuffp++;
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i2cp->remaining_bytes--;
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if(i2cp->remaining_bytes == 0) {
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/* If no further data to be sent, disable the ITBUF in order to not have a TxE interrupt */
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dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
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}
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dp->DR = *datap;
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}
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break;
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case I2C_EV8_2_MASTER_BYTE_TRANSMITTED:
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dp->CR1 |= I2C_CR1_STOP; // stop generation
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/* Disable ITEVT In order to not have again a BTF IT */
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dp->CR2 &= (uint16_t)~I2C_CR2_ITEVTEN;
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/* Portable I2C ISR code defined in the high level driver, note, it is a macro.*/
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_i2c_isr_code(i2cp);
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break;
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//------------------------------------------------------------------------
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// Master Receiver -------------------------------------------------------
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//------------------------------------------------------------------------
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case I2C_EV6_MASTER_REC_MODE_SELECTED:
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chSysLockFromIsr();
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switch(i2cp->flags & EV6_SUBEV_MASK) {
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case I2C_EV6_3_MASTER_REC_1BTR_MODE_SELECTED: // only an single byte to receive
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/* Clear ACK */
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dp->CR1 &= (uint16_t)~I2C_CR1_ACK;
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/* Program the STOP */
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dp->CR1 |= I2C_CR1_STOP;
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break;
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case I2C_EV6_1_MASTER_REC_2BTR_MODE_SELECTED: // only two bytes to receive
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/* Clear ACK */
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dp->CR1 &= (uint16_t)~I2C_CR1_ACK;
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/* Disable the ITBUF in order to have only the BTF interrupt */
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dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
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break;
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}
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chSysUnlockFromIsr();
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/* Initialize receive buffer pointer */
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rxBuffp = i2cp->rxbuf;
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break;
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case I2C_EV7_MASTER_REC_BYTE_RECEIVED:
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if(i2cp->remaining_bytes != 3) {
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/* Read the data register */
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*rxBuffp = dp->DR;
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rxBuffp++;
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i2cp->remaining_bytes--;
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switch(i2cp->remaining_bytes){
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case 3:
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/* Disable the ITBUF in order to have only the BTF interrupt */
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dp->CR2 &= (uint16_t)~I2C_CR2_ITBUFEN;
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i2cp->flags |= I2C_FLG_3BTR;
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break;
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case 0:
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/* Portable I2C ISR code defined in the high level driver, note, it is a macro.*/
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_i2c_isr_code(i2cp);
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break;
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}
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}
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// when remaining 3 bytes do nothing, wait until RXNE and BTF are set (until 2 bytes are received)
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break;
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case I2C_EV7_MASTER_REC_BYTE_QUEUED:
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switch(i2cp->flags & EV7_SUBEV_MASK) {
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case I2C_EV7_2_MASTER_REC_3BYTES_TO_PROCESS:
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// DataN-2 and DataN-1 are received
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chSysLockFromIsr();
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dp->CR2 |= I2C_CR2_ITBUFEN;
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/* Clear ACK */
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dp->CR1 &= (uint16_t)~I2C_CR1_ACK;
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/* Read the DataN-2*/
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*rxBuffp = dp->DR; //This clear the RXE & BFT flags and launch the DataN reception in the shift register (ending the SCL stretch)
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rxBuffp++;
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/* Program the STOP */
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dp->CR1 |= I2C_CR1_STOP;
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/* Read the DataN-1 */
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*rxBuffp = dp->DR;
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chSysUnlockFromIsr();
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rxBuffp++;
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/* Decrement the number of readed bytes */
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i2cp->remaining_bytes -= 2;
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i2cp->flags = 0;
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// ready for read DataN on the next EV7
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break;
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case I2C_EV7_3_MASTER_REC_2BYTES_TO_PROCESS: // only for case of two bytes to be received
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// DataN-1 and DataN are received
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chSysLockFromIsr();
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/* Program the STOP */
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dp->CR1 |= I2C_CR1_STOP;
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/* Read the DataN-1*/
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*rxBuffp = dp->DR;
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chSysUnlockFromIsr();
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rxBuffp++;
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/* Read the DataN*/
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*rxBuffp = dp->DR;
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i2cp->remaining_bytes = 0;
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i2cp->flags = 0;
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/* Portable I2C ISR code defined in the high level driver, note, it is a macro.*/
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_i2c_isr_code(i2cp);
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break;
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}
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break;
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}
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}
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static void i2c_serve_error_interrupt(I2CDriver *i2cp) {
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i2cflags_t flags;
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I2C_TypeDef *reg;
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reg = i2cp->i2c_register;
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flags = I2CD_NO_ERROR;
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if(reg->SR1 & I2C_SR1_BERR) { // Bus error
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reg->SR1 &= ~I2C_SR1_BERR;
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flags |= I2CD_BUS_ERROR;
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}
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if(reg->SR1 & I2C_SR1_ARLO) { // Arbitration lost
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reg->SR1 &= ~I2C_SR1_ARLO;
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flags |= I2CD_ARBITRATION_LOST;
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}
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if(reg->SR1 & I2C_SR1_AF) { // Acknowledge fail
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reg->SR1 &= ~I2C_SR1_AF;
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reg->CR1 |= I2C_CR1_STOP; // setting stop bit
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flags |= I2CD_ACK_FAILURE;
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}
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if(reg->SR1 & I2C_SR1_OVR) { // Overrun
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reg->SR1 &= ~I2C_SR1_OVR;
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flags |= I2CD_OVERRUN;
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}
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if(reg->SR1 & I2C_SR1_PECERR) { // PEC error
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reg->SR1 &= ~I2C_SR1_PECERR;
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flags |= I2CD_PEC_ERROR;
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}
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if(reg->SR1 & I2C_SR1_TIMEOUT) { // SMBus Timeout
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reg->SR1 &= ~I2C_SR1_TIMEOUT;
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flags |= I2CD_TIMEOUT;
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}
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if(reg->SR1 & I2C_SR1_SMBALERT) { // SMBus alert
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reg->SR1 &= ~I2C_SR1_SMBALERT;
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flags |= I2CD_SMB_ALERT;
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}
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if(flags != I2CD_NO_ERROR) {
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// send communication end signal
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_i2c_isr_code(i2cp);
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chSysLockFromIsr();
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i2cAddFlagsI(i2cp, flags);
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chSysUnlockFromIsr();
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}
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}
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#if STM32_I2C_USE_I2C1 || defined(__DOXYGEN__)
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/**
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* @brief I2C1 event interrupt handler.
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*/
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CH_IRQ_HANDLER(I2C1_EV_IRQHandler) {
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CH_IRQ_PROLOGUE();
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i2c_serve_event_interrupt(&I2CD1);
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief I2C1 error interrupt handler.
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*/
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CH_IRQ_HANDLER(I2C1_ER_IRQHandler) {
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CH_IRQ_PROLOGUE();
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i2c_serve_error_interrupt(&I2CD1);
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CH_IRQ_EPILOGUE();
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}
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#endif
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#if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__)
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/**
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* @brief I2C2 event interrupt handler.
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*/
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CH_IRQ_HANDLER(I2C2_EV_IRQHandler) {
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CH_IRQ_PROLOGUE();
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i2c_serve_event_interrupt(&I2CD2);
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CH_IRQ_EPILOGUE();
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}
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/**
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* @brief I2C2 error interrupt handler.
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*/
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CH_IRQ_HANDLER(I2C2_ER_IRQHandler) {
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CH_IRQ_PROLOGUE();
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i2c_serve_error_interrupt(&I2CD2);
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CH_IRQ_EPILOGUE();
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}
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#endif
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void i2c_lld_reset(I2CDriver *i2cp){
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chDbgCheck((i2cp->state == I2C_STOP)||(i2cp->state == I2C_READY),
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"i2c_lld_reset: invalid state");
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RCC->APB1RSTR = RCC_APB1RSTR_I2C1RST; // reset I2C 1
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RCC->APB1RSTR = 0;
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}
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void i2c_lld_set_clock(I2CDriver *i2cp, int32_t clock_speed, I2C_DutyCycle_t duty) {
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volatile uint16_t regCCR, regCR2, freq, clock_div;
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volatile uint16_t pe_bit_saved;
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chDbgCheck((i2cp != NULL) && (clock_speed > 0) && (clock_speed <= 4000000),
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"i2c_lld_set_clock");
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/*---------------------------- CR2 Configuration ------------------------*/
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/* Get the I2Cx CR2 value */
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regCR2 = i2cp->i2c_register->CR2;
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/* Clear frequency FREQ[5:0] bits */
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regCR2 &= (uint16_t)~I2C_CR2_FREQ;
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/* Set frequency bits depending on pclk1 value */
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freq = (uint16_t)(STM32_PCLK1 / 1000000);
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chDbgCheck((freq >= 2) && (freq <= 36),
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"i2c_lld_set_clock() : Peripheral clock freq. out of range");
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regCR2 |= freq;
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i2cp->i2c_register->CR2 = regCR2;
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/*---------------------------- CCR Configuration ------------------------*/
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pe_bit_saved = (i2cp->i2c_register->CR1 & I2C_CR1_PE);
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/* Disable the selected I2C peripheral to configure TRISE */
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i2cp->i2c_register->CR1 &= (uint16_t)~I2C_CR1_PE;
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/* Clear F/S, DUTY and CCR[11:0] bits */
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regCCR = 0;
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clock_div = I2C_CCR_CCR;
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/* Configure clock_div in standard mode */
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if (clock_speed <= 100000) {
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chDbgAssert(duty == stdDutyCycle,
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"i2c_lld_set_clock(), #3", "Invalid standard mode duty cycle");
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/* Standard mode clock_div calculate: Tlow/Thigh = 1/1 */
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clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 2));
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/* Test if CCR value is under 0x4, and set the minimum allowed value */
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if (clock_div < 0x04) clock_div = 0x04;
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/* Set clock_div value for standard mode */
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regCCR |= (clock_div & I2C_CCR_CCR);
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/* Set Maximum Rise Time for standard mode */
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i2cp->i2c_register->TRISE = freq + 1;
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}
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/* Configure clock_div in fast mode */
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else if(clock_speed <= 400000) {
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chDbgAssert((duty == fastDutyCycle_2) || (duty == fastDutyCycle_16_9),
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"i2c_lld_set_clock(), #3", "Invalid fast mode duty cycle");
|
||
|
|
if(duty == fastDutyCycle_2) {
|
||
|
|
/* Fast mode clock_div calculate: Tlow/Thigh = 2/1 */
|
||
|
|
clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 3));
|
||
|
|
}
|
||
|
|
else if(duty == fastDutyCycle_16_9) {
|
||
|
|
/* Fast mode clock_div calculate: Tlow/Thigh = 16/9 */
|
||
|
|
clock_div = (uint16_t)(STM32_PCLK1 / (clock_speed * 25));
|
||
|
|
/* Set DUTY bit */
|
||
|
|
regCCR |= I2C_CCR_DUTY;
|
||
|
|
}
|
||
|
|
/* Test if CCR value is under 0x1, and set the minimum allowed value */
|
||
|
|
if(clock_div < 0x01) clock_div = 0x01;
|
||
|
|
/* Set clock_div value and F/S bit for fast mode*/
|
||
|
|
regCCR |= (I2C_CCR_FS | (clock_div & I2C_CCR_CCR));
|
||
|
|
/* Set Maximum Rise Time for fast mode */
|
||
|
|
i2cp->i2c_register->TRISE = (freq * 300 / 1000) + 1;
|
||
|
|
}
|
||
|
|
chDbgAssert((clock_div <= I2C_CCR_CCR),
|
||
|
|
"i2c_lld_set_clock(), #2", "Too low clock clock speed selected");
|
||
|
|
|
||
|
|
/* Write to I2Cx CCR */
|
||
|
|
i2cp->i2c_register->CCR = regCCR;
|
||
|
|
|
||
|
|
/* restore the I2C peripheral enabled state */
|
||
|
|
i2cp->i2c_register->CR1 |= pe_bit_saved;
|
||
|
|
}
|
||
|
|
|
||
|
|
void i2c_lld_set_opmode(I2CDriver *i2cp, I2C_opMode_t opmode) {
|
||
|
|
uint16_t regCR1;
|
||
|
|
|
||
|
|
/*---------------------------- CR1 Configuration ------------------------*/
|
||
|
|
/* Get the I2Cx CR1 value */
|
||
|
|
regCR1 = i2cp->i2c_register->CR1;
|
||
|
|
switch(opmode){
|
||
|
|
case opmodeI2C:
|
||
|
|
regCR1 &= (uint16_t)~(I2C_CR1_SMBUS|I2C_CR1_SMBTYPE);
|
||
|
|
break;
|
||
|
|
case opmodeSMBusDevice:
|
||
|
|
regCR1 |= I2C_CR1_SMBUS;
|
||
|
|
regCR1 &= (uint16_t)~(I2C_CR1_SMBTYPE);
|
||
|
|
break;
|
||
|
|
case opmodeSMBusHost:
|
||
|
|
regCR1 |= (I2C_CR1_SMBUS|I2C_CR1_SMBTYPE);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
/* Write to I2Cx CR1 */
|
||
|
|
i2cp->i2c_register->CR1 = regCR1;
|
||
|
|
}
|
||
|
|
|
||
|
|
void i2c_lld_set_own_address(I2CDriver *i2cp, int16_t address, int8_t nbit_addr) {
|
||
|
|
/*---------------------------- OAR1 Configuration -----------------------*/
|
||
|
|
/* Set the Own Address1 and bit number address acknowledged */
|
||
|
|
i2cp->i2c_register->OAR1 = address & I2C_OAR1_ADD0_9;
|
||
|
|
switch(nbit_addr) {
|
||
|
|
case 10:
|
||
|
|
i2cp->i2c_register->OAR1 |= I2C_OAR1_ADDMODE; // set ADDMODE bit and bit 14.
|
||
|
|
case 7:
|
||
|
|
i2cp->i2c_register->OAR1 |= I2C_OAR1_BIT14; // set only bit 14.
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Low level I2C driver initialization.
|
||
|
|
*/
|
||
|
|
void i2c_lld_init(void) {
|
||
|
|
|
||
|
|
#if STM32_I2C_USE_I2C1
|
||
|
|
RCC->APB1RSTR = RCC_APB1RSTR_I2C1RST; // reset I2C 1
|
||
|
|
RCC->APB1RSTR = 0;
|
||
|
|
i2cObjectInit(&I2CD1);
|
||
|
|
I2CD1.i2c_register = I2C1;
|
||
|
|
#endif
|
||
|
|
#if STM32_I2C_USE_I2C2
|
||
|
|
RCC->APB1RSTR = RCC_APB1RSTR_I2C2RST; // reset I2C 2
|
||
|
|
RCC->APB1RSTR = 0;
|
||
|
|
i2cObjectInit(&I2CD2);
|
||
|
|
I2CD2.i2c_register = I2C2;
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Configures and activates the I2C peripheral.
|
||
|
|
*
|
||
|
|
* @param[in] i2cp pointer to the @p I2CDriver object
|
||
|
|
*/
|
||
|
|
void i2c_lld_start(I2CDriver *i2cp) {
|
||
|
|
chDbgCheck((i2cp->state == I2C_STOP)||(i2cp->state == I2C_READY),
|
||
|
|
"i2c_lld_start: invalid state");
|
||
|
|
|
||
|
|
/* If in stopped state then enables the I2C clock.*/
|
||
|
|
if (i2cp->state == I2C_STOP) {
|
||
|
|
#if STM32_I2C_USE_I2C1
|
||
|
|
if (&I2CD1 == i2cp) {
|
||
|
|
NVICEnableVector(I2C1_EV_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY);
|
||
|
|
NVICEnableVector(I2C1_ER_IRQn, STM32_I2C_I2C1_IRQ_PRIORITY);
|
||
|
|
RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; // I2C 1 clock enable
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#if STM32_I2C_USE_I2C2
|
||
|
|
if (&I2CD2 == i2cp) {
|
||
|
|
NVICEnableVector(I2C2_EV_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY);
|
||
|
|
NVICEnableVector(I2C2_ER_IRQn, STM32_I2C_I2C2_IRQ_PRIORITY);
|
||
|
|
RCC->APB1ENR |= RCC_APB1ENR_I2C2EN; // I2C 2 clock enable
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
i2cp->i2c_register->CR1 |= I2C_CR1_PE; // enable I2C peripheral
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Deactivates the I2C peripheral.
|
||
|
|
*
|
||
|
|
* @param[in] i2cp pointer to the @p I2CDriver object
|
||
|
|
*/
|
||
|
|
void i2c_lld_stop(I2CDriver *i2cp) {
|
||
|
|
|
||
|
|
chDbgCheck((i2cp->state == I2C_READY),
|
||
|
|
"i2c_lld_stop: invalid state");
|
||
|
|
|
||
|
|
/* I2C disable.*/
|
||
|
|
i2cp->i2c_register->CR1 = 0;
|
||
|
|
|
||
|
|
/* If in ready state then disables the I2C clock.*/
|
||
|
|
if (i2cp->state == I2C_READY) {
|
||
|
|
#if STM32_I2C_USE_I2C1
|
||
|
|
if (&I2CD1 == i2cp) {
|
||
|
|
NVICDisableVector(I2C1_EV_IRQn);
|
||
|
|
NVICDisableVector(I2C1_ER_IRQn);
|
||
|
|
RCC->APB1ENR &= ~RCC_APB1ENR_I2C1EN;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
#if STM32_I2C_USE_I2C2
|
||
|
|
if (&I2CD2 == i2cp) {
|
||
|
|
NVICDisableVector(I2C2_EV_IRQn);
|
||
|
|
NVICDisableVector(I2C2_ER_IRQn);
|
||
|
|
RCC->APB1ENR &= ~RCC_APB1ENR_I2C2EN;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Transmits data ever the I2C bus as master.
|
||
|
|
*
|
||
|
|
* @param[in] i2cp pointer to the @p I2CDriver object
|
||
|
|
* @param[in] n number of words to send
|
||
|
|
* @param[in] slave_addr1 the 7-bit address of the slave (should be aligned to left)
|
||
|
|
* @param[in] slave_addr2 used in 10 bit address mode
|
||
|
|
* @param[in] txbuf the pointer to the transmit buffer
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr, size_t n, void *txbuf) {
|
||
|
|
|
||
|
|
// enable ERR, EVT & BUF ITs
|
||
|
|
i2cp->i2c_register->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN);
|
||
|
|
i2cp->i2c_register->CR1 &= ~I2C_CR1_POS;
|
||
|
|
|
||
|
|
switch(i2cp->nbit_address){
|
||
|
|
case 7:
|
||
|
|
i2cp->slave_addr1 = ((slave_addr <<1) & 0x00FE); // LSB = 0 -> write
|
||
|
|
break;
|
||
|
|
case 10:
|
||
|
|
i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); // add the two msb of 10-bit address to the header
|
||
|
|
i2cp->slave_addr1 |= 0xF0; // add the header bits with LSB = 0 -> write
|
||
|
|
i2cp->slave_addr2 = slave_addr & 0x00FF; // the remaining 8 bit of 10-bit address
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
i2cp->txbuf = txbuf;
|
||
|
|
i2cp->remaining_bytes = n;
|
||
|
|
i2cp->flags = 0;
|
||
|
|
i2cp->errors = 0;
|
||
|
|
|
||
|
|
i2cp->i2c_register->CR1 |= I2C_CR1_START; // send start bit
|
||
|
|
|
||
|
|
#if !I2C_USE_WAIT
|
||
|
|
/* Wait until the START condition is generated on the bus: the START bit is cleared by hardware */
|
||
|
|
uint32_t tmo = 0xfffff;
|
||
|
|
while((i2cp->i2c_register->CR1 & I2C_CR1_START) && tmo--)
|
||
|
|
;
|
||
|
|
#endif /* I2C_USE_WAIT */
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* @brief Receives data from the I2C bus.
|
||
|
|
*
|
||
|
|
* @param[in] i2cp pointer to the @p I2CDriver object
|
||
|
|
* @param[in] slave_addr1 7-bit address of he slave
|
||
|
|
* @param[in] slave_addr2 used in 10-bit address mode
|
||
|
|
* @param[in] n number of words to receive
|
||
|
|
* @param[out] rxbuf the pointer to the receive buffer
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr, size_t n, void *rxbuf) {
|
||
|
|
// enable ERR, EVT & BUF ITs
|
||
|
|
i2cp->i2c_register->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN);
|
||
|
|
i2cp->i2c_register->CR1 |= I2C_CR1_ACK; // acknowledge returned
|
||
|
|
i2cp->i2c_register->CR1 &= ~I2C_CR1_POS;
|
||
|
|
|
||
|
|
switch(i2cp->nbit_address){
|
||
|
|
case 7:
|
||
|
|
i2cp->slave_addr1 = ((slave_addr <<1) | 0x01); // LSB = 1 -> receive
|
||
|
|
break;
|
||
|
|
case 10:
|
||
|
|
i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); // add the two msb of 10-bit address to the header
|
||
|
|
i2cp->slave_addr1 |= 0xF0; // add the header bits (the LSB -> 1 will be add to second
|
||
|
|
i2cp->slave_addr2 = slave_addr & 0x00FF; // the remaining 8 bit of 10-bit address
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
i2cp->rxbuf = rxbuf;
|
||
|
|
i2cp->remaining_bytes = n;
|
||
|
|
i2cp->flags = I2C_FLG_MASTER_RECEIVER;
|
||
|
|
i2cp->errors = 0;
|
||
|
|
|
||
|
|
// Only one byte to be received
|
||
|
|
if(i2cp->remaining_bytes == 1) {
|
||
|
|
i2cp->flags |= I2C_FLG_1BTR;
|
||
|
|
}
|
||
|
|
// Only two bytes to be received
|
||
|
|
else if(i2cp->remaining_bytes == 2) {
|
||
|
|
i2cp->flags |= I2C_FLG_2BTR;
|
||
|
|
i2cp->i2c_register->CR1 |= I2C_CR1_POS; // Acknowledge Position
|
||
|
|
}
|
||
|
|
|
||
|
|
i2cp->i2c_register->CR1 |= I2C_CR1_START; // send start bit
|
||
|
|
|
||
|
|
#if !I2C_USE_WAIT
|
||
|
|
/* Wait until the START condition is generated on the bus: the START bit is cleared by hardware */
|
||
|
|
uint32_t tmo = 0xfffff;
|
||
|
|
while((i2cp->i2c_register->CR1 & I2C_CR1_START) && tmo--)
|
||
|
|
;
|
||
|
|
#endif /* I2C_USE_WAIT */
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif // HAL_USE_I2C
|
||
|
|
|