2013-06-15 16:38:10 +00:00
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/*
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SPC5 HAL - Copyright (C) 2013 STMicroelectronics
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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* SPC560Pxx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 1...15 Lowest...Highest.
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* DMA priorities:
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* 0...15 Highest...Lowest.
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*/
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#define SPC560Pxx_MCUCONF
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/*
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* HAL driver system settings.
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*/
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#define SPC5_NO_INIT FALSE
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#define SPC5_ALLOW_OVERCLOCK FALSE
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#define SPC5_DISABLE_WATCHDOG TRUE
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#define SPC5_FMPLL0_IDF_VALUE 5
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#define SPC5_FMPLL0_NDIV_VALUE 32
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#define SPC5_FMPLL0_ODF SPC5_FMPLL_ODF_DIV4
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#define SPC5_FMPLL1_IDF_VALUE 5
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#define SPC5_FMPLL1_NDIV_VALUE 60
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#define SPC5_FMPLL1_ODF SPC5_FMPLL_ODF_DIV4
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#define SPC5_AUX0CLK_SRC SPC5_CGM_SS_FMPLL0
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#define SPC5_MCONTROL_DIVIDER_VALUE 2
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#define SPC5_FMPLL1_CLK_DIVIDER_VALUE 2
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#define SPC5_AUX2CLK_SRC SPC5_CGM_SS_FMPLL1
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#define SPC5_SP_CLK_DIVIDER_VALUE 2
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#define SPC5_AUX3CLK_SRC SPC5_CGM_SS_FMPLL1
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#define SPC5_FR_CLK_DIVIDER_VALUE 2
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#define SPC5_ME_ME_BITS (SPC5_ME_ME_RUN1 | \
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SPC5_ME_ME_RUN2 | \
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SPC5_ME_ME_RUN3 | \
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SPC5_ME_ME_HALT0 | \
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SPC5_ME_ME_STOP0)
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#define SPC5_ME_TEST_MC_BITS (SPC5_ME_MC_SYSCLK_IRC | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_SAFE_MC_BITS (SPC5_ME_MC_PDO)
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#define SPC5_ME_DRUN_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_RUN0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_RUN1_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_RUN2_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_RUN3_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_HALT0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_STOP0_MC_BITS (SPC5_ME_MC_SYSCLK_FMPLL0 | \
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SPC5_ME_MC_IRCON | \
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SPC5_ME_MC_XOSC0ON | \
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SPC5_ME_MC_PLL0ON | \
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SPC5_ME_MC_PLL1ON | \
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SPC5_ME_MC_CFLAON_NORMAL | \
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SPC5_ME_MC_DFLAON_NORMAL | \
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SPC5_ME_MC_MVRON)
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#define SPC5_ME_RUN_PC3_BITS (SPC5_ME_RUN_PC_RUN0 | \
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SPC5_ME_RUN_PC_RUN1 | \
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SPC5_ME_RUN_PC_RUN2 | \
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SPC5_ME_RUN_PC_RUN3)
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#define SPC5_ME_RUN_PC4_BITS (SPC5_ME_RUN_PC_RUN0 | \
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SPC5_ME_RUN_PC_RUN1 | \
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SPC5_ME_RUN_PC_RUN2 | \
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SPC5_ME_RUN_PC_RUN3)
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#define SPC5_ME_RUN_PC5_BITS (SPC5_ME_RUN_PC_RUN0 | \
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SPC5_ME_RUN_PC_RUN1 | \
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SPC5_ME_RUN_PC_RUN2 | \
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SPC5_ME_RUN_PC_RUN3)
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#define SPC5_ME_RUN_PC6_BITS (SPC5_ME_RUN_PC_RUN0 | \
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SPC5_ME_RUN_PC_RUN1 | \
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SPC5_ME_RUN_PC_RUN2 | \
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SPC5_ME_RUN_PC_RUN3)
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#define SPC5_ME_RUN_PC7_BITS (SPC5_ME_RUN_PC_RUN0 | \
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SPC5_ME_RUN_PC_RUN1 | \
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SPC5_ME_RUN_PC_RUN2 | \
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SPC5_ME_RUN_PC_RUN3)
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#define SPC5_ME_LP_PC4_BITS (SPC5_ME_LP_PC_HALT0 | \
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SPC5_ME_LP_PC_STOP0)
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#define SPC5_ME_LP_PC5_BITS (SPC5_ME_LP_PC_HALT0 | \
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SPC5_ME_LP_PC_STOP0)
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#define SPC5_ME_LP_PC6_BITS (SPC5_ME_LP_PC_HALT0 | \
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SPC5_ME_LP_PC_STOP0)
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#define SPC5_ME_LP_PC7_BITS (SPC5_ME_LP_PC_HALT0 | \
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SPC5_ME_LP_PC_STOP0)
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#define SPC5_PIT0_IRQ_PRIORITY 4
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#define SPC5_CLOCK_FAILURE_HOOK() chSysHalt()
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/*
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* EDMA driver settings.
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*/
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#define SPC5_EDMA_CR_SETTING 0
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#define SPC5_EDMA_GROUP0_PRIORITIES \
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
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#define SPC5_EDMA_ERROR_IRQ_PRIO 2
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#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
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/*
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* Serial driver system settings.
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*/
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#define SPC5_SERIAL_USE_LINFLEX0 TRUE
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#define SPC5_SERIAL_USE_LINFLEX1 TRUE
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#define SPC5_SERIAL_LINFLEX0_PRIORITY 8
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#define SPC5_SERIAL_LINFLEX1_PRIORITY 8
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#define SPC5_SERIAL_LINFLEX0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_SERIAL_LINFLEX0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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#define SPC5_SERIAL_LINFLEX1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_SERIAL_LINFLEX1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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/*
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* PWM driver system settings.
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*/
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#define SPC5_PWM_USE_SMOD0 TRUE
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#define SPC5_PWM_USE_SMOD1 FALSE
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#define SPC5_PWM_USE_SMOD2 FALSE
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#define SPC5_PWM_USE_SMOD3 FALSE
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#define SPC5_PWM_SMOD0_PRIORITY 7
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#define SPC5_PWM_SMOD1_PRIORITY 7
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#define SPC5_PWM_SMOD2_PRIORITY 7
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#define SPC5_PWM_SMOD3_PRIORITY 7
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#define SPC5_PWM_FLEXPWM0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_PWM_FLEXPWM0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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/*
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* ICU driver system settings.
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*/
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#define SPC5_ICU_USE_SMOD0 TRUE
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#define SPC5_ICU_USE_SMOD1 FALSE
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#define SPC5_ICU_USE_SMOD2 FALSE
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#define SPC5_ICU_USE_SMOD3 FALSE
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#define SPC5_ICU_USE_SMOD4 FALSE
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#define SPC5_ICU_USE_SMOD5 FALSE
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#define SPC5_ICU_ETIMER0_PRIORITY 7
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#define SPC5_ICU_ETIMER0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_ICU_ETIMER0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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#define SPC5_ICU_USE_SMOD6 FALSE
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#define SPC5_ICU_USE_SMOD7 FALSE
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#define SPC5_ICU_USE_SMOD8 FALSE
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#define SPC5_ICU_USE_SMOD9 FALSE
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#define SPC5_ICU_USE_SMOD10 FALSE
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#define SPC5_ICU_USE_SMOD11 FALSE
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#define SPC5_ICU_ETIMER1_PRIORITY 7
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#define SPC5_ICU_ETIMER1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_ICU_ETIMER1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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/*
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* SPI driver system settings.
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*/
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#define SPC5_SPI_USE_DSPI0 FALSE
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#define SPC5_SPI_USE_DSPI1 FALSE
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#define SPC5_SPI_USE_DSPI2 FALSE
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#define SPC5_SPI_USE_DSPI3 FALSE
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#define SPC5_SPI_USE_DSPI4 FALSE
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#define SPC5_SPI_DSPI0_MCR (SPC5_MCR_PCSIS0 | \
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SPC5_MCR_PCSIS1 | \
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SPC5_MCR_PCSIS2 | \
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SPC5_MCR_PCSIS3 | \
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SPC5_MCR_PCSIS4 | \
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SPC5_MCR_PCSIS5 | \
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SPC5_MCR_PCSIS6 | \
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SPC5_MCR_PCSIS7)
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#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
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SPC5_MCR_PCSIS1 | \
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SPC5_MCR_PCSIS2 | \
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SPC5_MCR_PCSIS3 | \
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SPC5_MCR_PCSIS4 | \
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SPC5_MCR_PCSIS5 | \
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SPC5_MCR_PCSIS6 | \
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SPC5_MCR_PCSIS7)
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#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \
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SPC5_MCR_PCSIS1 | \
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SPC5_MCR_PCSIS2 | \
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SPC5_MCR_PCSIS3 | \
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SPC5_MCR_PCSIS4 | \
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SPC5_MCR_PCSIS5 | \
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SPC5_MCR_PCSIS6 | \
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SPC5_MCR_PCSIS7)
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#define SPC5_SPI_DSPI3_MCR (SPC5_MCR_PCSIS0 | \
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SPC5_MCR_PCSIS1 | \
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SPC5_MCR_PCSIS2 | \
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SPC5_MCR_PCSIS3 | \
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SPC5_MCR_PCSIS4 | \
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SPC5_MCR_PCSIS5 | \
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SPC5_MCR_PCSIS6 | \
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SPC5_MCR_PCSIS7)
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#define SPC5_SPI_DSPI4_MCR (SPC5_MCR_PCSIS0 | \
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SPC5_MCR_PCSIS1 | \
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SPC5_MCR_PCSIS2 | \
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SPC5_MCR_PCSIS3 | \
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SPC5_MCR_PCSIS4 | \
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SPC5_MCR_PCSIS5 | \
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SPC5_MCR_PCSIS6 | \
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SPC5_MCR_PCSIS7)
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2013-06-17 07:01:48 +00:00
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#define SPC5_SPI_DSPI0_TX1_DMA_CH_ID 4
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#define SPC5_SPI_DSPI0_TX2_DMA_CH_ID 5
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#define SPC5_SPI_DSPI0_RX_DMA_CH_ID 6
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#define SPC5_SPI_DSPI1_TX1_DMA_CH_ID 7
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#define SPC5_SPI_DSPI1_TX2_DMA_CH_ID 8
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#define SPC5_SPI_DSPI1_RX_DMA_CH_ID 9
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#define SPC5_SPI_DSPI2_TX1_DMA_CH_ID 10
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#define SPC5_SPI_DSPI2_TX2_DMA_CH_ID 11
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#define SPC5_SPI_DSPI2_RX_DMA_CH_ID 12
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#define SPC5_SPI_DSPI3_TX1_DMA_CH_ID 13
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#define SPC5_SPI_DSPI3_TX2_DMA_CH_ID 14
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#define SPC5_SPI_DSPI3_RX_DMA_CH_ID 15
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#define SPC5_SPI_DSPI4_TX1_DMA_CH_ID 1
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#define SPC5_SPI_DSPI4_TX2_DMA_CH_ID 2
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#define SPC5_SPI_DSPI4_RX_DMA_CH_ID 3
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2013-06-15 16:38:10 +00:00
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#define SPC5_SPI_DSPI0_DMA_IRQ_PRIO 10
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#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
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#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
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#define SPC5_SPI_DSPI3_DMA_IRQ_PRIO 10
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#define SPC5_SPI_DSPI4_DMA_IRQ_PRIO 10
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#define SPC5_SPI_DSPI0_IRQ_PRIO 10
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#define SPC5_SPI_DSPI1_IRQ_PRIO 10
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#define SPC5_SPI_DSPI2_IRQ_PRIO 10
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#define SPC5_SPI_DSPI3_IRQ_PRIO 10
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#define SPC5_SPI_DSPI4_IRQ_PRIO 10
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#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
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#define SPC5_SPI_DSPI0_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_SPI_DSPI0_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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#define SPC5_SPI_DSPI1_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_SPI_DSPI1_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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#define SPC5_SPI_DSPI2_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_SPI_DSPI2_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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#define SPC5_SPI_DSPI3_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_SPI_DSPI3_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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#define SPC5_SPI_DSPI4_START_PCTL (SPC5_ME_PCTL_RUN(1) | \
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SPC5_ME_PCTL_LP(2))
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#define SPC5_SPI_DSPI4_STOP_PCTL (SPC5_ME_PCTL_RUN(0) | \
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SPC5_ME_PCTL_LP(0))
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