2012-09-21 14:55:10 +00:00
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/*
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2012-11-27 10:14:29 +00:00
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* Licensed under ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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2012-09-21 14:55:10 +00:00
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/**
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2012-12-11 10:27:10 +00:00
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* @file SPC5xx/SIUL_v1/pal_lld.c
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2012-12-12 09:41:58 +00:00
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* @brief SPC5xx SIUL low level driver code.
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2012-09-21 14:55:10 +00:00
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*
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* @addtogroup PAL
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* @{
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*/
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#include "ch.h"
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#include "hal.h"
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/*===========================================================================*/
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2013-02-28 16:23:19 +00:00
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/* Driver local variables and types. */
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2012-09-21 14:55:10 +00:00
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/*===========================================================================*/
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2012-12-12 09:41:58 +00:00
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#if defined(SPC5_SIUL_SYSTEM_PINS)
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static const unsigned system_pins[] = {SPC5_SIUL_SYSTEM_PINS};
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2012-11-21 13:47:59 +00:00
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#endif
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2012-09-21 14:55:10 +00:00
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief SPC5xx I/O ports configuration.
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*
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* @param[in] config the STM32 ports configuration
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*
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* @notapi
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*/
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void _pal_lld_init(const PALConfig *config) {
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unsigned i;
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2012-12-12 09:41:58 +00:00
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#if defined(SPC5_SIUL_PCTL)
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2012-11-20 15:53:33 +00:00
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/* SIUL clock gating if present.*/
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2012-12-12 09:41:58 +00:00
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halSPCSetPeripheralClockMode(SPC5_SIUL_PCTL,
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2012-11-20 15:53:33 +00:00
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SPC5_ME_PCTL_RUN(2) | SPC5_ME_PCTL_LP(2));
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#endif
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2012-09-27 08:41:07 +00:00
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/* Initialize PCR registers for undefined pads.*/
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2012-12-12 09:41:58 +00:00
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for (i = 0; i < SPC5_SIUL_NUM_PCRS; i++) {
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#if defined(SPC5_SIUL_SYSTEM_PINS)
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2012-11-21 13:47:59 +00:00
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/* Handling the case where some SIU pins are not meant to be reprogrammed,
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for example JTAG pins.*/
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unsigned j;
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for (j = 0; j < sizeof system_pins; j++) {
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if (i == system_pins[j])
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goto skip;
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}
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2012-09-21 14:55:10 +00:00
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SIU.PCR[i].R = config->default_mode;
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2012-11-21 13:47:59 +00:00
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skip:
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;
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#else
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SIU.PCR[i].R = config->default_mode;
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#endif
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}
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2012-09-21 14:55:10 +00:00
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2012-09-27 08:41:07 +00:00
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/* Initialize PADSEL registers.*/
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2012-12-12 09:41:58 +00:00
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for (i = 0; i < SPC5_SIUL_NUM_PADSELS; i++)
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2012-09-27 08:41:07 +00:00
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SIU.PSMI[i].R = config->padsels[i];
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/* Initialize PCR registers for defined pads.*/
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2012-09-21 14:55:10 +00:00
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i = 0;
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2012-09-26 15:31:12 +00:00
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while (config->inits[i].pcr_value != 0) {
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SIU.GPDO[config->inits[i].pcr_index].R = config->inits[i].gpdo_value;
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SIU.PCR[config->inits[i].pcr_index].R = config->inits[i].pcr_value;
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2012-09-21 14:55:10 +00:00
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i++;
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}
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}
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2012-09-27 12:11:57 +00:00
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/**
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* @brief Reads a group of bits.
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*
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* @param[in] port port identifier
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* @param[in] mask group mask
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* @param[in] offset group bit offset within the port
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* @return The group logical states.
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*
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* @notapi
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*/
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ioportmask_t _pal_lld_readgroup(ioportid_t port,
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ioportmask_t mask,
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uint_fast8_t offset) {
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(void)port;
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(void)mask;
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(void)offset;
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return 0;
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}
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/**
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* @brief Writes a group of bits.
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*
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* @param[in] port port identifier
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* @param[in] mask group mask
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* @param[in] offset group bit offset within the port
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* @param[in] bits bits to be written. Values exceeding the group width
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* are masked.
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*
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* @notapi
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*/
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void _pal_lld_writegroup(ioportid_t port,
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ioportmask_t mask,
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uint_fast8_t offset,
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ioportmask_t bits) {
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(void)port;
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(void)mask;
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(void)offset;
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(void)bits;
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}
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2012-09-21 14:55:10 +00:00
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/**
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* @brief Pads mode setup.
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* @details This function programs a pads group belonging to the same port
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* with the specified mode.
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*
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* @param[in] port the port identifier
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* @param[in] mask the group mask
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* @param[in] mode the mode
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*
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* @notapi
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*/
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void _pal_lld_setgroupmode(ioportid_t port,
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ioportmask_t mask,
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iomode_t mode) {
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2012-09-27 12:11:57 +00:00
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unsigned pcr_index = (unsigned)(port * PAL_IOPORTS_WIDTH);
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ioportmask_t m1 = 0x8000;
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while (m1) {
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if (mask & m1)
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SIU.PCR[pcr_index].R = mode;
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m1 >>= 1;
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++pcr_index;
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}
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2012-09-21 14:55:10 +00:00
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}
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#endif /* HAL_USE_PAL */
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/** @} */
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