481 lines
15 KiB
C
481 lines
15 KiB
C
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file SPC5xx/ADC_v1/adc_lld.c
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* @brief ADC Driver subsystem low level driver source.
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*
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* @addtogroup ADC
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* @{
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*/
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#include "hal.h"
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#if HAL_USE_ADC || defined(__DOXYGEN__)
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/* Some forward declarations.*/
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static void adc_serve_adc_irq(edma_channel_t channel, void *p);
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static void adc_serve_dma_error_irq(edma_channel_t channel,
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void *p,
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uint32_t esr);
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/**
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* @brief ADC1 driver identifier.
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*/
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#if SPC5_ADC_USE_ADC0 || defined(__DOXYGEN__)
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ADCDriver ADCD1;
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#endif
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#if SPC5_ADC_USE_ADC1 || defined(__DOXYGEN__)
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ADCDriver ADCD2;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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#if SPC5_ADC_USE_ADC0 || defined(__DOXYGEN__)
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/**
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* @brief DMA configuration for ADC0.
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*/
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static const edma_channel_config_t adc_adc0_dma_config = {
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SPC5_ADC_ADC0_DMA_CH_ID,
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SPC5_ADC0_DMA_DEV_ID,
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SPC5_ADC_ADC0_DMA_IRQ_PRIO,
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adc_serve_adc_irq, adc_serve_dma_error_irq, &ADCD1
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};
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#endif /* SPC5_ADC_USE_ADC0 */
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#if SPC5_ADC_USE_ADC1 || defined(__DOXYGEN__)
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/**
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* @brief DMA configuration for ADC1.
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*/
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static const edma_channel_config_t adc_adc1_dma_config = {
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SPC5_ADC_ADC1_DMA_CH_ID,
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SPC5_ADC1_DMA_DEV_ID,
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SPC5_ADC_ADC1_DMA_IRQ_PRIO,
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adc_serve_adc_irq, adc_serve_dma_error_irq, &ADCD2
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};
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#endif /* SPC5_ADC_USE_ADC1 */
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/*===========================================================================*/
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/* Driver local functions and macros. */
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/*===========================================================================*/
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/**
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* @brief Unsigned two's complement.
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*
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* @param[in] n the value to be complemented
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*
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* @notapi
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*/
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#define CPL2(n) ((~(uint32_t)(n)) + 1)
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/**
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* @brief Shared ISR for ADC events.
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*
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* @param[in] channel the channel number
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* @param[in] p parameter for the registered function
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*
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* @notapi
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*/
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static void adc_serve_adc_irq(edma_channel_t channel, void *p) {
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ADCDriver *adcp = (ADCDriver *)p;
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edma_tcd_t *tcdp = edmaGetTCD(channel);
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if (adcp->grpp != NULL) {
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if ((tcdp->word[5] >> 16) != (tcdp->word[7] >> 16)) {
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/* Half transfer processing.*/
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_adc_isr_half_code(adcp);
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}
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else {
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/* Re-starting DMA channel if in circular mode.*/
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if (adcp->grpp->circular) {
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edmaChannelStart(adcp->adc_dma_channel);
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}
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/* Transfer complete processing.*/
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_adc_isr_full_code(adcp);
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}
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}
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}
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/**
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* @brief Shared ISR for DMA error events.
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*
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* @param[in] channel the channel number
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* @param[in] p parameter for the registered function
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* @param[in] esr content of the ESR register
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*
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* @notapi
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*/
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static void adc_serve_dma_error_irq(edma_channel_t channel,
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void *p,
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uint32_t esr) {
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ADCDriver *adcp = (ADCDriver *)p;
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(void)channel;
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(void)esr;
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_adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
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}
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/**
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* @brief ADC ISR service routine.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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* @param[in] isr content of the ISR register
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*/
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static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) {
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/* It could be a spurious interrupt caused by overflows after DMA disabling,
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just ignore it in this case.*/
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if (adcp->grpp != NULL) {
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if (isr & ADC_ISR_AWD0_LT) {
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/* Analog watchdog error.*/
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_adc_isr_error_code(adcp, ADC_ERR_AWD0_LT);
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}
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if (isr & ADC_ISR_AWD1_LT) {
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/* Analog watchdog error.*/
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_adc_isr_error_code(adcp, ADC_ERR_AWD1_LT);
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}
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if (isr & ADC_ISR_AWD2_LT) {
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/* Analog watchdog error.*/
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_adc_isr_error_code(adcp, ADC_ERR_AWD2_LT);
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}
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if (isr & ADC_ISR_AWD3_LT) {
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/* Analog watchdog error.*/
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_adc_isr_error_code(adcp, ADC_ERR_AWD3_LT);
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}
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if (isr & ADC_ISR_AWD0_HT) {
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/* Analog watchdog error.*/
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_adc_isr_error_code(adcp, ADC_ERR_AWD0_HT);
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}
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if (isr & ADC_ISR_AWD1_HT) {
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/* Analog watchdog error.*/
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_adc_isr_error_code(adcp, ADC_ERR_AWD1_HT);
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}
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if (isr & ADC_ISR_AWD2_HT) {
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/* Analog watchdog error.*/
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_adc_isr_error_code(adcp, ADC_ERR_AWD2_HT);
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}
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if (isr & ADC_ISR_AWD3_HT) {
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/* Analog watchdog error.*/
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_adc_isr_error_code(adcp, ADC_ERR_AWD3_HT);
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}
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}
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}
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if SPC5_ADC_USE_ADC0
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#if !defined(SPC5_ADC0_WD_HANDLER)
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#error "SPC5_ADC0_WD_HANDLER not defined"
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#endif
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/**
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* @brief ADC0 Watch Dog interrupt handler.
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* @note It is assumed that the various sources are only activated if the
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* associated callback pointer is not equal to @p NULL in order to not
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* perform an extra check in a potentially critical interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(SPC5_ADC0_WD_HANDLER) {
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uint32_t isr;
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OSAL_IRQ_PROLOGUE();
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isr = ADCD1.adc_tagp->WTISR.R;
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adc_lld_serve_interrupt(&ADCD1, isr);
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OSAL_IRQ_EPILOGUE();
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}
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#endif /* SPC5_ADC_USE_ADC0 */
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#if SPC5_ADC_USE_ADC1
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#if !defined(SPC5_ADC1_WD_HANDLER)
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#error "SPC5_ADC1_WD_HANDLER not defined"
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#endif
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/**
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* @brief ADC1 Watch Dog interrupt handler.
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* @note It is assumed that the various sources are only activated if the
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* associated callback pointer is not equal to @p NULL in order to not
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* perform an extra check in a potentially critical interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(SPC5_ADC1_WD_HANDLER) {
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uint32_t isr;
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OSAL_IRQ_PROLOGUE();
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isr = ADCD2.adc_tagp->WTISR.R;
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adc_lld_serve_interrupt(&ADCD2, isr);
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OSAL_IRQ_EPILOGUE();
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}
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#endif /* SPC5_ADC_USE_ADC1 */
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level ADC driver initialization.
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*
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* @notapi
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*/
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void adc_lld_init(void) {
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#if SPC5_ADC_USE_ADC0
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/* Driver initialization.*/
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adcObjectInit(&ADCD1);
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ADCD1.adc_dma_channel = EDMA_ERROR;
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ADCD1.adc_tagp = &SPC5_ADC_0;
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#endif /* SPC5_ADC_USE_ADC0 */
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#if SPC5_ADC_USE_ADC1
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/* Driver initialization.*/
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adcObjectInit(&ADCD2);
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ADCD2.adc_dma_channel = EDMA_ERROR;
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ADCD2.adc_tagp = &SPC5_ADC_1;
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#endif /* SPC5_ADC_USE_ADC1 */
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#if SPC5_ADC_USE_ADC0
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INTC.PSR[SPC5_ADC0_EOC_NUMBER].R = SPC5_ADC_ADC0_EOC_PRIORITY;
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INTC.PSR[SPC5_ADC0_ER_NUMBER].R = SPC5_ADC_ADC0_ER_PRIORITY;
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INTC.PSR[SPC5_ADC0_WD_NUMBER].R = SPC5_ADC_ADC0_WD_PRIORITY;
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#endif
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#if SPC5_ADC_USE_ADC1
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INTC.PSR[SPC5_ADC1_EOC_NUMBER].R = SPC5_ADC_ADC1_EOC_PRIORITY;
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INTC.PSR[SPC5_ADC1_ER_NUMBER].R = SPC5_ADC_ADC1_ER_PRIORITY;
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INTC.PSR[SPC5_ADC1_WD_NUMBER].R = SPC5_ADC_ADC1_WD_PRIORITY;
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#endif
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}
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/**
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* @brief Configures and activates the ADC peripheral.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_start(ADCDriver *adcp) {
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if (adcp->state == ADC_STOP) {
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/* Enables the peripheral.*/
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#if SPC5_ADC_USE_ADC0
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if (&ADCD1 == adcp) {
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adcp->adc_dma_channel = edmaChannelAllocate(&adc_adc0_dma_config);
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}
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#endif /* SPC5_ADC_USE_ADC0 */
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#if SPC5_ADC_USE_ADC1
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if (&ADCD2 == adcp) {
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adcp->adc_dma_channel = edmaChannelAllocate(&adc_adc1_dma_config);
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}
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#endif /* SPC5_ADC_USE_ADC1 */
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osalDbgAssert((adcp->adc_dma_channel != EDMA_ERROR),
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"adc_lld_start(), #1", "DMA channel cannot be allocated");
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/* Configures the peripheral.*/
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/* Sets ADC0 Clock.*/
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#if SPC5_ADC_USE_ADC0
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if (&ADCD1 == adcp) {
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halSPCSetPeripheralClockMode(SPC5_ADC0_PCTL,
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SPC5_ADC_ADC0_START_PCTL);
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}
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#endif
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/* Sets ADC1 Clock.*/
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#if SPC5_ADC_USE_ADC1
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if (&ADCD2 == adcp) {
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halSPCSetPeripheralClockMode(SPC5_ADC1_PCTL,
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SPC5_ADC_ADC1_START_PCTL);
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}
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#endif
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/* Sets ADC Normal Mode.*/
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adcp->adc_tagp->MCR.B.PWDN = 0;
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/* Sets analog clock.*/
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if (adcp->config->clock == HALF_PERIPHERAL_SET_CLOCK_FREQUENCY) {
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adcp->adc_tagp->MCR.B.ADCLKSEL = 0;
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} else if (adcp->config->clock == PERIPHERAL_SET_CLOCK_FREQUENCY) {
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adcp->adc_tagp->MCR.B.ADCLKSEL = 1;
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}
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/* Sets MCR Register.*/
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adcp->adc_tagp->MCR.R = ADC_MCR_OWREN | ADC_MCR_MODE;
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}
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}
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/**
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* @brief Deactivates the ADC peripheral.
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*
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* @param[in] adcp pointer to the @p ADCDriver object
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*
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* @notapi
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*/
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void adc_lld_stop(ADCDriver *adcp) {
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if (adcp->state == ADC_READY) {
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/* Resets the peripheral.*/
|
|||
|
|
|
|||
|
|
/* Releases the allocated DMA channel.*/
|
|||
|
|
edmaChannelRelease(adcp->adc_dma_channel);
|
|||
|
|
|
|||
|
|
/* Clears thresholds<64> values and deactives watchdog threshold interrupts.*/
|
|||
|
|
if (adcp->grpp->wtimr != 0) {
|
|||
|
|
adcp->adc_tagp->TRC[0].R = 0;
|
|||
|
|
adcp->adc_tagp->TRC[1].R = 0;
|
|||
|
|
adcp->adc_tagp->TRC[2].R = 0;
|
|||
|
|
adcp->adc_tagp->TRC[3].R = 0;
|
|||
|
|
adcp->adc_tagp->THRHLR[0].R = 0;
|
|||
|
|
adcp->adc_tagp->THRHLR[1].R = 0;
|
|||
|
|
adcp->adc_tagp->THRHLR[2].R = 0;
|
|||
|
|
adcp->adc_tagp->THRHLR[3].R = 0;
|
|||
|
|
adcp->adc_tagp->WTIMR.R = 0;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Deactives ADC channels and the ADC DMA channels.*/
|
|||
|
|
adcp->adc_tagp->NCMR[0].R = 0;
|
|||
|
|
adcp->adc_tagp->DMAR[0].R = 0;
|
|||
|
|
|
|||
|
|
/* Puts the ADC Peripheral in Power-Down Mode.*/
|
|||
|
|
adcp->adc_tagp->MCR.B.PWDN = 1U;
|
|||
|
|
|
|||
|
|
/* Disables the peripheral.*/
|
|||
|
|
#if SPC5_ADC_USE_ADC0
|
|||
|
|
if (&ADCD1 == adcp) {
|
|||
|
|
halSPCSetPeripheralClockMode(SPC5_ADC0_PCTL,
|
|||
|
|
SPC5_ADC_ADC0_STOP_PCTL);
|
|||
|
|
}
|
|||
|
|
#endif
|
|||
|
|
|
|||
|
|
#if SPC5_ADC_USE_ADC1
|
|||
|
|
if (&ADCD2 == adcp) {
|
|||
|
|
halSPCSetPeripheralClockMode(SPC5_ADC1_PCTL,
|
|||
|
|
SPC5_ADC_ADC1_STOP_PCTL);
|
|||
|
|
}
|
|||
|
|
#endif
|
|||
|
|
}
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @brief Starts an ADC conversion.
|
|||
|
|
*
|
|||
|
|
* @param[in] adcp pointer to the @p ADCDriver object
|
|||
|
|
*
|
|||
|
|
* @notapi
|
|||
|
|
*/
|
|||
|
|
void adc_lld_start_conversion(ADCDriver *adcp) {
|
|||
|
|
uint8_t i;
|
|||
|
|
|
|||
|
|
//osalDbgAssert(adcp->grpp->num_channels*2 >= adcp->depth,
|
|||
|
|
// "adc_lld_start_conversion(), #1", "too many elements");
|
|||
|
|
|
|||
|
|
/* Active DMA.*/
|
|||
|
|
adcp->adc_tagp->DMAE.R = ADC_DMAE_DMAEN;
|
|||
|
|
|
|||
|
|
/* Setting up DMA TCD parameters.*/
|
|||
|
|
edmaChannelSetup(adcp->adc_dma_channel, /* channel. */
|
|||
|
|
adcp->adc_tagp->CDR[adcp->grpp->init_channel].B.CDATA, /* src. */
|
|||
|
|
adcp->samples, /* dst. */
|
|||
|
|
4, /* soff, advance by four. */
|
|||
|
|
2, /* doff, advance by two. */
|
|||
|
|
1, /* ssize, 16 bits transfers.*/
|
|||
|
|
1, /* dsize, 16 bits transfers.*/
|
|||
|
|
2, /* nbytes, always two. */
|
|||
|
|
(uint32_t)adcp->grpp->num_channels *
|
|||
|
|
(uint32_t)adcp->depth, /* iter. */
|
|||
|
|
CPL2((uint32_t)adcp->grpp->num_channels * 4), /* slast. */
|
|||
|
|
CPL2((uint32_t)adcp->grpp->num_channels *
|
|||
|
|
(uint32_t)adcp->depth *
|
|||
|
|
sizeof(adcsample_t)), /* dlast. */
|
|||
|
|
EDMA_TCD_MODE_DREQ | EDMA_TCD_MODE_INT_END |
|
|||
|
|
((adcp->depth > 1) ? EDMA_TCD_MODE_INT_HALF: 0)); /* mode. */
|
|||
|
|
|
|||
|
|
/* Sets thresholds<64> values and active watchdog threshold interrupts if any.*/
|
|||
|
|
if (adcp->grpp->wtimr != 0) {
|
|||
|
|
adcp->adc_tagp->TRC[0].R = adcp->grpp->trcr[0];
|
|||
|
|
adcp->adc_tagp->TRC[1].R = adcp->grpp->trcr[1];
|
|||
|
|
adcp->adc_tagp->TRC[2].R = adcp->grpp->trcr[2];
|
|||
|
|
adcp->adc_tagp->TRC[3].R = adcp->grpp->trcr[3];
|
|||
|
|
adcp->adc_tagp->THRHLR[0].R = adcp->grpp->thrhlr[0];
|
|||
|
|
adcp->adc_tagp->THRHLR[1].R = adcp->grpp->thrhlr[1];
|
|||
|
|
adcp->adc_tagp->THRHLR[2].R = adcp->grpp->thrhlr[2];
|
|||
|
|
adcp->adc_tagp->THRHLR[3].R = adcp->grpp->thrhlr[3];
|
|||
|
|
adcp->adc_tagp->WTIMR.R = adcp->grpp->wtimr;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Active ADC channels for the conversion and sets the ADC DMA channels.*/
|
|||
|
|
for (i = adcp->grpp->init_channel; i <= adcp->grpp->final_channel; i++) {
|
|||
|
|
adcp->adc_tagp->NCMR[0].R |= 1U << i;
|
|||
|
|
adcp->adc_tagp->DMAR[0].R |= 1U << i;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/* Sets ADC conversion timing register.*/
|
|||
|
|
adcp->adc_tagp->CTR[0].R = adcp->grpp->ctr;
|
|||
|
|
|
|||
|
|
/* Starting DMA channels.*/
|
|||
|
|
edmaChannelStart(adcp->adc_dma_channel);
|
|||
|
|
|
|||
|
|
/* Starts conversion.*/
|
|||
|
|
adcp->adc_tagp->MCR.B.NSTART = 1U;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
/**
|
|||
|
|
* @brief Stops an ongoing conversion.
|
|||
|
|
*
|
|||
|
|
* @param[in] adcp pointer to the @p ADCDriver object
|
|||
|
|
*
|
|||
|
|
* @notapi
|
|||
|
|
*/
|
|||
|
|
void adc_lld_stop_conversion(ADCDriver *adcp) {
|
|||
|
|
|
|||
|
|
/* Stop DMA channel.*/
|
|||
|
|
edmaChannelStop(adcp->adc_dma_channel);
|
|||
|
|
|
|||
|
|
/* Stops conversion.*/
|
|||
|
|
adcp->adc_tagp->MCR.B.NSTART = 0;
|
|||
|
|
|
|||
|
|
/* Disables Interrupts and DMA.*/
|
|||
|
|
adcp->adc_tagp->WTIMR.R = 0;
|
|||
|
|
adcp->adc_tagp->DMAE.R = ADC_DMAE_DMAEN;
|
|||
|
|
|
|||
|
|
/* Clears all Interrupts.*/
|
|||
|
|
adcp->adc_tagp->WTISR.R = 0;
|
|||
|
|
}
|
|||
|
|
|
|||
|
|
#endif /* HAL_USE_ADC */
|
|||
|
|
|
|||
|
|
/** @} */
|