2013-06-15 16:38:10 +00:00
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/*
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SPC5 HAL - Copyright (C) 2013 STMicroelectronics
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/*
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* SPC563Mxx drivers configuration.
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* The following settings override the default settings present in
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* the various device driver implementation headers.
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* Note that the settings for each driver only have effect if the whole
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* driver is enabled in halconf.h.
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*
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* IRQ priorities:
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* 1...15 Lowest...Highest.
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* DMA priorities:
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* 0...15 Highest...Lowest.
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*/
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#define SPC563Mxx_MCUCONF
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/*
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* HAL driver system settings.
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*/
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#define SPC5_NO_INIT FALSE
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#define SPC5_CLK_BYPASS FALSE
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#define SPC5_ALLOW_OVERCLOCK FALSE
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#define SPC5_CLK_PREDIV_VALUE 2
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#define SPC5_CLK_MFD_VALUE 80
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#define SPC5_CLK_RFD SPC5_RFD_DIV4
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#define SPC5_FLASH_BIUCR (BIUCR_BANK1_TOO | \
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BIUCR_MASTER4_PREFETCH | \
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BIUCR_MASTER0_PREFETCH | \
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BIUCR_DPFEN | \
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BIUCR_IPFEN | \
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BIUCR_PFLIM_ON_MISS | \
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BIUCR_BFEN)
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2013-06-22 07:51:40 +00:00
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#define SPC5_EMIOS_GPRE_VALUE 20
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2013-06-15 16:38:10 +00:00
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/*
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* EDMA driver settings.
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*/
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#define SPC5_EDMA_CR_SETTING (EDMA_CR_GRP3PRI(3) | \
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EDMA_CR_GRP2PRI(2) | \
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EDMA_CR_GRP1PRI(1) | \
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EDMA_CR_GRP0PRI(0) | \
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EDMA_CR_ERGA)
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#define SPC5_EDMA_GROUP0_PRIORITIES \
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
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#define SPC5_EDMA_GROUP1_PRIORITIES \
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
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2013-06-18 14:20:32 +00:00
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#define SPC5_EDMA_ERROR_IRQ_PRIO 12
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2013-06-15 16:38:10 +00:00
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#define SPC5_EDMA_ERROR_HANDLER() chSysHalt()
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/*
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* ADC driver settings.
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*/
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#define SPC5_ADC_USE_ADC0_Q0 FALSE
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#define SPC5_ADC_USE_ADC0_Q1 FALSE
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#define SPC5_ADC_USE_ADC0_Q2 FALSE
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#define SPC5_ADC_USE_ADC1_Q3 FALSE
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#define SPC5_ADC_USE_ADC1_Q4 FALSE
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#define SPC5_ADC_USE_ADC1_Q5 FALSE
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#define SPC5_ADC_FIFO0_DMA_IRQ_PRIO 12
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#define SPC5_ADC_FIFO1_DMA_IRQ_PRIO 12
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#define SPC5_ADC_FIFO2_DMA_IRQ_PRIO 12
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#define SPC5_ADC_FIFO3_DMA_IRQ_PRIO 12
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#define SPC5_ADC_FIFO4_DMA_IRQ_PRIO 12
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#define SPC5_ADC_FIFO5_DMA_IRQ_PRIO 12
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#define SPC5_ADC_CR_CLK_PS ADC_CR_CLK_PS(5)
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#define SPC5_ADC_PUDCR {ADC_PUDCR_NONE, \
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ADC_PUDCR_NONE, \
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ADC_PUDCR_NONE, \
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ADC_PUDCR_NONE, \
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ADC_PUDCR_NONE, \
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ADC_PUDCR_NONE, \
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ADC_PUDCR_NONE, \
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ADC_PUDCR_NONE}
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/*
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* SERIAL driver system settings.
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*/
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#define SPC5_USE_ESCIA TRUE
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#define SPC5_USE_ESCIB TRUE
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#define SPC5_ESCIA_PRIORITY 8
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#define SPC5_ESCIB_PRIORITY 8
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/*
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* SPI driver system settings.
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*/
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#define SPC5_SPI_USE_DSPI1 TRUE
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#define SPC5_SPI_USE_DSPI2 TRUE
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#define SPC5_SPI_DSPI1_MCR (SPC5_MCR_PCSIS0 | \
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SPC5_MCR_PCSIS1 | \
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SPC5_MCR_PCSIS2 | \
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SPC5_MCR_PCSIS3 | \
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SPC5_MCR_PCSIS4 | \
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SPC5_MCR_PCSIS5 | \
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SPC5_MCR_PCSIS6 | \
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SPC5_MCR_PCSIS7)
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#define SPC5_SPI_DSPI2_MCR (SPC5_MCR_PCSIS0 | \
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SPC5_MCR_PCSIS1 | \
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SPC5_MCR_PCSIS2 | \
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SPC5_MCR_PCSIS3 | \
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SPC5_MCR_PCSIS4 | \
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SPC5_MCR_PCSIS5 | \
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SPC5_MCR_PCSIS6 | \
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SPC5_MCR_PCSIS7)
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#define SPC5_SPI_DSPI1_DMA_IRQ_PRIO 10
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#define SPC5_SPI_DSPI2_DMA_IRQ_PRIO 10
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#define SPC5_SPI_DSPI1_IRQ_PRIO 10
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#define SPC5_SPI_DSPI2_IRQ_PRIO 10
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#define SPC5_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
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