2013-08-04 13:38:53 +00:00
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/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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/**
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* @file STM32/USARTv2/serial_lld.c
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* @brief STM32 low level serial driver code.
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*
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* @addtogroup SERIAL
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* @{
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*/
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#include "hal.h"
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#if HAL_USE_SERIAL || defined(__DOXYGEN__)
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/*===========================================================================*/
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/* Driver local definitions. */
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/*===========================================================================*/
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/*===========================================================================*/
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/* Driver exported variables. */
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/*===========================================================================*/
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/** @brief USART1 serial driver identifier.*/
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#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
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SerialDriver SD1;
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#endif
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/** @brief USART2 serial driver identifier.*/
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#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
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SerialDriver SD2;
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#endif
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/** @brief USART3 serial driver identifier.*/
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#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
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SerialDriver SD3;
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#endif
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/** @brief UART4 serial driver identifier.*/
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#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
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SerialDriver SD4;
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#endif
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/** @brief UART5 serial driver identifier.*/
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#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
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SerialDriver SD5;
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#endif
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/** @brief USART6 serial driver identifier.*/
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#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
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SerialDriver SD6;
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#endif
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/*===========================================================================*/
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/* Driver local variables and types. */
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/*===========================================================================*/
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/** @brief Driver default configuration.*/
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static const SerialConfig default_config =
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{
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SERIAL_DEFAULT_BITRATE,
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0,
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USART_CR2_STOP1_BITS | USART_CR2_LINEN,
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0
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};
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/*===========================================================================*/
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/* Driver local functions. */
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/*===========================================================================*/
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/**
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* @brief USART initialization.
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* @details This function must be invoked with interrupts disabled.
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*
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* @param[in] sdp pointer to a @p SerialDriver object
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* @param[in] config the architecture-dependent serial driver configuration
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*/
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static void usart_init(SerialDriver *sdp, const SerialConfig *config) {
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USART_TypeDef *u = sdp->usart;
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/* Baud rate setting.*/
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u->BRR = (uint16_t)(sdp->clock / config->speed);
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/* Note that some bits are enforced.*/
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u->CR2 = config->cr2 | USART_CR2_LBDIE;
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u->CR3 = config->cr3 | USART_CR3_EIE;
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u->CR1 = config->cr1 | USART_CR1_UE | USART_CR1_PEIE |
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USART_CR1_RXNEIE | USART_CR1_TE |
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USART_CR1_RE;
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u->ICR = 0xFFFFFFFF;
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}
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/**
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* @brief USART de-initialization.
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* @details This function must be invoked with interrupts disabled.
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*
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* @param[in] u pointer to an USART I/O block
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*/
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static void usart_deinit(USART_TypeDef *u) {
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u->CR1 = 0;
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u->CR2 = 0;
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u->CR3 = 0;
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}
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/**
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* @brief Error handling routine.
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*
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* @param[in] sdp pointer to a @p SerialDriver object
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* @param[in] isr USART ISR register value
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*/
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static void set_error(SerialDriver *sdp, uint32_t isr) {
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eventflags_t sts = 0;
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if (isr & USART_ISR_ORE)
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sts |= SD_OVERRUN_ERROR;
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if (isr & USART_ISR_PE)
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sts |= SD_PARITY_ERROR;
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if (isr & USART_ISR_FE)
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sts |= SD_FRAMING_ERROR;
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if (isr & USART_ISR_NE)
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sts |= SD_NOISE_ERROR;
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osalSysLockFromISR();
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chnAddFlagsI(sdp, sts);
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osalSysUnlockFromISR();
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}
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/**
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* @brief Common IRQ handler.
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*
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* @param[in] sdp communication channel associated to the USART
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*/
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static void serve_interrupt(SerialDriver *sdp) {
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USART_TypeDef *u = sdp->usart;
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uint32_t cr1 = u->CR1;
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uint32_t isr;
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/* Reading and clearing status.*/
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isr = u->ISR;
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u->ICR = isr;
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/* Error condition detection.*/
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if (isr & (USART_ISR_ORE | USART_ISR_NE | USART_ISR_FE | USART_ISR_PE))
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set_error(sdp, isr);
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/* Special case, LIN break detection.*/
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if (isr & USART_ISR_LBD) {
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osalSysLockFromISR();
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chnAddFlagsI(sdp, SD_BREAK_DETECTED);
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osalSysUnlockFromISR();
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}
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/* Data available.*/
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if (isr & USART_ISR_RXNE) {
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osalSysLockFromISR();
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sdIncomingDataI(sdp, (uint8_t)u->RDR);
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osalSysUnlockFromISR();
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}
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/* Transmission buffer empty.*/
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if ((cr1 & USART_CR1_TXEIE) && (isr & USART_ISR_TXE)) {
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msg_t b;
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osalSysLockFromISR();
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b = oqGetI(&sdp->oqueue);
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if (b < Q_OK) {
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chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY);
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u->CR1 = (cr1 & ~USART_CR1_TXEIE) | USART_CR1_TCIE;
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}
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else
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u->TDR = b;
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osalSysUnlockFromISR();
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}
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/* Physical transmission end.*/
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if (isr & USART_ISR_TC) {
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osalSysLockFromISR();
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chnAddFlagsI(sdp, CHN_TRANSMISSION_END);
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osalSysUnlockFromISR();
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u->CR1 = cr1 & ~USART_CR1_TCIE;
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}
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}
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#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
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2013-08-09 13:43:56 +00:00
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static void notify1(io_queue_t *qp) {
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2013-08-04 13:38:53 +00:00
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(void)qp;
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USART1->CR1 |= USART_CR1_TXEIE;
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}
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#endif
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#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
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2013-08-09 13:43:56 +00:00
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static void notify2(io_queue_t *qp) {
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2013-08-04 13:38:53 +00:00
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(void)qp;
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USART2->CR1 |= USART_CR1_TXEIE;
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}
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#endif
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#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
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2013-08-09 13:43:56 +00:00
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static void notify3(io_queue_t *qp) {
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2013-08-04 13:38:53 +00:00
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(void)qp;
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USART3->CR1 |= USART_CR1_TXEIE;
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}
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#endif
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#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
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2013-08-09 13:43:56 +00:00
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static void notify4(io_queue_t *qp) {
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2013-08-04 13:38:53 +00:00
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(void)qp;
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UART4->CR1 |= USART_CR1_TXEIE;
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}
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#endif
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#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
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2013-08-09 13:43:56 +00:00
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static void notify5(io_queue_t *qp) {
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2013-08-04 13:38:53 +00:00
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(void)qp;
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UART5->CR1 |= USART_CR1_TXEIE;
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}
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#endif
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#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
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2013-08-09 13:43:56 +00:00
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static void notify6(io_queue_t *qp) {
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2013-08-04 13:38:53 +00:00
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(void)qp;
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USART6->CR1 |= USART_CR1_TXEIE;
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}
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#endif
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/*===========================================================================*/
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/* Driver interrupt handlers. */
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/*===========================================================================*/
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#if STM32_SERIAL_USE_USART1 || defined(__DOXYGEN__)
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#if !defined(STM32_USART1_HANDLER)
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#error "STM32_USART1_HANDLER not defined"
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#endif
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/**
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* @brief USART1 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_USART1_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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serve_interrupt(&SD1);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if STM32_SERIAL_USE_USART2 || defined(__DOXYGEN__)
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#if !defined(STM32_USART2_HANDLER)
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#error "STM32_USART2_HANDLER not defined"
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#endif
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/**
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* @brief USART2 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_USART2_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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serve_interrupt(&SD2);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if STM32_SERIAL_USE_USART3 || defined(__DOXYGEN__)
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#if !defined(STM32_USART3_HANDLER)
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#error "STM32_USART3_HANDLER not defined"
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#endif
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/**
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* @brief USART3 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_USART3_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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serve_interrupt(&SD3);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if STM32_SERIAL_USE_UART4 || defined(__DOXYGEN__)
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#if !defined(STM32_UART4_HANDLER)
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#error "STM32_UART4_HANDLER not defined"
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#endif
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/**
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* @brief UART4 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_UART4_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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serve_interrupt(&SD4);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if STM32_SERIAL_USE_UART5 || defined(__DOXYGEN__)
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#if !defined(STM32_UART5_HANDLER)
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#error "STM32_UART5_HANDLER not defined"
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#endif
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/**
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* @brief UART5 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_UART5_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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serve_interrupt(&SD5);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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#if STM32_SERIAL_USE_USART6 || defined(__DOXYGEN__)
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#if !defined(STM32_USART6_HANDLER)
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#error "STM32_USART6_HANDLER not defined"
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#endif
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/**
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* @brief USART1 interrupt handler.
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*
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* @isr
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*/
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OSAL_IRQ_HANDLER(STM32_USART6_HANDLER) {
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OSAL_IRQ_PROLOGUE();
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serve_interrupt(&SD6);
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OSAL_IRQ_EPILOGUE();
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}
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#endif
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/*===========================================================================*/
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/* Driver exported functions. */
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/*===========================================================================*/
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/**
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* @brief Low level serial driver initialization.
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*
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* @notapi
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*/
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void sd_lld_init(void) {
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#if STM32_SERIAL_USE_USART1
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sdObjectInit(&SD1, NULL, notify1);
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SD1.usart = USART1;
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SD1.clock = STM32_USART1CLK;
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#endif
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#if STM32_SERIAL_USE_USART2
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sdObjectInit(&SD2, NULL, notify2);
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SD2.usart = USART2;
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SD2.clock = STM32_USART2CLK;
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#endif
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#if STM32_SERIAL_USE_USART3
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sdObjectInit(&SD3, NULL, notify3);
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SD3.usart = USART3;
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SD3.clock = STM32_USART3CLK;
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|
|
|
#endif
|
|
|
|
|
|
|
|
#if STM32_SERIAL_USE_UART4
|
|
|
|
sdObjectInit(&SD4, NULL, notify4);
|
|
|
|
SD4.usart = UART4;
|
|
|
|
SD4.clock = STM32_UART4CLK;
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|
|
|
#endif
|
|
|
|
|
|
|
|
#if STM32_SERIAL_USE_UART5
|
|
|
|
sdObjectInit(&SD5, NULL, notify5);
|
|
|
|
SD5.usart = UART5;
|
|
|
|
SD5.clock = STM32_UART5CLK;
|
|
|
|
#endif
|
|
|
|
|
|
|
|
#if STM32_SERIAL_USE_USART6
|
|
|
|
sdObjectInit(&SD6, NULL, notify6);
|
|
|
|
SD6.usart = USART6;
|
|
|
|
SD6.clock = STM32_USART6CLK;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Low level serial driver configuration and (re)start.
|
|
|
|
*
|
|
|
|
* @param[in] sdp pointer to a @p SerialDriver object
|
|
|
|
* @param[in] config the architecture-dependent serial driver configuration.
|
|
|
|
* If this parameter is set to @p NULL then a default
|
|
|
|
* configuration is used.
|
|
|
|
*
|
|
|
|
* @notapi
|
|
|
|
*/
|
|
|
|
void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
|
|
|
|
|
|
|
|
if (config == NULL)
|
|
|
|
config = &default_config;
|
|
|
|
|
|
|
|
if (sdp->state == SD_STOP) {
|
|
|
|
#if STM32_SERIAL_USE_USART1
|
|
|
|
if (&SD1 == sdp) {
|
|
|
|
rccEnableUSART1(FALSE);
|
2013-08-07 14:07:06 +00:00
|
|
|
nvicEnableVector(STM32_USART1_NUMBER, STM32_SERIAL_USART1_PRIORITY);
|
2013-08-04 13:38:53 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#if STM32_SERIAL_USE_USART2
|
|
|
|
if (&SD2 == sdp) {
|
|
|
|
rccEnableUSART2(FALSE);
|
2013-08-07 14:07:06 +00:00
|
|
|
nvicEnableVector(STM32_USART2_NUMBER, STM32_SERIAL_USART2_PRIORITY);
|
2013-08-04 13:38:53 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#if STM32_SERIAL_USE_USART3
|
|
|
|
if (&SD3 == sdp) {
|
|
|
|
rccEnableUSART3(FALSE);
|
2013-08-07 14:07:06 +00:00
|
|
|
nvicEnableVector(STM32_USART3_NUMBER, STM32_SERIAL_USART3_PRIORITY);
|
2013-08-04 13:38:53 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#if STM32_SERIAL_USE_UART4
|
|
|
|
if (&SD4 == sdp) {
|
|
|
|
rccEnableUART4(FALSE);
|
2013-08-07 14:07:06 +00:00
|
|
|
nvicEnableVector(STM32_UART4_NUMBER, STM32_SERIAL_UART4_PRIORITY);
|
2013-08-04 13:38:53 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#if STM32_SERIAL_USE_UART5
|
|
|
|
if (&SD5 == sdp) {
|
|
|
|
rccEnableUART5(FALSE);
|
2013-08-07 14:07:06 +00:00
|
|
|
nvicEnableVector(STM32_UART5_NUMBER, STM32_SERIAL_UART5_PRIORITY);
|
2013-08-04 13:38:53 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#if STM32_SERIAL_USE_USART6
|
|
|
|
if (&SD6 == sdp) {
|
|
|
|
rccEnableUSART6(FALSE);
|
2013-08-07 14:07:06 +00:00
|
|
|
nvicEnableVector(STM32_USART6_NUMBER, STM32_SERIAL_USART6_PRIORITY);
|
2013-08-04 13:38:53 +00:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
usart_init(sdp, config);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* @brief Low level serial driver stop.
|
|
|
|
* @details De-initializes the USART, stops the associated clock, resets the
|
|
|
|
* interrupt vector.
|
|
|
|
*
|
|
|
|
* @param[in] sdp pointer to a @p SerialDriver object
|
|
|
|
*
|
|
|
|
* @notapi
|
|
|
|
*/
|
|
|
|
void sd_lld_stop(SerialDriver *sdp) {
|
|
|
|
|
|
|
|
if (sdp->state == SD_READY) {
|
|
|
|
usart_deinit(sdp->usart);
|
|
|
|
#if STM32_SERIAL_USE_USART1
|
|
|
|
if (&SD1 == sdp) {
|
|
|
|
rccDisableUSART1(FALSE);
|
|
|
|
nvicDisableVector(STM32_USART1_NUMBER);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#if STM32_SERIAL_USE_USART2
|
|
|
|
if (&SD2 == sdp) {
|
|
|
|
rccDisableUSART2(FALSE);
|
|
|
|
nvicDisableVector(STM32_USART2_NUMBER);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#if STM32_SERIAL_USE_USART3
|
|
|
|
if (&SD3 == sdp) {
|
|
|
|
rccDisableUSART3(FALSE);
|
|
|
|
nvicDisableVector(STM32_USART3_NUMBER);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#if STM32_SERIAL_USE_UART4
|
|
|
|
if (&SD4 == sdp) {
|
|
|
|
rccDisableUART4(FALSE);
|
|
|
|
nvicDisableVector(STM32_UART4_NUMBER);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#if STM32_SERIAL_USE_UART5
|
|
|
|
if (&SD5 == sdp) {
|
|
|
|
rccDisableUART5(FALSE);
|
|
|
|
nvicDisableVector(STM32_UART5_NUMBER);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
#if STM32_SERIAL_USE_USART6
|
|
|
|
if (&SD6 == sdp) {
|
|
|
|
rccDisableUSART6(FALSE);
|
|
|
|
nvicDisableVector(STM32_USART6_NUMBER);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* HAL_USE_SERIAL */
|
|
|
|
|
|
|
|
/** @} */
|